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Gen4_R-Car_Trace32/2_Trunk/peram389x.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: AM3892/4, TMS320C6A8167/8 TSM320DM8165/6 TSM320DM8167/8 On-Chip Peripherals
; @Props: Released
; @Author: KRU, LEM, MAR, MPI, SLA
; @Changelog: 2011-01-27 MAR
; @Manufacturer: TI - Texas Instruments
; @Doc: sprugx7.pdf; am3892.pdf; tms320c6a8167.pdf; sprugx9.pdf
; sprugx8_public.pdf; tms320dm8168_public.pdf
; @Core: Cortex-A8
; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peram389x.per 12528 2020-11-12 13:57:39Z bschroefel $
; Known problems:
; 1. HD Video Processing Subsystem (HDVPSS) registers description NOT included in documentation!(Included for DM8165/DM8166/DM8167/DM8168)
; 2. Peripheral Component Interconnect Express (PCIe) only base address for Application Registers is described in documentation other are not described.
config 16. 8.
width 0x0b
base ad:0x00000000
tree "Core Registers (Cortex-A8)"
width 0x8
; --------------------------------------------------------------------------------
; Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup c15:0x0--0x0
line.long 0x0 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. " ARCH , Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline " "
hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number"
bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c15:0x100--0x100
line.long 0x0 "CTR,Cache Type Register"
bitfld.long 0x0 29.--31. " FORMAT ,Format" "Not ARMv7,Not ARMv7,Not ARMv7,Not ARMv7,ARMv7,Not ARMv7,Not ARMv7,Not ARMv7"
bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline " "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup c15:0x200--0x200
line.long 0x0 "TCMTR,Tighly-Coupled Memory Type Register"
bitfld.long 0x0 29.--31. " FORMAT ,Format" "ARMv6,ARMv6,ARMv6,ARMv6,ARMv7,ARMv6,ARMv6,ARMv6"
bitfld.long 0x0 16.--19. " DTCMS ,Data Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0.--3. " ITCMS ,Instruction Banks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c15:0x300--0x300
line.long 0x0 "TLBTR,TLB Type Register"
hexmask.long.byte 0x0 16.--23. 0x1 " ITLBLOCK ,Specifies the number of instruction TLB lockable entries"
hexmask.long.byte 0x0 8.--15. 0x1 " DTLBLOCK ,Specifies the number of unified or data TLB lockable entries"
bitfld.long 0x0 0. " S ,Unified or Separate TLBs" "Unified,Separate"
rgroup c15:0x400--0x400
line.long 0x0 "MPUTR,MPU type register"
rgroup c15:0x500--0x500
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitniy Level 2"
hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitniy Level 1"
hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitniy Level 0"
textline " "
rgroup c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup c15:0x0020++0x00
line.long 0x00 "ISAR0,Instruction Set Attribute Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0120++0x00
line.long 0x00 "ISAR1,Instruction Set Attribute Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0220++0x00
line.long 0x00 "ISAR2,Instruction Set Attribute Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0320++0x00
line.long 0x00 "ISAR3,Instruction Set Attribute Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup c15:0x0420++0x00
line.long 0x00 "ISAR4,Instruction Set Attribute Register 4"
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup c15:0x0010++0x00
line.long 0x00 "PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup c15:0x0110++0x00
line.long 0x00 "PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline " "
rgroup c15:0x0210++0x00
line.long 0x00 "DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline " "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup c15:0x0310++0x00
line.long 0x00 "AFR0,Auxiliary Feature Register 0"
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
tree.end
width 0x8
tree "System Control and Configuration"
group c15:0x1--0x1
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disabled,Enabled"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disabled,Enabled"
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
textline " "
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
textline " "
group c15:0x101--0x101
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " L2RD ,L2 hardware reset disable" "Enable,Disable"
bitfld.long 0x00 30. " L1RD ,L1 hardware reset disable" "Enable,Disable"
textline " "
bitfld.long 0x00 18. " CPISEL ,CP14/CP15 instruction serialization" "No,Yes"
bitfld.long 0x00 17. " CPWAI ,CP14/CP15 wait on idle" "No,Yes"
bitfld.long 0x00 16. " CPFL ,CP14/CP15 pipeline flush" "No,Yes"
textline " "
bitfld.long 0x00 15. " FETMCLK ,Force ETM clock" "No,Yes"
bitfld.long 0x00 14. " FNCLK ,Force NEON clock" "No,Yes"
bitfld.long 0x00 13. " FMCLK ,Force main clock" "No,Yes"
textline " "
bitfld.long 0x00 12. " FNSI ,Force NEON single issue" "No,Yes"
bitfld.long 0x00 11. " FLSSI ,Force load/store single issue" "No,Yes"
bitfld.long 0x00 10. " FSI ,Force single issue" "No,Yes"
textline " "
bitfld.long 0x00 9. " PLDNOP ,PLD executes as NOP" "Execute,NOP"
bitfld.long 0x00 8. " WFINOP ,WFI executes as NOP" "Execute,NOP"
textline " "
bitfld.long 0x00 7. " DBSM ,Disable branch size mispredicts" "Enable,Disable"
bitfld.long 0x00 6. " IBE ,Invalidate BTB Enable" "Disable,Enable"
textline " "
bitfld.long 0x00 5. " L1NEON ,NEON Data Caching Within the L1 Data Cache Enable" "Disable,Enable"
bitfld.long 0x00 4. " ASA ,Speculative Accesses on AXI Enable" "Disable,Enable"
textline " "
bitfld.long 0x00 3. " L1PE ,L1 Cache Parity Detection Enable" "Disable,Enable"
bitfld.long 0x00 1. " L2EN ,L2 Cache Enable" "Disable,Enable"
bitfld.long 0x00 0. " L1ALIAS ,L1 Data Cache Hardware Alias Checks Enable" "Enable,Disable"
group c15:0x201--0x201
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline " "
group c15:0x11--0x11
line.long 0x0 "SCR,Secure Configuration Register"
bitfld.long 0x00 5. " AW ,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed"
bitfld.long 0x00 4. " FW ,FW-bit controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " EA ,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor"
bitfld.long 0x00 2. " FIQ ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor"
textline " "
bitfld.long 0x00 1. " IRQ ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor"
bitfld.long 0x00 0. " NS ,Secure mode " "Secure,Non-secure"
group c15:0x111--0x111
line.long 0x0 "SDER,Secure Debug Enable Register"
bitfld.long 0x00 1. " SUNIDEN ,Non-Invasive Secure User Debug Enable bit" "Denied,Permitted"
bitfld.long 0x00 0. " SUIDEN ,Invasive Secure User Debug Enable bit" "Denied,Permitted"
group c15:0x0211++0x00
line.long 0x00 "NSACR,Non-Secure Access Control Register"
bitfld.long 0x00 18. " PLE ,PLE Registers Access in Nonsecure World" "Denied,Permitted"
bitfld.long 0x00 17. " TL ,Lockable Page Table Entries Allocation in Nonsecure World" "Denied,Permitted"
textline " "
bitfld.long 0x00 16. " CL ,Lockdown Entries Allocation Within the L2 Cache in Nonsecure World" "Denied,Permitted"
textline " "
bitfld.long 0x00 13. " CP13 ,Coprocessor 13 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 12. " CP12 ,Coprocessor 12 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 11. " CP11 ,Coprocessor 11 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 10. " CP10 ,Coprocessor 10 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 9. " CP9 ,Coprocessor 9 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 8. " CP8 ,Coprocessor 8 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 7. " CP7 ,Coprocessor 7 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 6. " CP6 ,Coprocessor 6 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 5. " CP5 ,Coprocessor 5 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 4. " CP4 ,Coprocessor 4 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 3. " CP3 ,Coprocessor 3 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 2. " CP2 ,Coprocessor 2 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
bitfld.long 0x00 1. " CP1 ,Coprocessor 1 in the Nonsecure World Access Permission" "Denied,Permitted"
bitfld.long 0x00 0. " CP0 ,Coprocessor 0 in the Nonsecure World Access Permission" "Denied,Permitted"
textline " "
group c15:0x000c++0x00
line.long 0x00 "VBAR,Secure or Nonsecure Vector Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " VBA ,Base Address"
group c15:0x10c--0x10c
line.long 0x0 "MVBAR,Monitor Vector Base Address Register"
hexmask.long.long 0x00 5.--31. 0x20 " MVBA , Monitor Vector Base Address"
textline " "
rgroup c15:0x1C--0x1C
line.long 0x0 "ISR,Interrupt status Register"
bitfld.long 0x0 8. " A ,Pending External Abort" "Not pending,Pending"
bitfld.long 0x0 7. " I ,Pending IRQ" "Not pending,Pending"
bitfld.long 0x0 6. " F ,Pending FIQ" "Not pending,Pending"
tree.end
width 0x0d
tree "Memory Management Unit"
width 8.
group c15:0x1--0x1
line.long 0x0 "SCTLR,Control Register"
bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. " NMFI ,DNonmaskable Fast Interrupt enable" "Disable,Enable"
textline " "
bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. " VE ,Vector Enable" "Not vectored,Vectored"
bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline " "
bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable"
textline " "
bitfld.long 0x0 2. " C ,Enable unified cache or data cache" "Disable,Enable"
bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. " M ,MMU or Protection Unit" "Disable,Enable"
textline " "
group c15:0x0002++0x00
line.long 0x00 "TTBR0,Translation Table Base Register 0"
hexmask.long 0x00 14.--31. 0x4000 " TTB0 ,Translation Table Base Address"
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
textline " "
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
group c15:0x0102++0x00
line.long 0x00 "TTBR1,Translation Table Base Register 1"
hexmask.long 0x00 14.--31. 0x4000 " TTB1 ,Translation Table Base Address"
bitfld.long 0x00 3.--4. " RGN ,Outer Cacheable Attributes for Page Table Walking" "Noncacheable,Back/allocated,Through,Back/not allocated"
textline " "
bitfld.long 0x00 1. " S ,Page Table Walk to Shared Memory" "Nonshared,Shared"
bitfld.long 0x00 0. " C ,Page Table Walk Inner Cacheable" "Noncacheable,Cacheable"
group c15:0x0202++0x00
line.long 0x00 "TTBCR,Translation Table Base Control Register"
bitfld.long 0x00 5. " PD1 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 1" "Enable,Disable"
bitfld.long 0x00 4. " PD0 ,Page Table Walk on a TLB Miss When Using Translation Table Base Register 0" "Enable,Disable"
bitfld.long 0x0 0.--2. " N ,Translation Table Base Register 0 page table boundary size" "Off,0x80000000,0x40000000,0x20000000,0x10000000,0x08000000,0x04000000,0x02000000"
textline " "
group c15:0x3--0x3
line.long 0x0 "DACR,Domain Access Control Register"
bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
textline " "
bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
textline " "
group c15:0x0005++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write"
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/decode,Reserved,Imprecise/parity/ECC,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Imprecise/external/slave,?..."
group c15:0x0006++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
group c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10. 12. " STATUS ,Generated Exception Type" "Reserved,Reserved,Debug,Access/section,Reserved,Translation/section,Access/page,Translation/page,Precise/decode,Domain/section,Reserved,Domain/page,L1/external/decode,Permission/section,L2/external/decode,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/parity,Reserved,Reserved,Reserved,L1/parity,Reserved,L2/parity,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Precise/slave,Reserved,Reserved,Reserved,L1/external/slave,Reserved,L2/external/slave,?..."
group c15:0x0206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
group c15:0x0015++0x00
line.long 0x00 "DAFSR,Data Auxiliary Fault Status Register"
group c15:0x0115++0x00
line.long 0x00 "IAFSR,Instruction Auxiliary Fault Status Register"
textline " "
group c15:0x002A--0x002A
line.long 0x00 "PMRRR,Primary Memory Region Remap Register"
bitfld.long 0x00 19. " NS1 ,Shareable Attribute Remap when S=1 for Normal Regions" "Remapped,Not remapped"
bitfld.long 0x00 18. " NS0 ,Shareable Attribute Remap when S=0 for Normal Regions" "Not remapped,Remapped"
textline " "
bitfld.long 0x00 17. " DS1 ,Shareable Attribute Remap when S=1 for Device regions" "Remapped,Not remapped"
bitfld.long 0x00 16. " DS0 ,Shareable Attribute Remap when S=0 for Device regions" "Not remapped,Remapped"
textline " "
bitfld.long 0x00 14.--15. " TR7 ,{TEX[0] C B} = b111 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 12.--13. " TR6 ,{TEX[0] C B} = b110 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 10.--11. " TR5 ,{TEX[0] C B} = b101 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 8.--9. " TR4 ,{TEX[0] C B} = b100 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 6.--7. " TR3 ,{TEX[0] C B} = b011 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 4.--5. " TR2 ,{TEX[0] C B} = b010 Remap" "Strongly ordered,Device,Normal,UNP"
textline " "
bitfld.long 0x00 2.--3. " TR1 ,{TEX[0] C B} = b001 Remap" "Strongly ordered,Device,Normal,UNP"
bitfld.long 0x00 0.--1. " TR0 ,{TEX[0] C B} = b000 Remap" "Strongly ordered,Device,Normal,UNP"
group c15:0x012A--0x012A
line.long 0x00 "NMRR,Normal Memory Remap Register"
bitfld.long 0x00 30.--31. " OR7 ,Outer Attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 28.--29. " OR6 ,Outer Attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 26.--27. " OR5 ,Outer Attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 24.--25. " OR4 ,Outer Attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 22.--23. " OR3 ,Outer Attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 20.--21. " OR2 ,Outer Attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 18.--19. " OR1 ,Outer Attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 16.--17. " OR0 ,Outer Attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 14.--15. " IR7 ,Inner attribute for {TEX[0] C B} = b111 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 12.--13. " IR6 ,Inner attribute for {TEX[0] C B} = b110 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 10.--11. " IR5 ,Inner attribute for {TEX[0] C B} = b101 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 8.--9. " IR4 ,Inner attribute for {TEX[0] C B} = b100 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 6.--7. " IR3 ,Inner attribute for {TEX[0] C B} = b011 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 4.--5. " IR2 ,Inner attribute for {TEX[0] C B} = b010 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
bitfld.long 0x00 2.--3. " IR1 ,Inner attribute for {TEX[0] C B} = b001 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
bitfld.long 0x00 0.--1. " IR0 ,Inner attribute for {TEX[0] C B} = b000 Remap" "Noncacheable,Write-back allocate,Write-through,Write-back no allocate"
textline " "
group c15:0x000d++0x00
line.long 0x00 "FCSEPID,FCSE PID Register"
hexmask.long.byte 0x00 25.--31. 1. " FCSEPID ,Process for Fast Context Switch Identification and Specification"
group c15:0x10d--0x10d
line.long 0x0 "CONTEXT,Context ID Register"
hexmask.long.tbyte 0x0 8.--31. 1. " PROCID ,Process ID"
hexmask.long.byte 0x0 0.--7. 1. " ASID ,Application Space ID"
group c15:0x020d++0x00
line.long 0x00 "URWTPID,User Read/Write Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " URWTPID ,User Read/Write Thread and Process ID"
group c15:0x030d++0x00
line.long 0x00 "UROTPID,User Read-Only Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " UROTPID ,User Read-Only Thread and Process ID"
group c15:0x040d++0x00
line.long 0x00 "POTPID,Privileged Only Thread and Process ID Register"
hexmask.long 0x00 0.--31. 1. " POTPID ,Privileged Only Thread and Process ID"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup c15:0x1100--0x1100
line.long 0x0 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline " "
bitfld.long 0x00 21.--23. " CTYPE8 ,Cache type for levels 8" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 18.--20. " CTYPE7 ,Cache type for levels 7" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 15.--17. " CTYPE6 ,Cache type for levels 6" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 12.--14. " CTYPE5 ,Cache type for levels 5" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 9.--11. " CTYPE4 ,Cache type for levels 4" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 6.--8. " CTYPE3 ,Cache type for levels 3" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
textline " "
bitfld.long 0x00 3.--5. " CTYPE2 ,Cache type for levels 2" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
bitfld.long 0x00 0.--2. " CTYPE1 ,Cache type for levels 1" "No cache,I-cache,D-cache,Separate I/D,Unified,?..."
rgroup c15:0x1000--0x1000
line.long 0x0 "CCSIDR,Current Cache Size ID Register"
bitfld.long 0x00 31. " WT ,Write-Through" "Not Supported,Supported"
bitfld.long 0x00 30. " WB ,Write-Back" "Not Supported,Supported"
textline " "
bitfld.long 0x00 29. " RA ,Read-Allocate" "Not Supported,Supported"
bitfld.long 0x00 28. " WA ,Write-Allocate" "Not Supported,Supported"
textline " "
hexmask.long.word 0x00 13.--27. 1. 1. " SETS ,Number of Sets"
hexmask.long.word 0x00 3.--12. 1. 1. " ASSOC ,Associativity"
textline " "
bitfld.long 0x00 0.--2. " LSIZE ,Line Size" "4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words"
group c15:0x2000--0x2000
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL ,Level" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
bitfld.long 0x00 0. " IND ,Instruction/Not Data" "Data/unified,Instruction"
tree.end
width 0x8
tree "L2 Cache Control and Configuration"
group c15:0x1009++0x00
line.long 0x00 "L2CLR,L2 Cache Lockdown Register"
bitfld.long 0x00 7. " LOCK_way_7 ,Way 7 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 6. " LOCK_way_6 ,Way 6 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 5. " LOCK_way_5 ,Way 5 of the L2 Cache Lockdown" "Not locked,Locked"
textline " "
bitfld.long 0x00 4. " LOCK_way_4 ,Way 4 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 3. " LOCK_way_3 ,Way 3 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 2. " LOCK_way_2 ,Way 2 of the L2 Cache Lockdown" "Not locked,Locked"
textline " "
bitfld.long 0x00 1. " LOCK_way_1 ,Way 1 of the L2 Cache Lockdown" "Not locked,Locked"
bitfld.long 0x00 0. " LOCK_way_0 ,Way 0 of the L2 Cache Lockdown" "Not locked,Locked"
group c15:0x1209++0x00
line.long 0x00 "L2CACR,L2 Cache Auxiliary Control Register"
bitfld.long 0x00 28. " ECCP ,ECC/Parity Selection" "Parity,ECC"
bitfld.long 0x00 27. " PLDFD ,PLD Forwarding to LS Request Disable" "Enabled,Disabled"
bitfld.long 0x00 26. " PLDD ,PLD Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 25. " WCD ,Write Combining Disable" "Enabled,Disabled"
bitfld.long 0x00 24. " WADD ,External Linefill When Storing an Entire Line With Write Allocate Permission Disable" "Enabled,Disabled"
bitfld.long 0x00 23. " WACD ,Combining of Data in the L2 Write Combining Buffers Disable" "Enabled,Disabled"
textline " "
bitfld.long 0x00 22. " WAD ,Allocate on Write Miss in L2 Disable" "Enabled,Disabled"
bitfld.long 0x00 21. " PECCE ,Parity/ECC Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " L2I ,L2 Inner" "Outer,Inner"
textline " "
bitfld.long 0x00 6.--8. " TRAML ,Program Tag RAM Latency" "2 cycles,2 cycles,3 cycles,4 cycles,4 cycles,4 cycles,4 cycles,4 cycles"
bitfld.long 0x00 0.--3. " DRAML ,Program Data RAM Latency" "3 cycles,3 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles,8 cycles,9 cycles,10 cycles,11 cycles,12 cycles,13 cycles,13 cycles,13 cycles,13 cycles"
textline " "
rgroup c15:0x000b++0x00
line.long 0x00 "PLEISR0,PLE Identification and Status Register 0"
bitfld.long 0x00 1. " CH1P ,Channel 1 Present" "Not present,Present"
bitfld.long 0x00 0. " CH0P ,Channel 0 Present" "Not present,Present"
rgroup c15:0x010b++0x00
line.long 0x00 "PLEISR1,PLE Identification and Status Register 1"
bitfld.long 0x00 1. " CH1Q ,Channel 1 Queue" "Not queued,Queued"
bitfld.long 0x00 0. " CH0Q ,Channel 0 Queue" "Not queued,Queued"
rgroup c15:0x020b++0x00
line.long 0x00 "PLEISR2,PLE Identification and Status Register 2"
bitfld.long 0x00 1. " CH1R ,Channel 1 Run" "Not running,Running"
bitfld.long 0x00 0. " CH0R ,Channel 0 Run" "Not running,Running"
rgroup c15:0x030b++0x00
line.long 0x00 "PLEISR3,PLE Identification and Status Register 3"
bitfld.long 0x00 1. " CH1I ,Channel 1 Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 0. " CH0I ,Channel 0 Interrupt" "No interrupt,Interrupt"
group c15:0x001b++0x00
line.long 0x00 "PLEUAR,PLE User Accessibility Register"
bitfld.long 0x00 1. " U1 ,User Mode Process Access Registers for Channel 1 Permission" "Not permitted,Permitted"
bitfld.long 0x00 0. " U0 ,User Mode Process Access Registers for Channel 0 Permission" "Not permitted,Permitted"
group c15:0x002b++0x00
line.long 0x00 "PLECNR,PLE Channel Number Register"
bitfld.long 0x00 0. " CN ,PLE Channel Selection" "Channel 0,Channel 1"
wgroup c15:0x003b++0x00
line.long 0x00 "PLEER0,PLE Enable Register 0"
hexmask.long 0x00 0.--31. 1. " PLEE_STOP ,PLE Enable Stop"
wgroup c15:0x013b++0x00
line.long 0x00 "PLEER1,PLE Enable Register 1"
hexmask.long 0x00 0.--31. 1. " PLEE_START ,PLE Enable Start"
wgroup c15:0x023b++0x00
line.long 0x00 "PLEER2,PLE Enable Register 2"
hexmask.long 0x00 0.--31. 1. " PLEES_CLEAR ,PLE Enable Clear"
group c15:0x004b++0x00
line.long 0x00 "PLECR,PLE Control Register"
bitfld.long 0x00 30. " DT ,Transfer Direction" "Memory->cache,Cache->memory"
bitfld.long 0x00 29. " IC ,Interrupt on Completion of the PLE Transfer" "No interrupt,Interrupt"
bitfld.long 0x00 28. " IE ,Interrupt on an Error" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 26. " UM ,Permission Checks Type" "Privileged,User"
bitfld.long 0x00 0.--2. " Wy ,L2 Cache Way for Filling Data" "Way 0,Way 1,Way 2,Way 3,Way 4,Way 5,Way 6,Way 7"
textline " "
group c15:0x005b++0x00
line.long 0x00 "PLEISAR,PLE Internal Start Address Register"
hexmask.long 0x00 0.--31. 1. " PLEISA ,PLE Internal Start Address"
group c15:0x007b++0x00
line.long 0x00 "PLEIEAR,PLE Internal End Address Register"
hexmask.long.word 0x00 6.--17. 1. " Lines ,Number of Cache Lines Transferred"
rgroup c15:0x008b++0x00
line.long 0x00 "PLECSR,PLE Channel Status Register"
hexmask.long.byte 0x00 2.--8. 1. " EC ,External Address Error Status"
bitfld.long 0x00 0.--1. " Status ,PLE Channel Status" "Idle,Queued,Running,Complete/error"
group c15:0x00fb++0x00
line.long 0x00 "PLECIDR,PLE Context ID Register"
hexmask.long.tbyte 0x00 8.--31. 1. " PROCID ,ASID Extension to Form the Process ID and Current Process Identification"
hexmask.long.byte 0x00 0.--7. 1. " ASID ,ASID of the Current Process and the Current ASID Identification"
tree.end
width 12.
tree "System Performance Monitor"
group c15:0xC9--0xC9
line.long 0x0 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code"
bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. " DP ,Disable CCNT when prohibited" "Enabled,Disabled"
textline " "
bitfld.long 0x00 4. " X ,Export Enabled" "Disabled,Enabled"
bitfld.long 0x00 3. " D ,Clock Divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. " C ,Clock Counter Reset" "No action,Reset"
bitfld.long 0x00 1. " P ,Performance Counter Reset" "No action,Reset"
textline " "
bitfld.long 0x00 0. " E ,Counters Enable" "Disabled,Enabled"
group c15:0x1C9--0x1C9
line.long 0x0 "CNTENS,Count Enable Set Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group c15:0x2C9--0x2C9
line.long 0x0 "CNTENC,Count Enable Clear Register"
eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,PMN3 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled"
group c15:0x3C9--0x3C9
line.long 0x0 "FLAG,Overflow Flag Status Register"
eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00 3. " P3 ,PMN3 overflowed" "No overflow,Overflow"
eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow"
group c15:0x4C9--0x4C9
line.long 0x0 "SWINCR,Software Increment Register"
eventfld.long 0x00 3. " P3 ,Increment PMN3" "No action,Increment"
eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment"
eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment"
eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment"
group c15:0x5C9--0x5C9
line.long 0x0 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Selection value" "CNT0,CNT1,CNT2,CNT3,..."
group c15:0xD9--0xD9
line.long 0x0 "PMCCNTR,Cycle Count Register"
group c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group c15:0x02d9++0x00
line.long 0x00 "PMCNT,Performance Monitor Count Register"
group c15:0xE9--0xE9
line.long 0x0 "PMUSERENR,User Enable Register"
bitfld.long 0x00 0. " EN ,User Mode Enable" "Disabled,Enabled"
group c15:0x1E9--0x1E9
line.long 0x0 "INTENS,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
group c15:0x2E9--0x2E9
line.long 0x0 "INTENC,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 3. " P3 ,Interrupt on PMN3 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
tree.end
width 8.
tree "Debug Registers"
width 10.
rgroup c14:0x000--0x000
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
bitfld.long 0x0 20.--23. " CONTEXT ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
bitfld.long 0x0 16.--19. " VERSION ,Debug Architecture Version" "Reserved,ARMv6,ARMv6.1,ARMv7,?..."
textline " "
bitfld.long 0x0 13. " PCSAMPLE ,PC Sample register implemented" "Not implemented,Implemented"
bitfld.long 0x0 12. " SECURITY ,Security Extensions implemented" "Not implemented,Implemented"
textline " "
bitfld.long 0x0 4.--7. " VARIANT ,Implementation-defined Variant Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 0.--3. " REVISION ,Implementation-defined Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
width 10.
group c14:0x22--0x22
line.long 0x0 "DBGDSCR,Debug Status and Control Register"
bitfld.long 0x0 30. " DTRRXFULL ,The DTRRX Full Flag" "Empty,Full"
bitfld.long 0x0 29. " DTRTXfull ,The DTRTX Full Flag" "Empty,Full"
textline " "
bitfld.long 0x00 27. " DTRRXFULL_L ,The DTRRX Full Flag 1" "Empty,Full"
bitfld.long 0x00 26. " DTRTXfull_l ,The DTRTX Full Flag 1" "Empty,Full"
textline " "
bitfld.long 0x0 25. " SPA ,Sticky Pipeline Advance" "No effect,Instruction retired"
bitfld.long 0x0 24. " IC ,Instruction Complete" "Executing,Not executing"
textline " "
bitfld.long 0x0 20.--21. " DTR ,DTR Access Mode" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x0 19. " NSWS ,Imprecise Data Aborts discarded" "Not discarded,Discarded"
textline " "
bitfld.long 0x0 18. " NS ,Non-secure World Status" "Secured,Not secured"
bitfld.long 0x0 17. " nSPNIDEN ,Secure Non-invasive Debug Disabled" "Enabled,Disabled"
textline " "
bitfld.long 0x0 16. " NSPIDEN ,Secure Invasive Debug Disabled" "Enabled,Disabled"
bitfld.long 0x0 15. " MONITOR ,Monitor Debug-mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 14. " HDEn ,Halting Debug-mode enable" "Disabled,Enabled"
bitfld.long 0x0 13. " EXECUTE ,Execute instruction enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0 12. " COMMS ,User mode access to Comms Channel disable" "Enabled,Disabled"
bitfld.long 0x0 11. " IntDis ,Disable Interrupts" "Enabled,Disabled"
textline " "
bitfld.long 0x0 10. " DBGACK ,Force Debug Acknowledge" "Not forced,Forced"
bitfld.long 0x0 8. " UEXT ,Sticky Undefined Exception" "No exception,Exception"
textline " "
bitfld.long 0x0 7. " IABORT ,Sticky Imprecise Abort" "Not aborted,Aborted"
bitfld.long 0x0 6. " PABORT ,Sticky Precise Abort" "Not aborted,Aborted"
textline " "
bitfld.long 0x0 2.--5. " MOE ,Method of Debug Entry" "Debug Entry,Breakpoint,Imprecise Watchpoint,BKPT instruction,External debug,Vector catch,Reserved,Reserved,OS Unlock,?..."
bitfld.long 0x0 1. " RESTARTED ,Core Restarted" "Debug not exited,Debug exited"
textline " "
bitfld.long 0x0 0. " HALTED ,Core Halted" "Normal state,Debug state"
textline " "
width 10.
if (((data.long(c14:0x00))&0x01000)==0x00000)
group c14:0x007--0x007
line.long 0x0 "DBGVCR,Vector Catch Register"
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
textline " "
bitfld.long 0x0 4. " DABORT ,Vector Catch Enable Data Abort" "Disabled,Enabled"
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
textline " "
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
textline " "
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
else
group c14:0x007--0x007
line.long 0x0 "DBGVCR,Vector Catch Register"
bitfld.long 0x0 31. " FIQN ,Vector Catch Enable FIQ (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 30. " IRQN ,Vector Catch Enable IRQ (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 28. " DABORTN ,Vector Catch Enable Data Abort (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 27. " PABORTN ,Vector Catch Enable Prefetch abort (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 26. " SWIN ,Vector Catch Enable SWI (Non-secure)" "Disabled,Enabled"
bitfld.long 0x0 25. " UNDEFS ,Vector Catch Enable Undefined (Non-secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 15. " FIQS ,Vector Catch Enable FIQ (Secure)" "Disabled,Enabled"
bitfld.long 0x0 14. " IRQS ,Vector Catch Enable IRQ (Secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 12. " DABORTS ,Vector Catch Enable Data Abort (Secure)" "Disabled,Enabled"
bitfld.long 0x00 11. " PABORTS ,Vector Catch Enable Prefetch abort (Secure)" "Disabled,Enabled"
textline " "
bitfld.long 0x0 10. " SMI ,Vector Catch Enable SMI (Secure)" "Disabled,Enabled"
bitfld.long 0x0 7. " FIQ ,Vector Catch Enable FIQ" "Disabled,Enabled"
textline " "
bitfld.long 0x0 6. " IRQ ,Vector Catch Enable IRQ" "Disabled,Enabled"
bitfld.long 0x0 4. " DABORT0 ,Vector Catch Enable Data Abort" "Disabled,Enabled"
textline " "
bitfld.long 0x0 3. " PABORT ,Vector Catch Enable Prefetch Abort" "Disabled,Enabled"
bitfld.long 0x0 2. " SWI ,Vector Catch Enable SWI" "Disabled,Enabled"
textline " "
bitfld.long 0x0 1. " UNDEF ,Vector Catch Enable Undefined Instruction" "Disabled,Enabled"
bitfld.long 0x0 0. " RESET ,Vector Catch Enable Reset" "Disabled,Enabled"
endif
width 10.
hgroup c14:0x020--0x020
hide.long 0x0 "DBGDTRRX,Debug Receive Register (External View)"
in
group c14:0x023--0x023
line.long 0x0 "DBGDTRTX,Debug Transmit Register (External View)"
group c14:0x09++0x00
line.long 0x00 "DBGECR,Event Catch Register"
bitfld.long 0x00 0. " OSUC ,OS Unlock Catch" "Disabled,Enabled"
group c14:0x0a++0x00
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT ,Not Write-Through" "Forced,Normal"
bitfld.long 0x00 0. " DUCL ,Data and Unified Cache Linefill" "Disabled,Normal"
wgroup c14:0x21++0x00
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup c14:0x24++0x00
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance" "Not cleared,Cleared"
bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions" "Not cleared,Cleared"
textline " "
bitfld.long 0x00 1. " RR ,Restart Request" "Not requested,Requested"
bitfld.long 0x00 0. " HR ,Halt Request" "Not requested,Requested"
wgroup c14:0xc0++0x00
line.long 0x00 "DBGOSLAR,Operating System Lock Access Register"
rgroup c14:0xc1++0x00
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 2. " 32_BA ,32-Bit Access" "Not required,Required"
bitfld.long 0x00 1. " LB ,Locked Bit" "Not locked,Locked"
bitfld.long 0x00 0. " LIB ,Lock Implemented Bit" "Not implemented,Implemented"
group c14:0xc2++0x00
line.long 0x00 "DBGOSSRR,Operating System Save and Restore Register"
hexmask.long 0x00 0.--31. 1. " OSSR ,OS Save and Restore"
group c14:0xc4++0x00
line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register"
bitfld.long 0x00 2. " HIR ,Hold Internal Reset" "Not held,Held"
bitfld.long 0x00 1. " FIR ,Force Internal Reset" "Not forced,Forced"
bitfld.long 0x00 0. " NPD ,No Power-Down" "DBGNOPWRDWN low,DBGNOPWRDWN high"
hgroup c14:0xc5++0x00
hide.long 0x00 "DBGPRSR,Device Power-Down and Reset Status Register"
in
width 11.
tree "Processor Identifier Registers"
rgroup c14:0x340--0x340
line.long 0x00 "CPUID,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number"
textline " "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH , Architecture"
hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
textline " "
hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision"
rgroup c14:0x341--0x341
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup c14:0x343--0x343
line.long 0x00 "TLBTYPE,TLB Type Register"
hexmask.long.byte 0x0 16.--23. 0x1 " ILSIZE ,Specifies the number of instruction TLB lockable entries"
hexmask.long.byte 0x0 8.--15. 0x1 " DLSIZE ,Specifies the number of unified or data TLB lockable entries"
textline " "
bitfld.long 0x0 0. " U ,Unified or separate instruction TLBs" "Unified,Separate"
rgroup c14:0x348--0x348
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup c14:0x349--0x349
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup c14:0x34a--0x34a
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup c14:0x34b--0x34b
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
hexmask.long 0x00 0.--31. 1. " AF ,Auxiliary Feature"
rgroup c14:0x34c--0x34c
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup c14:0x34d--0x34d
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup c14:0x34e--0x34e
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline " "
bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup c14:0x34f--0x34f
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup c14:0x350--0x350
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x351--0x351
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " ENDI ,Endian Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x352--0x352
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x353--0x353
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup c14:0x354--0x354
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline " "
bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup c14:0x355--0x355
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 0xC
tree "Coresight Management Registers"
width 17.
group c14:0x03bd++0x00
line.long 0x00 "DBGITCTRL_IOC,Integration Internal Output Control Register"
bitfld.long 0x00 5. " I_DBGTRIGGER ,Internal DBGTRIGGER" "0,1"
bitfld.long 0x00 4. " I_DBGRESTARTED ,Internal DBGRESTARTED" "0,1"
textline " "
bitfld.long 0x00 3. " I_nPMUIRQ ,Internal nPMUIRQ" "0,1"
bitfld.long 0x00 2. " InternalCOMMTX ,Internal COMMTX" "0,1"
textline " "
bitfld.long 0x00 1. " I_COMMRX ,Internal COMMRX" "0,1"
bitfld.long 0x00 0. " I_DBGACK ,Internal DBGACK" "0,1"
group c14:0x03be++0x00
line.long 0x00 "DBGITCTRL_EOC,Integration External Output Control Register"
bitfld.long 0x00 7. " NDMAEXTERRIQ ,External nDMAEXTERRIRQ" "0,1"
bitfld.long 0x00 6. " nDMASIRQ ,External nDMASIRQ" "0,1"
textline " "
bitfld.long 0x00 5. " NDMAIRQ ,External nDMAIRQ" "0,1"
bitfld.long 0x00 4. " nPMUIRQ ,External nPMUIRQ" "0,1"
textline " "
bitfld.long 0x00 3. " STANDBYWFI ,External STANDBYWFI" "0,1"
bitfld.long 0x00 2. " COMMTX ,External COMMTX" "0,1"
textline " "
bitfld.long 0x00 1. " COMMRX ,External COMMRX" "0,1"
bitfld.long 0x00 0. " DBGACK ,External DBGACK" "0,1"
rgroup c14:0x03bf++0x00
line.long 0x00 "DBGITCTRL_IS,Integration Input Status Register"
bitfld.long 0x00 11. " CTI_DBGRESTART ,CTI Debug Restart" "0,1"
bitfld.long 0x00 10. " CTI_EDBGRQ ,CTI Debug Request" "0,1"
textline " "
bitfld.long 0x00 9. " CTI_PMUEXTIN[1] ,CTI PMUEXTIN[1] Signal" "0,1"
bitfld.long 0x00 8. " CTI_PMUEXTIN[0] ,CTI PMUEXTIN[0] Signal" "0,1"
textline " "
bitfld.long 0x00 2. " nFIQ ,nFIQ Input" "0,1"
bitfld.long 0x00 1. " nIRQ ,nIRQ Input" "0,1"
textline " "
bitfld.long 0x00 0. " EDBGRQ ,EDBGRQ Input" "0,1"
group c14:0x3c0--0x3c0
line.long 0x0 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x0 0. " IME ,Integration Mode Enable" "Disabled,Enabled"
group c14:0x3e8--0x3e8
line.long 0x0 "DBGCLAIMSET,Claim Tag Set Register"
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Set"
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Set"
textline " "
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Set"
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Set"
textline " "
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Set"
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Set"
textline " "
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Set"
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Set"
group c14:0x3e9--0x3e9
line.long 0x0 "DBGCLAIMCLR,Claim Tag Clear Register"
bitfld.long 0x0 7. " CT7 ,Claim Tag 7" "No Effect,Cleared"
bitfld.long 0x0 6. " CT6 ,Claim Tag 6" "No Effect,Cleared"
textline " "
bitfld.long 0x0 5. " CT5 ,Claim Tag 5" "No Effect,Cleared"
bitfld.long 0x0 4. " CT4 ,Claim Tag 4" "No Effect,Cleared"
textline " "
bitfld.long 0x0 3. " CT3 ,Claim Tag 3" "No Effect,Cleared"
bitfld.long 0x0 2. " CT2 ,Claim Tag 2" "No Effect,Cleared"
textline " "
bitfld.long 0x0 1. " CT1 ,Claim Tag 1" "No Effect,Cleared"
bitfld.long 0x0 0. " CT0 ,Claim Tag 0" "No Effect,Cleared"
wgroup c14:0x3ec--0x3ec
line.long 0x0 "DBGLAR,Lock Access Register"
rgroup c14:0x3ed--0x3ed
line.long 0x0 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " NTT ,Not 32-bit access" "32-bit,Not 32-bit"
bitfld.long 0x00 1. " SLK ,Software Lock status" "Not locked,Locked"
textline " "
bitfld.long 0x00 0. " SLI ,Software Lock Implemented" "Not implemented,Implemented"
width 17.
rgroup c14:0x3ee--0x3ee
line.long 0x0 "DBGAUTHSTATUS,Debug Authentication Status Register"
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enable (DBGEN OR NIDEN) AND (SPIDEN OR SPNIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " SI ,Secure invasive debug features implementation" "No effect,Implemented"
bitfld.long 0x00 4. " SE ,Secure invasive debug enable (DBGEN AND SPIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enable (DBGEN OR NIDEN)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implementation" "Not implemented,Implemented"
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enable (DBGEN)" "Disabled,Enabled"
width 17.
hgroup c14:0x3f2--0x3f2
hide.long 0x0 "DBGDEVID,Device Identifier (RESERVED)"
rgroup c14:0x3f3--0x3f3
line.long 0x0 "DBGDEVTYPE,Device Type"
bitfld.long 0x00 4.--7. " T ,Sub type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. " C ,Main class" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup c14:0x3f8--0x3f8
line.long 0x00 "DBGPID0,Debug Peripheral ID 0"
hexmask.long.byte 0x00 0.--7. 1. " PN[7:0] ,Part Number [7:0]"
rgroup c14:0x3f9--0x3f9
line.long 0x00 "DBGPID1,Debug Peripheral ID 1"
hexmask.long.byte 0x00 4.--7. 1. " JEPID[3:0] ,JEP Identity Code[3:0]"
hexmask.long.byte 0x00 0.--3. 1. " PN[11:8] ,Part Number [11:8]"
rgroup c14:0x3fa--0x3fa
line.long 0x00 "DBGPID2,Debug Peripheral ID 2"
hexmask.long.byte 0x00 4.--7. 1. " REV ,Revision"
bitfld.long 0x00 3. " UJEPCODE ,Uses JEP Code" "Disabled,Enabled"
hexmask.long.byte 0x00 0.--2. 1. " JEPID[6:4] ,JEP Identity Code[6:4]"
rgroup c14:0x3fb--0x3fb
line.long 0x00 "DBGPID3,Debug Peripheral ID 3"
hexmask.long.byte 0x00 4.--7. 1. " REVAND ,Manufacturing revision"
hexmask.long.byte 0x00 0.--3. 1. " CM ,Customer modified"
rgroup c14:0x3f4--0x3f4
line.long 0x00 "DBGPID4,Debug Peripheral ID 4"
hexmask.long.byte 0x00 4.--7. 1. " 4KB_COUNT ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CONT_CODE ,JEP 106 Continuation code"
rgroup c14:0x3fc--0x3fc
line.long 0x00 "DBGCID0,Debug Component ID 0"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 0"
rgroup c14:0x3fd--0x3fd
line.long 0x00 "DBGCID1,Debug Component ID 1"
hexmask.long.byte 0x00 4.--7. 1. " CC ,Component class"
hexmask.long.byte 0x00 0.--3. 1. " PREAMBLE ,Preamble byte 1"
rgroup c14:0x3fe--0x3fe
line.long 0x00 "DBGCID2,Debug Component ID 2"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 2"
rgroup c14:0x3ff--0x3ff
line.long 0x00 "DBGCID3,Debug Component ID 3"
hexmask.long.byte 0x00 0.--7. 1. " PREAMBLE ,Preamble byte 3"
tree.end
tree.end
width 7.
tree "Breakpoint Registers"
group c14:0x40++0x00
line.long 0x00 "BVR0,Breakpoint Value Register 0"
group c14:0x50++0x00
line.long 0x00 "BCR0,Breakpoint Control Register 0"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x41++0x00
line.long 0x00 "BVR1,Breakpoint Value Register 1"
group c14:0x51++0x00
line.long 0x00 "BCR1,Breakpoint Control Register 1"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x42++0x00
line.long 0x00 "BVR2,Breakpoint Value Register 2"
group c14:0x52++0x00
line.long 0x00 "BCR2,Breakpoint Control Register 2"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x43++0x00
line.long 0x00 "BVR3,Breakpoint Value Register 3"
group c14:0x53++0x00
line.long 0x00 "BCR3,Breakpoint Control Register 3"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Reserved,Reserved,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x44++0x00
line.long 0x00 "BVR4,Breakpoint Value Register 4"
group c14:0x54++0x00
line.long 0x00 "BCR4,Breakpoint Control Register 4"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
group c14:0x45++0x00
line.long 0x00 "BVR5,Breakpoint Value Register 5"
group c14:0x55++0x00
line.long 0x00 "BCR5,Breakpoint Control Register 5"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline " "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled"
tree.end
width 6.
tree "Watchpoint Control Registers"
group c14:0x60++0x00
line.long 0x00 "WVR0,Watchpoint Value Register 0"
hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0"
group c14:0x70--0x70
line.long 0x0 "WCR0,Watchpoint Control Register 0"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group c14:0x61++0x00
line.long 0x00 "WVR1,Watchpoint Value Register 1"
hexmask.long 0x00 2.--31. 0x04 " WA1 ,Watchpoint Address 1"
group c14:0x71--0x71
line.long 0x0 "WCR1,Watchpoint Control Register 1"
bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled"
textline " "
bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline " "
bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0 ,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0 ,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0 ,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0 ,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0 ,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0 ,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0 ,1"
textline " "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any"
textline " "
bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled"
group c14:0x006--0x006
line.long 0x0 "WFAR,Watchpoint Fault Address Register"
hexmask.long.long 0x00 1.--31. 0x02 " WFAR ,Address of the watchpointed instruction"
tree.end
tree.end
sif (cpuis("C6A816*")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168"))
tree "DEMMU (DSP/EDMA Memory Management Unit)"
base ad:0x48010000
width 18.
rgroup.long 0x00++0x3
line.long 0x00 "MMU_REVISION,IP Revision Code"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!cpuis("DM8165"))&&(!cpuis("DM8166"))&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")&&(!cpuis("DM8167"))&&(!cpuis("DM8168"))&&(!cpuis("DM8165DSP"))&&(!cpuis("DM8166DSP"))&&(!cpuis("DM8167DSP"))&&(!cpuis("DM8168DSP"))&&(!cpuis("DRA62*")))
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP Revision"
endif
group.long 0x10++0x3
line.long 0x00 "MMU_SYSCONFIG,Various Parameters Of The Interconnect Interface"
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity during wake-up mode" "Switched off,?..."
textline " "
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force,No idle,Smart,?..."
textline " "
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Always,Never"
textline " "
bitfld.long 0x00 0. " AUTOIDLE ,Internal interconnect clock gating strategy" "Free-running,Applied"
rgroup.long 0x14++0x3
line.long 0x00 "MMU_SYSSTATUS,Status Information About The Module"
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.long 0x18++0x7
line.long 0x00 "MMU_IRQSTATUS,Interrupt Status Register"
eventfld.long 0x00 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB (MultiHitFault)" "False,Pending"
textline " "
eventfld.long 0x00 3. " TABLEWALKFAULT ,Error response received during a table walk (TableWalkFault)" "False,Pending"
textline " "
eventfld.long 0x00 2. " EMUMISS ,Unrecoverable TLB miss during debug (EMUMiss)" "False,Pending"
textline " "
eventfld.long 0x00 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables (TranslationFault)" "False,Pending"
textline " "
eventfld.long 0x00 0. " TLBMISS ,Unrecoverable TLB miss" "False,Pending"
line.long 0x04 "MMU_IRQENABLE,Interrupt Enable Register"
bitfld.long 0x04 4. " MULTIHITFAULT ,Error due to multiple matches in the TLB" "Masked,Enabled"
textline " "
bitfld.long 0x04 3. " TABLEWALKFAULT ,Error response received during a table walk" "Masked,Enabled"
textline " "
bitfld.long 0x04 2. " EMUMISS ,Unrecoverable TLB miss during debug" "Masked,Enabled"
textline " "
bitfld.long 0x04 1. " TRANSLATIONFAULT ,Invalid descriptor in translation tables" "Masked,Enabled"
textline " "
bitfld.long 0x04 0. " TLBMISS ,Unrecoverable TLB miss" "Masked,Enabled"
rgroup.long 0x40++0x3
line.long 0x00 "MMU_WALKING_ST,Status Information About The Table Walking Logic"
bitfld.long 0x00 0. " TWLRUNNING ,Table walking logic is running" "Completed,Running"
group.long 0x44++0x3
line.long 0x00 "MMU_CNTL,MMU Features"
bitfld.long 0x00 3. " EMUTLBUPDATE ,Enable TLB update on emulator table walk" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " TWLENABLE ,Table walking logic enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " MMUENABLE ,MMU enable" "Disabled,Enabled"
rgroup.long 0x48++0x3
line.long 0x00 "MMU_FAULT_AD,Virtual Address That Generated The Interrupt"
group.long 0x4C++0x7
line.long 0x00 "MMU_TTB,Resolution Table Base Address"
hexmask.long 0x00 7.--31. 0x80 " TTBADDRESS ,Translation table base address"
line.long 0x04 "MMU_LOCK,Lock the TLB entries to be read"
bitfld.long 0x04 10.--14. " BASEVALUE ,Locked entries base value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x04 4.--8. " CURRENTVICTIM ,Eentry updated by the TWL/by the software/TLB entry read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x54++0x13
line.long 0x00 "MMU_LD_TLB,Loads A TLB Entry"
bitfld.long 0x00 0. " LDTLBITEM ,Write (load) data in the TLB" "No effect,Load"
line.long 0x04 "MMU_CAM,CAM Entry"
hexmask.long.tbyte 0x04 12.--31. 0x10 " VATAG ,Virtual address tag"
textline " "
bitfld.long 0x04 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
textline " "
bitfld.long 0x04 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
textline " "
bitfld.long 0x04 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
line.long 0x08 "MMU_RAM,RAM Entry"
hexmask.long.tbyte 0x08 12.--31. 0x10 " PHYSICALADDRESS ,Physical address of the page"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,?..."
else
bitfld.long 0x08 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
endif
textline " "
bitfld.long 0x08 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
textline " "
bitfld.long 0x08 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
line.long 0x0C "MMU_GFLUSH,Flushes All The Non-protected TLB Entries"
bitfld.long 0x0C 0. " GLOBALFLUSH ,Flush all the non-protected TLB entries" "No effect,Flush"
line.long 0x10 "MMU_FLUSH_ENTRY,Flushes The Entry Pointed To By The CAM Virtual Address"
bitfld.long 0x10 0. " FLUSHENTRY ,Flush the TLB entry pointed by the virtual address" "No effect,Flush"
rgroup.long 0x68++0xB
line.long 0x00 "MMU_READ_CAM,Reads CAM Data From A CAM Entry"
hexmask.long 0x00 12.--31. 0x1000 " VATAG ,Virtual address tag"
textline " "
bitfld.long 0x00 3. " P ,Preserved bit (TLB entry flushed)" "Not protected,Protected"
textline " "
bitfld.long 0x00 2. " V ,Valid bit (TLB entry)" "Invalid,Valid"
textline " "
bitfld.long 0x00 0.--1. " PAGESIZE ,Page size" "1MB,64KB,4KB,16MB"
line.long 0x04 "MMU_READ_RAM,Reads RAM Data From A RAM Entry"
hexmask.long 0x04 12.--31. 0x1000 " PHYSICALADDRESS ,Physical address of the page"
textline " "
bitfld.long 0x04 9. " ENDIANNESS ,Endianness of the page" "Little endian,Big endian"
textline " "
bitfld.long 0x04 7.--8. " ELEMENTSIZE ,Element size of the page" "8 bits,16 bits,32 bits,No translation"
textline " "
bitfld.long 0x04 6. " MIXED ,Mixed page attribute (use CPU element size)" "TLB,CPU"
line.long 0x08 "MMU_EMU_FAULT_AD,Last Virtual Address Of A Fault Caused By The Debugger"
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP")||cpuis("DRA62*"))
rgroup.long 0x80++0x3
line.long 0x00 "MMU_FAULT_PC,MMU Fault Caused By CPU Program Counter Value"
endif
width 0xb
tree.end
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
tree "SGX530 (2D/3D Graphics Accelerator)"
base ad:0x5600fe00
width 21.
rgroup.long 0x00++0x07
line.long 0x00 "OCP_REVISION,OCP Revision Register"
line.long 0x04 "OCP_HWINFO,Hardware implementation information"
bitfld.long 0x04 2. " MEM_BUS_WIDTH ,Memory bus width (bits)" "64,128"
bitfld.long 0x04 0.--1. " SYS_BUS_WIDTH ,System bus width (bits)" "32,64,128,?..."
group.long 0x10++0x03
line.long 0x00 "OCP_SYSCONFIG,System Configuration register"
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Clock standby mode" "Force Standby,No Standby,Smart Standby,Smart Standby"
bitfld.long 0x00 2.--3. " IDLE_MODE ,Clock Idle mode" "Force Idle,No idle,Smart Idle,Smart Idle"
group.long 0x24++0x0b
line.long 0x00 "OCP_IRQSTATUS_RAW_0,Raw IRQ 0 Status"
bitfld.long 0x00 0. " INIT_MINTERRUPT_RAW ,Interrupt 0 - master port raw event" "No interrupt,Interrupt"
line.long 0x04 "OCP_IRQSTATUS_RAW_1,Raw IRQ1 Status"
bitfld.long 0x04 0. " TARGET_SINTERRUPT_RAW ,Interrupt 1 - slave port raw event" "No interrupt,Interrupt"
line.long 0x08 "OCP_IRQSTATUS_RAW_2,Raw IRQ2 Status"
bitfld.long 0x08 0. " THALIA_IRQ_RAW ,Interrupt 2 - Thalia port raw event" "No interrupt,Interrupt"
sif (cpuis("DRA62*"))
group.long 0x30++0x0B
line.long 0x00 "OCP_IRQSTATUS_0,Interrupt 0 Status event"
eventfld.long 0x00 0. " INIT_MINTERRUPT_STATUS ,Interrupt 0 - master port status event" "No interrupt,Interrupt"
line.long 0x04 "OCP_IRQSTATUS_1,Interrupt 1 Status event"
eventfld.long 0x04 0. " TARGET_SINTERRUPT_STATUS ,Interrupt 1 - slave port status event" "No interrupt,Interrupt"
line.long 0x08 "OCP_IRQSTATUS_2,Interrupt 2 Status event"
eventfld.long 0x08 0. " THALIA_IRQ_STATUS ,Interrupt 2 - Thalia (core) status event" "No interrupt,Interrupt"
group.long 0x3C++0x0B
line.long 0x00 "OCP_IRQENABLE_0,Interrupt 0 Enable"
setclrfld.long 0x00 0. 0x00 0. 0xC 0. " INIT_MINTERRUPT_ENABLE_set/clr ,Interrupt 0 - master port enable" "Disabled,Enabled"
line.long 0x04 "OCP_IRQENABLE_1,Interrupt 1 Enable"
setclrfld.long 0x04 0. 0x04 0. 0x10 0. " TARGET_SINTERRUPT_ENABLE_set/clr ,Interrupt 1 - slave port enable" "Disabled,Enabled"
line.long 0x08 "OCP_IRQENABLE_2,Interrupt 2 Enable"
setclrfld.long 0x08 0. 0x08 0. 0x14 0. " THALIA_IRQ_ENABLE_set/clr ,Interrupt 2 - Thalia (core) enable" "Disabled,Enabled"
else
group.long 0x30++0x03
line.long 0x00 "OCP_IRQSTATUS_0,Interrupt 0 Status event"
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " INIT_MINTERRUPT_STATUS_set/clr ,Interrupt 0 - master port status event" "No interrupt,Interrupt"
group.long 0x34++0x03
line.long 0x00 "OCP_IRQSTATUS_1,Interrupt 1 Status event"
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " TARGET_SINTERRUPT_STATUS_set/clr ,Interrupt 1 - slave port status event" "No interrupt,Interrupt"
group.long 0x38++0x03
line.long 0x00 "OCP_IRQSTATUS_2,Interrupt 2 Status event"
setclrfld.long 0x00 0. 0x0c 0. 0x18 0. " THALIA_IRQ_STATUS_set/clr ,Interrupt 2 - Thalia (core) status event" "No interrupt,Interrupt"
endif
group.long 0x100++0x0f
line.long 0x00 "OCP_PAGE_CONFIG,Configure memory pages"
sif (cpuis("DRA62*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface" "4 KB,2 KB,1 KB,520 B"
else
bitfld.long 0x00 3.--4. " OCP_PAGE_SIZE ,Defines the page size on OCP memory interface" "4 KB,2 KB,1 KB,512 B"
endif
textline " "
bitfld.long 0x00 2. " MEM_PAGE_CHECK_EN ,Enable page boundary checking" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface" "4 KB,2 KB,1 KB,520 B"
else
bitfld.long 0x00 0.--1. " MEM_PAGE_SIZE ,Defines the page size on internal memory interface" "4 KB,2 KB,1 KB,512 B"
endif
line.long 0x04 "OCP_INTERRUPT_EVENT,Interrupt events"
bitfld.long 0x04 10. " TARGET_INVALID_OCP_CMD ,Invalid command from OCP" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 9. " TARGET_CMD_FIFO_FULL ,Command FIFO full" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 8. " TARGET_RESP_FIFO_FULL ,Response FIFO full" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " INIT_MEM_REQ_FIFO_OVERRUN ,Memory request FIFO overrun" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 4. " INIT_READ_TAG_FIFO_OVERRUN ,Read tag FIFO overrun" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " INIT_PAGE_CROSS_ERROR ,Memory page had been crossed during a burst" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 2. " INIT_RESP_ERROR ,Receiving error response" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " INIT_RESP_UNUSED_TAG ,Receiving response on an unused tag" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 0. " INIT_RESP_UNEXPECTED ,Receiving response when not expected" "No interrupt,Interrupt"
line.long 0x08 "OCP_DEBUG_CONFIG,Configuration of debug modes"
bitfld.long 0x08 31. " THALIA_INT_BYPASS ,Bypass OCP IPG interrupt logic" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x08 5. " SELECT_INIT_IDLE ,Select Init Idle" "Whole SGX,OCP initiator"
textline " "
bitfld.long 0x08 4. " FORCE_PASS_DATA ,Forces the initiator to pass data independent of disconnect protocol" "Normal,Forced"
textline " "
bitfld.long 0x08 2.--3. " FORCE_INIT_IDLE ,Forces the OCP master port to Idle" "Normal,Port always Idle,Target port never Idle,Normal"
textline " "
bitfld.long 0x08 0.--1. " FORCE_TARGET_IDLE ,Forces the OCP target port to Idle" "Normal,Port always Idle,Target port never Idle,Normal"
line.long 0x0c "OCP_DEBUG_STATUS,Status of debug"
bitfld.long 0x0C 31. " CMD_DEBUG_STATE ,Target command state machine" "Idle,Accepted"
textline " "
bitfld.long 0x0C 30. " CMD_RESP_DEBUG_STATE ,Target response state machine" "Send,Wait"
textline " "
rbitfld.long 0x0C 29. " TARGET_IDLE ,Target idle" "Low,High"
textline " "
rbitfld.long 0x0C 28. " RESP_FIFO_FULL ,Target response FIFO full" "Not full,Full"
textline " "
rbitfld.long 0x0C 27. " CMD_FIFO_FULL ,Target command FIFO full" "Not full,Full"
textline " "
rbitfld.long 0x0C 26. " RESP_ERROR ,Respond to OCP with error" "No error,Error"
textline " "
bitfld.long 0x0C 21.--25. " WHICH_TARGET_REGISTER ,Indicates which OCP target registers to read" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
rbitfld.long 0x0C 18.--20. " TARGET_CMD_OUT ,Command received from OCP" "WRSYS,RDSYS,WR_ERROR,RD_ERROR,CHK_WRADDR_PAGE,CHK_RDADDR_PAGE,TARGET_REG_WRITE,TARGET_REG_READ"
textline " "
rbitfld.long 0x0C 17. " INIT_MSTANDBY ,Status of init_MStandby signal" "Low,High"
textline " "
rbitfld.long 0x0C 16. " INIT_MWAIT ,Status of init_MWait signal" "Low,High"
textline " "
rbitfld.long 0x0C 14.--15. " INIT_MDISCREQ ,Disconnect status of the OCP interface" "FUNCT,SLEEP TRANS,Reserved,IDLE"
textline " "
bitfld.long 0x0C 13. " INIT_MDISCACK ,Memory request FIFO full" "Not full,Full"
textline " "
rbitfld.long 0x0C 12. " INIT_SCONNECT2 ,Defines whether to wait in M_WAIT state for MConnect FSM" "Skip,Wait"
textline " "
rbitfld.long 0x0C 11. " INIT_SCONNECT1 ,Defines the busy-ness state of the slave" "Drained,Loaded"
textline " "
rbitfld.long 0x0C 10. " INIT_SCONNECT0 ,Disconnect from slave" "Disconnected,Connected"
textline " "
rbitfld.long 0x0C 8.--9. " INIT_MCONNECT ,Initiator MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON"
textline " "
rbitfld.long 0x0C 6.--7. " TARGET_SIDLEACK ,Acknowledge the SIdleAck state machine" "FUNCT,SLEEP TRANS,Reserved,IDLE"
textline " "
rbitfld.long 0x0C 4.--5. " TARGET_SDISCACK ,Acknowledge the SDiscAck state machine" "FUNCT,TRANS,Reserved,IDLE"
textline " "
rbitfld.long 0x0C 3. " TARGET_SIDLEREQ ,Request the target to go idle" "Not idle/go active,Go idle"
textline " "
rbitfld.long 0x0C 2. " TARGET_SCONNECT ,Target SConnect state" "Disconnected,Connected"
textline " "
rbitfld.long 0x0C 0.--1. " TARGET_MCONNECT ,Target MConnect state" "M_OFF,M_WAIT,M_DISC,M_CON"
width 0xb
tree.end
endif
tree "MAILBOX (Mailbox Registers)"
base ad:0x480c8000
width 23.
rgroup.long 0x00++0x3
line.long 0x00 "MAILBOX_REVISION,Mailbox IP Revision Code"
group.long 0x10++0x3
line.long 0x00 "MAILBOX_SYSCONFIG,Mailbox System Configuration Register"
sif (cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
bitfld.long 0x00 2.--3. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
else
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
endif
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "Normal,Reset"
sif (cpu()!="AM3874")&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")
rgroup.long 0x14++0x3
line.long 0x00 "MAILBOX_SYSSTATUS,Mailbox Status Information About The Module"
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "On-going,Completed"
endif
group.long 0x40++0x2f
line.long 0x0 "MAILBOX_MESSAGE_0,Mailbox Message 0 Register"
line.long 0x4 "MAILBOX_MESSAGE_1,Mailbox Message 1 Register"
line.long 0x8 "MAILBOX_MESSAGE_2,Mailbox Message 2 Register"
line.long 0xC "MAILBOX_MESSAGE_3,Mailbox Message 3 Register"
line.long 0x10 "MAILBOX_MESSAGE_4,Mailbox Message 4 Register"
line.long 0x14 "MAILBOX_MESSAGE_5,Mailbox Message 5 Register"
line.long 0x18 "MAILBOX_MESSAGE_6,Mailbox Message 6 Register"
line.long 0x1C "MAILBOX_MESSAGE_7,Mailbox Message 7 Register"
line.long 0x20 "MAILBOX_MESSAGE_8,Mailbox Message 8 Register"
line.long 0x24 "MAILBOX_MESSAGE_9,Mailbox Message 9 Register"
line.long 0x28 "MAILBOX_MESSAGE_10,Mailbox Message 10 Register"
line.long 0x2C "MAILBOX_MESSAGE_11,Mailbox Message 11 Register"
rgroup.long 0x80++0x2f
line.long 0x0 "MAILBOX_FIFOSTATUS_0 ,Mailbox FIFO Status 0 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x0 1.--31. 1. " MESSAGEVALUEMB0 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x0 0. " FIFOFULLMB0 ,Full flag for Mailbox" "Not full,Full"
line.long 0x4 "MAILBOX_FIFOSTATUS_1 ,Mailbox FIFO Status 1 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x4 1.--31. 1. " MESSAGEVALUEMB1 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x4 0. " FIFOFULLMB1 ,Full flag for Mailbox" "Not full,Full"
line.long 0x8 "MAILBOX_FIFOSTATUS_2 ,Mailbox FIFO Status 2 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x8 1.--31. 1. " MESSAGEVALUEMB2 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x8 0. " FIFOFULLMB2 ,Full flag for Mailbox" "Not full,Full"
line.long 0xC "MAILBOX_FIFOSTATUS_3 ,Mailbox FIFO Status 3 Register"
sif (cpuis("DRA62*"))
hexmask.long 0xC 1.--31. 1. " MESSAGEVALUEMB3 ,Message in Mailbox"
textline " "
endif
bitfld.long 0xC 0. " FIFOFULLMB3 ,Full flag for Mailbox" "Not full,Full"
line.long 0x10 "MAILBOX_FIFOSTATUS_4 ,Mailbox FIFO Status 4 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x10 1.--31. 1. " MESSAGEVALUEMB4 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x10 0. " FIFOFULLMB4 ,Full flag for Mailbox" "Not full,Full"
line.long 0x14 "MAILBOX_FIFOSTATUS_5 ,Mailbox FIFO Status 5 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x14 1.--31. 1. " MESSAGEVALUEMB5 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x14 0. " FIFOFULLMB5 ,Full flag for Mailbox" "Not full,Full"
line.long 0x18 "MAILBOX_FIFOSTATUS_6 ,Mailbox FIFO Status 6 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x18 1.--31. 1. " MESSAGEVALUEMB6 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x18 0. " FIFOFULLMB6 ,Full flag for Mailbox" "Not full,Full"
line.long 0x1C "MAILBOX_FIFOSTATUS_7 ,Mailbox FIFO Status 7 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x1C 1.--31. 1. " MESSAGEVALUEMB7 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x1C 0. " FIFOFULLMB7 ,Full flag for Mailbox" "Not full,Full"
line.long 0x20 "MAILBOX_FIFOSTATUS_8 ,Mailbox FIFO Status 8 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x20 1.--31. 1. " MESSAGEVALUEMB8 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x20 0. " FIFOFULLMB8 ,Full flag for Mailbox" "Not full,Full"
line.long 0x24 "MAILBOX_FIFOSTATUS_9 ,Mailbox FIFO Status 9 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x24 1.--31. 1. " MESSAGEVALUEMB9 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x24 0. " FIFOFULLMB9 ,Full flag for Mailbox" "Not full,Full"
line.long 0x28 "MAILBOX_FIFOSTATUS_10,Mailbox FIFO Status 10 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x28 1.--31. 1. " MESSAGEVALUEMB10 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x28 0. " FIFOFULLMB10 ,Full flag for Mailbox" "Not full,Full"
line.long 0x2C "MAILBOX_FIFOSTATUS_11,Mailbox FIFO Status 11 Register"
sif (cpuis("DRA62*"))
hexmask.long 0x2C 1.--31. 1. " MESSAGEVALUEMB11 ,Message in Mailbox"
textline " "
endif
bitfld.long 0x2C 0. " FIFOFULLMB11 ,Full flag for Mailbox" "Not full,Full"
rgroup.long 0xC0++0x2f
line.long 0x0 "MAILBOX_MSGSTATUS_0 ,Mailbox Message Status 0 Register"
bitfld.long 0x0 0.--2. " NBOFMSGMBM0 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x4 "MAILBOX_MSGSTATUS_1 ,Mailbox Message Status 1 Register"
bitfld.long 0x4 0.--2. " NBOFMSGMBM1 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x8 "MAILBOX_MSGSTATUS_2 ,Mailbox Message Status 2 Register"
bitfld.long 0x8 0.--2. " NBOFMSGMBM2 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0xC "MAILBOX_MSGSTATUS_3 ,Mailbox Message Status 3 Register"
bitfld.long 0xC 0.--2. " NBOFMSGMBM3 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x10 "MAILBOX_MSGSTATUS_4 ,Mailbox Message Status 4 Register"
bitfld.long 0x10 0.--2. " NBOFMSGMBM4 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x14 "MAILBOX_MSGSTATUS_5 ,Mailbox Message Status 5 Register"
bitfld.long 0x14 0.--2. " NBOFMSGMBM5 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x18 "MAILBOX_MSGSTATUS_6 ,Mailbox Message Status 6 Register"
bitfld.long 0x18 0.--2. " NBOFMSGMBM6 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x1C "MAILBOX_MSGSTATUS_7 ,Mailbox Message Status 7 Register"
bitfld.long 0x1C 0.--2. " NBOFMSGMBM7 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x20 "MAILBOX_MSGSTATUS_8 ,Mailbox Message Status 8 Register"
bitfld.long 0x20 0.--2. " NBOFMSGMBM8 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x24 "MAILBOX_MSGSTATUS_9 ,Mailbox Message Status 9 Register"
bitfld.long 0x24 0.--2. " NBOFMSGMBM9 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x28 "MAILBOX_MSGSTATUS_10,Mailbox Message Status 10 Register"
bitfld.long 0x28 0.--2. " NBOFMSGMBM10 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
line.long 0x2C "MAILBOX_MSGSTATUS_11,Mailbox Message Status 11 Register"
bitfld.long 0x2C 0.--2. " NBOFMSGMBM11 ,Number of Unread Messages in Mailbox" "0,1,2,3,4,?..."
width 25.
tree "User 0 Mailbox Interrupts"
group.long (0x100+0x0)++0xf
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_0,Mailbox IRQ RAW Status Register"
bitfld.long 0x00 23. " NOTFULLSTATUSU0MB11 ,NotFull Raw Status bit for User 0 Mailbox 11" "Full,Not full"
bitfld.long 0x00 22. " NEWMSGSTATUSU0MB11 ,NewMessage Raw Status bit for User 0 Mailbox 11" "No action,New message"
textline " "
bitfld.long 0x00 21. " NOTFULLSTATUSU0MB10 ,NotFull Raw Status bit for User 0 Mailbox 10" "Full,Not full"
bitfld.long 0x00 20. " NEWMSGSTATUSU0MB10 ,NewMessage Raw Status bit for User 0 Mailbox 10" "No action,New message"
textline " "
bitfld.long 0x00 19. " NOTFULLSTATUSU0MB9 ,NotFull Raw Status bit for User 0 Mailbox 9" "Full,Not full"
bitfld.long 0x00 18. " NEWMSGSTATUSU0MB9 ,NewMessage Raw Status bit for User 0 Mailbox 9" "No action,New message"
textline " "
bitfld.long 0x00 17. " NOTFULLSTATUSU0MB8 ,NotFull Raw Status bit for User 0 Mailbox 8" "Full,Not full"
bitfld.long 0x00 16. " NEWMSGSTATUSU0MB8 ,NewMessage Raw Status bit for User 0 Mailbox 8" "No action,New message"
textline " "
bitfld.long 0x00 15. " NOTFULLSTATUSU0MB7 ,NotFull Raw Status bit for User 0 Mailbox 7" "Full,Not full"
bitfld.long 0x00 14. " NEWMSGSTATUSU0MB7 ,NewMessage Raw Status bit for User 0 Mailbox 7" "No action,New message"
textline " "
bitfld.long 0x00 13. " NOTFULLSTATUSU0MB6 ,NotFull Raw Status bit for User 0 Mailbox 6" "Full,Not full"
bitfld.long 0x00 12. " NEWMSGSTATUSU0MB6 ,NewMessage Raw Status bit for User 0 Mailbox 6" "No action,New message"
textline " "
bitfld.long 0x00 11. " NOTFULLSTATUSU0MB5 ,NotFull Raw Status bit for User 0 Mailbox 5" "Full,Not full"
bitfld.long 0x00 10. " NEWMSGSTATUSU0MB5 ,NewMessage Raw Status bit for User 0 Mailbox 5" "No action,New message"
textline " "
bitfld.long 0x00 9. " NOTFULLSTATUSU0MB4 ,NotFull Raw Status bit for User 0 Mailbox 4" "Full,Not full"
bitfld.long 0x00 8. " NEWMSGSTATUSU0MB4 ,NewMessage Raw Status bit for User 0 Mailbox 4" "No action,New message"
textline " "
bitfld.long 0x00 7. " NOTFULLSTATUSU0MB3 ,NotFull Raw Status bit for User 0 Mailbox 3" "Full,Not full"
bitfld.long 0x00 6. " NEWMSGSTATUSU0MB3 ,NewMessage Raw Status bit for User 0 Mailbox 3" "No action,New message"
textline " "
bitfld.long 0x00 5. " NOTFULLSTATUSU0MB2 ,NotFull Raw Status bit for User 0 Mailbox 2" "Full,Not full"
bitfld.long 0x00 4. " NEWMSGSTATUSU0MB2 ,NewMessage Raw Status bit for User 0 Mailbox 2" "No action,New message"
textline " "
bitfld.long 0x00 3. " NOTFULLSTATUSU0MB1 ,NotFull Raw Status bit for User 0 Mailbox 1" "Full,Not full"
bitfld.long 0x00 2. " NEWMSGSTATUSU0MB1 ,NewMessage Raw Status bit for User 0 Mailbox 1" "No action,New message"
textline " "
bitfld.long 0x00 1. " NOTFULLSTATUSU0MB0 ,NotFull Raw Status bit for User 0 Mailbox 0" "Full,Not full"
bitfld.long 0x00 0. " NEWMSGSTATUSU0MB0 ,NewMessage Raw Status bit for User 0 Mailbox 0" "No action,New message"
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_0,Mailbox IRQ Clear Status Register"
eventfld.long 0x04 23. " NOTFULLSTATUSU0MB11 ,NotFull Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
eventfld.long 0x04 22. " NEWMSGSTATUSU0MB11 ,NewMessage Clear Status bit for User 0 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x04 21. " NOTFULLSTATUSU0MB10 ,NotFull Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
eventfld.long 0x04 20. " NEWMSGSTATUSU0MB10 ,NewMessage Clear Status bit for User 0 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x04 19. " NOTFULLSTATUSU0MB9 ,NotFull Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
eventfld.long 0x04 18. " NEWMSGSTATUSU0MB9 ,NewMessage Clear Status bit for User 0 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x04 17. " NOTFULLSTATUSU0MB8 ,NotFull Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
eventfld.long 0x04 16. " NEWMSGSTATUSU0MB8 ,NewMessage Clear Status bit for User 0 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x04 15. " NOTFULLSTATUSU0MB7 ,NotFull Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
eventfld.long 0x04 14. " NEWMSGSTATUSU0MB7 ,NewMessage Clear Status bit for User 0 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x04 13. " NOTFULLSTATUSU0MB6 ,NotFull Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
eventfld.long 0x04 12. " NEWMSGSTATUSU0MB6 ,NewMessage Clear Status bit for User 0 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x04 11. " NOTFULLSTATUSU0MB5 ,NotFull Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
eventfld.long 0x04 10. " NEWMSGSTATUSU0MB5 ,NewMessage Clear Status bit for User 0 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x04 9. " NOTFULLSTATUSU0MB4 ,NotFull Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
eventfld.long 0x04 8. " NEWMSGSTATUSU0MB4 ,NewMessage Clear Status bit for User 0 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x04 7. " NOTFULLSTATUSU0MB3 ,NotFull Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
eventfld.long 0x04 6. " NEWMSGSTATUSU0MB3 ,NewMessage Clear Status bit for User 0 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x04 5. " NOTFULLSTATUSU0MB2 ,NotFull Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
eventfld.long 0x04 4. " NEWMSGSTATUSU0MB2 ,NewMessage Clear Status bit for User 0 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x04 3. " NOTFULLSTATUSU0MB1 ,NotFull Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
eventfld.long 0x04 2. " NEWMSGSTATUSU0MB1 ,NewMessage Clear Status bit for User 0 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x04 1. " NOTFULLSTATUSU0MB0 ,NotFull Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
eventfld.long 0x04 0. " NEWMSGSTATUSU0MB0 ,NewMessage Clear Status bit for User 0 Mailbox 0" "Not pending,Pending"
line.long 0x08 "MAILBOX_IRQENABLE_SET_0,Mailbox IRQ Enable Set Register"
bitfld.long 0x08 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
bitfld.long 0x08 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Set bit for User 0 Mailbox 11" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
bitfld.long 0x08 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Set bit for User 0 Mailbox 10" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
bitfld.long 0x08 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Set bit for User 0 Mailbox 9" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
bitfld.long 0x08 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Set bit for User 0 Mailbox 8" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
bitfld.long 0x08 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Set bit for User 0 Mailbox 7" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
bitfld.long 0x08 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Set bit for User 0 Mailbox 6" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
bitfld.long 0x08 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Set bit for User 0 Mailbox 5" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
bitfld.long 0x08 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Set bit for User 0 Mailbox 4" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
bitfld.long 0x08 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Set bit for User 0 Mailbox 3" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
bitfld.long 0x08 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Set bit for User 0 Mailbox 2" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
bitfld.long 0x08 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Set bit for User 0 Mailbox 1" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
bitfld.long 0x08 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Set bit for User 0 Mailbox 0" "Disabled,Enabled"
line.long 0x0c "MAILBOX_IRQENABLE_CLR_0,Mailbox IRQ Enable Clear Register"
eventfld.long 0x0c 23. " NOTFULLENABLEU0MB11 ,NotFull Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
eventfld.long 0x0c 22. " NEWMSGENABLEU0MB11 ,NewMessage Enable Clear bit for User 0 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x0c 21. " NOTFULLENABLEU0MB10 ,NotFull Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
eventfld.long 0x0c 20. " NEWMSGENABLEU0MB10 ,NewMessage Enable Clear bit for User 0 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x0c 19. " NOTFULLENABLEU0MB9 ,NotFull Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
eventfld.long 0x0c 18. " NEWMSGENABLEU0MB9 ,NewMessage Enable Clear bit for User 0 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x0c 17. " NOTFULLENABLEU0MB8 ,NotFull Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
eventfld.long 0x0c 16. " NEWMSGENABLEU0MB8 ,NewMessage Enable Clear bit for User 0 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x0c 15. " NOTFULLENABLEU0MB7 ,NotFull Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
eventfld.long 0x0c 14. " NEWMSGENABLEU0MB7 ,NewMessage Enable Clear bit for User 0 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x0c 13. " NOTFULLENABLEU0MB6 ,NotFull Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
eventfld.long 0x0c 12. " NEWMSGENABLEU0MB6 ,NewMessage Enable Clear bit for User 0 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x0c 11. " NOTFULLENABLEU0MB5 ,NotFull Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
eventfld.long 0x0c 10. " NEWMSGENABLEU0MB5 ,NewMessage Enable Clear bit for User 0 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x0c 9. " NOTFULLENABLEU0MB4 ,NotFull Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
eventfld.long 0x0c 8. " NEWMSGENABLEU0MB4 ,NewMessage Enable Clear bit for User 0 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x0c 7. " NOTFULLENABLEU0MB3 ,NotFull Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
eventfld.long 0x0c 6. " NEWMSGENABLEU0MB3 ,NewMessage Enable Clear bit for User 0 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x0c 5. " NOTFULLENABLEU0MB2 ,NotFull Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
eventfld.long 0x0c 4. " NEWMSGENABLEU0MB2 ,NewMessage Enable Clear bit for User 0 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x0c 3. " NOTFULLENABLEU0MB1 ,NotFull Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
eventfld.long 0x0c 2. " NEWMSGENABLEU0MB1 ,NewMessage Enable Clear bit for User 0 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x0c 1. " NOTFULLENABLEU0MB0 ,NotFull Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
eventfld.long 0x0c 0. " NEWMSGENABLEU0MB0 ,NewMessage Enable Clear bit for User 0 Mailbox 0" "Not pending,Pending"
tree.end
tree "User 1 Mailbox Interrupts"
group.long (0x100+0x10)++0xf
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_1,Mailbox IRQ RAW Status Register"
bitfld.long 0x00 23. " NOTFULLSTATUSU1MB11 ,NotFull Raw Status bit for User 1 Mailbox 11" "Full,Not full"
bitfld.long 0x00 22. " NEWMSGSTATUSU1MB11 ,NewMessage Raw Status bit for User 1 Mailbox 11" "No action,New message"
textline " "
bitfld.long 0x00 21. " NOTFULLSTATUSU1MB10 ,NotFull Raw Status bit for User 1 Mailbox 10" "Full,Not full"
bitfld.long 0x00 20. " NEWMSGSTATUSU1MB10 ,NewMessage Raw Status bit for User 1 Mailbox 10" "No action,New message"
textline " "
bitfld.long 0x00 19. " NOTFULLSTATUSU1MB9 ,NotFull Raw Status bit for User 1 Mailbox 9" "Full,Not full"
bitfld.long 0x00 18. " NEWMSGSTATUSU1MB9 ,NewMessage Raw Status bit for User 1 Mailbox 9" "No action,New message"
textline " "
bitfld.long 0x00 17. " NOTFULLSTATUSU1MB8 ,NotFull Raw Status bit for User 1 Mailbox 8" "Full,Not full"
bitfld.long 0x00 16. " NEWMSGSTATUSU1MB8 ,NewMessage Raw Status bit for User 1 Mailbox 8" "No action,New message"
textline " "
bitfld.long 0x00 15. " NOTFULLSTATUSU1MB7 ,NotFull Raw Status bit for User 1 Mailbox 7" "Full,Not full"
bitfld.long 0x00 14. " NEWMSGSTATUSU1MB7 ,NewMessage Raw Status bit for User 1 Mailbox 7" "No action,New message"
textline " "
bitfld.long 0x00 13. " NOTFULLSTATUSU1MB6 ,NotFull Raw Status bit for User 1 Mailbox 6" "Full,Not full"
bitfld.long 0x00 12. " NEWMSGSTATUSU1MB6 ,NewMessage Raw Status bit for User 1 Mailbox 6" "No action,New message"
textline " "
bitfld.long 0x00 11. " NOTFULLSTATUSU1MB5 ,NotFull Raw Status bit for User 1 Mailbox 5" "Full,Not full"
bitfld.long 0x00 10. " NEWMSGSTATUSU1MB5 ,NewMessage Raw Status bit for User 1 Mailbox 5" "No action,New message"
textline " "
bitfld.long 0x00 9. " NOTFULLSTATUSU1MB4 ,NotFull Raw Status bit for User 1 Mailbox 4" "Full,Not full"
bitfld.long 0x00 8. " NEWMSGSTATUSU1MB4 ,NewMessage Raw Status bit for User 1 Mailbox 4" "No action,New message"
textline " "
bitfld.long 0x00 7. " NOTFULLSTATUSU1MB3 ,NotFull Raw Status bit for User 1 Mailbox 3" "Full,Not full"
bitfld.long 0x00 6. " NEWMSGSTATUSU1MB3 ,NewMessage Raw Status bit for User 1 Mailbox 3" "No action,New message"
textline " "
bitfld.long 0x00 5. " NOTFULLSTATUSU1MB2 ,NotFull Raw Status bit for User 1 Mailbox 2" "Full,Not full"
bitfld.long 0x00 4. " NEWMSGSTATUSU1MB2 ,NewMessage Raw Status bit for User 1 Mailbox 2" "No action,New message"
textline " "
bitfld.long 0x00 3. " NOTFULLSTATUSU1MB1 ,NotFull Raw Status bit for User 1 Mailbox 1" "Full,Not full"
bitfld.long 0x00 2. " NEWMSGSTATUSU1MB1 ,NewMessage Raw Status bit for User 1 Mailbox 1" "No action,New message"
textline " "
bitfld.long 0x00 1. " NOTFULLSTATUSU1MB0 ,NotFull Raw Status bit for User 1 Mailbox 0" "Full,Not full"
bitfld.long 0x00 0. " NEWMSGSTATUSU1MB0 ,NewMessage Raw Status bit for User 1 Mailbox 0" "No action,New message"
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_1,Mailbox IRQ Clear Status Register"
eventfld.long 0x04 23. " NOTFULLSTATUSU1MB11 ,NotFull Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
eventfld.long 0x04 22. " NEWMSGSTATUSU1MB11 ,NewMessage Clear Status bit for User 1 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x04 21. " NOTFULLSTATUSU1MB10 ,NotFull Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
eventfld.long 0x04 20. " NEWMSGSTATUSU1MB10 ,NewMessage Clear Status bit for User 1 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x04 19. " NOTFULLSTATUSU1MB9 ,NotFull Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
eventfld.long 0x04 18. " NEWMSGSTATUSU1MB9 ,NewMessage Clear Status bit for User 1 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x04 17. " NOTFULLSTATUSU1MB8 ,NotFull Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
eventfld.long 0x04 16. " NEWMSGSTATUSU1MB8 ,NewMessage Clear Status bit for User 1 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x04 15. " NOTFULLSTATUSU1MB7 ,NotFull Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
eventfld.long 0x04 14. " NEWMSGSTATUSU1MB7 ,NewMessage Clear Status bit for User 1 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x04 13. " NOTFULLSTATUSU1MB6 ,NotFull Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
eventfld.long 0x04 12. " NEWMSGSTATUSU1MB6 ,NewMessage Clear Status bit for User 1 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x04 11. " NOTFULLSTATUSU1MB5 ,NotFull Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
eventfld.long 0x04 10. " NEWMSGSTATUSU1MB5 ,NewMessage Clear Status bit for User 1 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x04 9. " NOTFULLSTATUSU1MB4 ,NotFull Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
eventfld.long 0x04 8. " NEWMSGSTATUSU1MB4 ,NewMessage Clear Status bit for User 1 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x04 7. " NOTFULLSTATUSU1MB3 ,NotFull Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
eventfld.long 0x04 6. " NEWMSGSTATUSU1MB3 ,NewMessage Clear Status bit for User 1 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x04 5. " NOTFULLSTATUSU1MB2 ,NotFull Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
eventfld.long 0x04 4. " NEWMSGSTATUSU1MB2 ,NewMessage Clear Status bit for User 1 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x04 3. " NOTFULLSTATUSU1MB1 ,NotFull Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
eventfld.long 0x04 2. " NEWMSGSTATUSU1MB1 ,NewMessage Clear Status bit for User 1 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x04 1. " NOTFULLSTATUSU1MB0 ,NotFull Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
eventfld.long 0x04 0. " NEWMSGSTATUSU1MB0 ,NewMessage Clear Status bit for User 1 Mailbox 0" "Not pending,Pending"
line.long 0x08 "MAILBOX_IRQENABLE_SET_1,Mailbox IRQ Enable Set Register"
bitfld.long 0x08 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
bitfld.long 0x08 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Set bit for User 1 Mailbox 11" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
bitfld.long 0x08 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Set bit for User 1 Mailbox 10" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
bitfld.long 0x08 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Set bit for User 1 Mailbox 9" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
bitfld.long 0x08 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Set bit for User 1 Mailbox 8" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
bitfld.long 0x08 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Set bit for User 1 Mailbox 7" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
bitfld.long 0x08 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Set bit for User 1 Mailbox 6" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
bitfld.long 0x08 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Set bit for User 1 Mailbox 5" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
bitfld.long 0x08 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Set bit for User 1 Mailbox 4" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
bitfld.long 0x08 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Set bit for User 1 Mailbox 3" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
bitfld.long 0x08 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Set bit for User 1 Mailbox 2" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
bitfld.long 0x08 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Set bit for User 1 Mailbox 1" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
bitfld.long 0x08 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Set bit for User 1 Mailbox 0" "Disabled,Enabled"
line.long 0x0c "MAILBOX_IRQENABLE_CLR_1,Mailbox IRQ Enable Clear Register"
eventfld.long 0x0c 23. " NOTFULLENABLEU1MB11 ,NotFull Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
eventfld.long 0x0c 22. " NEWMSGENABLEU1MB11 ,NewMessage Enable Clear bit for User 1 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x0c 21. " NOTFULLENABLEU1MB10 ,NotFull Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
eventfld.long 0x0c 20. " NEWMSGENABLEU1MB10 ,NewMessage Enable Clear bit for User 1 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x0c 19. " NOTFULLENABLEU1MB9 ,NotFull Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
eventfld.long 0x0c 18. " NEWMSGENABLEU1MB9 ,NewMessage Enable Clear bit for User 1 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x0c 17. " NOTFULLENABLEU1MB8 ,NotFull Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
eventfld.long 0x0c 16. " NEWMSGENABLEU1MB8 ,NewMessage Enable Clear bit for User 1 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x0c 15. " NOTFULLENABLEU1MB7 ,NotFull Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
eventfld.long 0x0c 14. " NEWMSGENABLEU1MB7 ,NewMessage Enable Clear bit for User 1 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x0c 13. " NOTFULLENABLEU1MB6 ,NotFull Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
eventfld.long 0x0c 12. " NEWMSGENABLEU1MB6 ,NewMessage Enable Clear bit for User 1 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x0c 11. " NOTFULLENABLEU1MB5 ,NotFull Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
eventfld.long 0x0c 10. " NEWMSGENABLEU1MB5 ,NewMessage Enable Clear bit for User 1 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x0c 9. " NOTFULLENABLEU1MB4 ,NotFull Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
eventfld.long 0x0c 8. " NEWMSGENABLEU1MB4 ,NewMessage Enable Clear bit for User 1 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x0c 7. " NOTFULLENABLEU1MB3 ,NotFull Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
eventfld.long 0x0c 6. " NEWMSGENABLEU1MB3 ,NewMessage Enable Clear bit for User 1 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x0c 5. " NOTFULLENABLEU1MB2 ,NotFull Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
eventfld.long 0x0c 4. " NEWMSGENABLEU1MB2 ,NewMessage Enable Clear bit for User 1 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x0c 3. " NOTFULLENABLEU1MB1 ,NotFull Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
eventfld.long 0x0c 2. " NEWMSGENABLEU1MB1 ,NewMessage Enable Clear bit for User 1 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x0c 1. " NOTFULLENABLEU1MB0 ,NotFull Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
eventfld.long 0x0c 0. " NEWMSGENABLEU1MB0 ,NewMessage Enable Clear bit for User 1 Mailbox 0" "Not pending,Pending"
tree.end
tree "User 2 Mailbox Interrupts"
group.long (0x100+0x20)++0xf
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_2,Mailbox IRQ RAW Status Register"
bitfld.long 0x00 23. " NOTFULLSTATUSU2MB11 ,NotFull Raw Status bit for User 2 Mailbox 11" "Full,Not full"
bitfld.long 0x00 22. " NEWMSGSTATUSU2MB11 ,NewMessage Raw Status bit for User 2 Mailbox 11" "No action,New message"
textline " "
bitfld.long 0x00 21. " NOTFULLSTATUSU2MB10 ,NotFull Raw Status bit for User 2 Mailbox 10" "Full,Not full"
bitfld.long 0x00 20. " NEWMSGSTATUSU2MB10 ,NewMessage Raw Status bit for User 2 Mailbox 10" "No action,New message"
textline " "
bitfld.long 0x00 19. " NOTFULLSTATUSU2MB9 ,NotFull Raw Status bit for User 2 Mailbox 9" "Full,Not full"
bitfld.long 0x00 18. " NEWMSGSTATUSU2MB9 ,NewMessage Raw Status bit for User 2 Mailbox 9" "No action,New message"
textline " "
bitfld.long 0x00 17. " NOTFULLSTATUSU2MB8 ,NotFull Raw Status bit for User 2 Mailbox 8" "Full,Not full"
bitfld.long 0x00 16. " NEWMSGSTATUSU2MB8 ,NewMessage Raw Status bit for User 2 Mailbox 8" "No action,New message"
textline " "
bitfld.long 0x00 15. " NOTFULLSTATUSU2MB7 ,NotFull Raw Status bit for User 2 Mailbox 7" "Full,Not full"
bitfld.long 0x00 14. " NEWMSGSTATUSU2MB7 ,NewMessage Raw Status bit for User 2 Mailbox 7" "No action,New message"
textline " "
bitfld.long 0x00 13. " NOTFULLSTATUSU2MB6 ,NotFull Raw Status bit for User 2 Mailbox 6" "Full,Not full"
bitfld.long 0x00 12. " NEWMSGSTATUSU2MB6 ,NewMessage Raw Status bit for User 2 Mailbox 6" "No action,New message"
textline " "
bitfld.long 0x00 11. " NOTFULLSTATUSU2MB5 ,NotFull Raw Status bit for User 2 Mailbox 5" "Full,Not full"
bitfld.long 0x00 10. " NEWMSGSTATUSU2MB5 ,NewMessage Raw Status bit for User 2 Mailbox 5" "No action,New message"
textline " "
bitfld.long 0x00 9. " NOTFULLSTATUSU2MB4 ,NotFull Raw Status bit for User 2 Mailbox 4" "Full,Not full"
bitfld.long 0x00 8. " NEWMSGSTATUSU2MB4 ,NewMessage Raw Status bit for User 2 Mailbox 4" "No action,New message"
textline " "
bitfld.long 0x00 7. " NOTFULLSTATUSU2MB3 ,NotFull Raw Status bit for User 2 Mailbox 3" "Full,Not full"
bitfld.long 0x00 6. " NEWMSGSTATUSU2MB3 ,NewMessage Raw Status bit for User 2 Mailbox 3" "No action,New message"
textline " "
bitfld.long 0x00 5. " NOTFULLSTATUSU2MB2 ,NotFull Raw Status bit for User 2 Mailbox 2" "Full,Not full"
bitfld.long 0x00 4. " NEWMSGSTATUSU2MB2 ,NewMessage Raw Status bit for User 2 Mailbox 2" "No action,New message"
textline " "
bitfld.long 0x00 3. " NOTFULLSTATUSU2MB1 ,NotFull Raw Status bit for User 2 Mailbox 1" "Full,Not full"
bitfld.long 0x00 2. " NEWMSGSTATUSU2MB1 ,NewMessage Raw Status bit for User 2 Mailbox 1" "No action,New message"
textline " "
bitfld.long 0x00 1. " NOTFULLSTATUSU2MB0 ,NotFull Raw Status bit for User 2 Mailbox 0" "Full,Not full"
bitfld.long 0x00 0. " NEWMSGSTATUSU2MB0 ,NewMessage Raw Status bit for User 2 Mailbox 0" "No action,New message"
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_2,Mailbox IRQ Clear Status Register"
eventfld.long 0x04 23. " NOTFULLSTATUSU2MB11 ,NotFull Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
eventfld.long 0x04 22. " NEWMSGSTATUSU2MB11 ,NewMessage Clear Status bit for User 2 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x04 21. " NOTFULLSTATUSU2MB10 ,NotFull Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
eventfld.long 0x04 20. " NEWMSGSTATUSU2MB10 ,NewMessage Clear Status bit for User 2 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x04 19. " NOTFULLSTATUSU2MB9 ,NotFull Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
eventfld.long 0x04 18. " NEWMSGSTATUSU2MB9 ,NewMessage Clear Status bit for User 2 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x04 17. " NOTFULLSTATUSU2MB8 ,NotFull Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
eventfld.long 0x04 16. " NEWMSGSTATUSU2MB8 ,NewMessage Clear Status bit for User 2 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x04 15. " NOTFULLSTATUSU2MB7 ,NotFull Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
eventfld.long 0x04 14. " NEWMSGSTATUSU2MB7 ,NewMessage Clear Status bit for User 2 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x04 13. " NOTFULLSTATUSU2MB6 ,NotFull Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
eventfld.long 0x04 12. " NEWMSGSTATUSU2MB6 ,NewMessage Clear Status bit for User 2 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x04 11. " NOTFULLSTATUSU2MB5 ,NotFull Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
eventfld.long 0x04 10. " NEWMSGSTATUSU2MB5 ,NewMessage Clear Status bit for User 2 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x04 9. " NOTFULLSTATUSU2MB4 ,NotFull Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
eventfld.long 0x04 8. " NEWMSGSTATUSU2MB4 ,NewMessage Clear Status bit for User 2 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x04 7. " NOTFULLSTATUSU2MB3 ,NotFull Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
eventfld.long 0x04 6. " NEWMSGSTATUSU2MB3 ,NewMessage Clear Status bit for User 2 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x04 5. " NOTFULLSTATUSU2MB2 ,NotFull Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
eventfld.long 0x04 4. " NEWMSGSTATUSU2MB2 ,NewMessage Clear Status bit for User 2 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x04 3. " NOTFULLSTATUSU2MB1 ,NotFull Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
eventfld.long 0x04 2. " NEWMSGSTATUSU2MB1 ,NewMessage Clear Status bit for User 2 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x04 1. " NOTFULLSTATUSU2MB0 ,NotFull Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
eventfld.long 0x04 0. " NEWMSGSTATUSU2MB0 ,NewMessage Clear Status bit for User 2 Mailbox 0" "Not pending,Pending"
line.long 0x08 "MAILBOX_IRQENABLE_SET_2,Mailbox IRQ Enable Set Register"
bitfld.long 0x08 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
bitfld.long 0x08 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Set bit for User 2 Mailbox 11" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
bitfld.long 0x08 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Set bit for User 2 Mailbox 10" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
bitfld.long 0x08 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Set bit for User 2 Mailbox 9" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
bitfld.long 0x08 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Set bit for User 2 Mailbox 8" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
bitfld.long 0x08 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Set bit for User 2 Mailbox 7" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
bitfld.long 0x08 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Set bit for User 2 Mailbox 6" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
bitfld.long 0x08 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Set bit for User 2 Mailbox 5" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
bitfld.long 0x08 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Set bit for User 2 Mailbox 4" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
bitfld.long 0x08 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Set bit for User 2 Mailbox 3" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
bitfld.long 0x08 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Set bit for User 2 Mailbox 2" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
bitfld.long 0x08 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Set bit for User 2 Mailbox 1" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
bitfld.long 0x08 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Set bit for User 2 Mailbox 0" "Disabled,Enabled"
line.long 0x0c "MAILBOX_IRQENABLE_CLR_2,Mailbox IRQ Enable Clear Register"
eventfld.long 0x0c 23. " NOTFULLENABLEU2MB11 ,NotFull Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
eventfld.long 0x0c 22. " NEWMSGENABLEU2MB11 ,NewMessage Enable Clear bit for User 2 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x0c 21. " NOTFULLENABLEU2MB10 ,NotFull Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
eventfld.long 0x0c 20. " NEWMSGENABLEU2MB10 ,NewMessage Enable Clear bit for User 2 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x0c 19. " NOTFULLENABLEU2MB9 ,NotFull Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
eventfld.long 0x0c 18. " NEWMSGENABLEU2MB9 ,NewMessage Enable Clear bit for User 2 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x0c 17. " NOTFULLENABLEU2MB8 ,NotFull Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
eventfld.long 0x0c 16. " NEWMSGENABLEU2MB8 ,NewMessage Enable Clear bit for User 2 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x0c 15. " NOTFULLENABLEU2MB7 ,NotFull Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
eventfld.long 0x0c 14. " NEWMSGENABLEU2MB7 ,NewMessage Enable Clear bit for User 2 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x0c 13. " NOTFULLENABLEU2MB6 ,NotFull Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
eventfld.long 0x0c 12. " NEWMSGENABLEU2MB6 ,NewMessage Enable Clear bit for User 2 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x0c 11. " NOTFULLENABLEU2MB5 ,NotFull Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
eventfld.long 0x0c 10. " NEWMSGENABLEU2MB5 ,NewMessage Enable Clear bit for User 2 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x0c 9. " NOTFULLENABLEU2MB4 ,NotFull Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
eventfld.long 0x0c 8. " NEWMSGENABLEU2MB4 ,NewMessage Enable Clear bit for User 2 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x0c 7. " NOTFULLENABLEU2MB3 ,NotFull Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
eventfld.long 0x0c 6. " NEWMSGENABLEU2MB3 ,NewMessage Enable Clear bit for User 2 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x0c 5. " NOTFULLENABLEU2MB2 ,NotFull Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
eventfld.long 0x0c 4. " NEWMSGENABLEU2MB2 ,NewMessage Enable Clear bit for User 2 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x0c 3. " NOTFULLENABLEU2MB1 ,NotFull Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
eventfld.long 0x0c 2. " NEWMSGENABLEU2MB1 ,NewMessage Enable Clear bit for User 2 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x0c 1. " NOTFULLENABLEU2MB0 ,NotFull Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
eventfld.long 0x0c 0. " NEWMSGENABLEU2MB0 ,NewMessage Enable Clear bit for User 2 Mailbox 0" "Not pending,Pending"
tree.end
tree "User 3 Mailbox Interrupts"
group.long (0x100+0x30)++0xf
line.long 0x00 "MAILBOX_IRQSTATUS_RAW_3,Mailbox IRQ RAW Status Register"
bitfld.long 0x00 23. " NOTFULLSTATUSU3MB11 ,NotFull Raw Status bit for User 3 Mailbox 11" "Full,Not full"
bitfld.long 0x00 22. " NEWMSGSTATUSU3MB11 ,NewMessage Raw Status bit for User 3 Mailbox 11" "No action,New message"
textline " "
bitfld.long 0x00 21. " NOTFULLSTATUSU3MB10 ,NotFull Raw Status bit for User 3 Mailbox 10" "Full,Not full"
bitfld.long 0x00 20. " NEWMSGSTATUSU3MB10 ,NewMessage Raw Status bit for User 3 Mailbox 10" "No action,New message"
textline " "
bitfld.long 0x00 19. " NOTFULLSTATUSU3MB9 ,NotFull Raw Status bit for User 3 Mailbox 9" "Full,Not full"
bitfld.long 0x00 18. " NEWMSGSTATUSU3MB9 ,NewMessage Raw Status bit for User 3 Mailbox 9" "No action,New message"
textline " "
bitfld.long 0x00 17. " NOTFULLSTATUSU3MB8 ,NotFull Raw Status bit for User 3 Mailbox 8" "Full,Not full"
bitfld.long 0x00 16. " NEWMSGSTATUSU3MB8 ,NewMessage Raw Status bit for User 3 Mailbox 8" "No action,New message"
textline " "
bitfld.long 0x00 15. " NOTFULLSTATUSU3MB7 ,NotFull Raw Status bit for User 3 Mailbox 7" "Full,Not full"
bitfld.long 0x00 14. " NEWMSGSTATUSU3MB7 ,NewMessage Raw Status bit for User 3 Mailbox 7" "No action,New message"
textline " "
bitfld.long 0x00 13. " NOTFULLSTATUSU3MB6 ,NotFull Raw Status bit for User 3 Mailbox 6" "Full,Not full"
bitfld.long 0x00 12. " NEWMSGSTATUSU3MB6 ,NewMessage Raw Status bit for User 3 Mailbox 6" "No action,New message"
textline " "
bitfld.long 0x00 11. " NOTFULLSTATUSU3MB5 ,NotFull Raw Status bit for User 3 Mailbox 5" "Full,Not full"
bitfld.long 0x00 10. " NEWMSGSTATUSU3MB5 ,NewMessage Raw Status bit for User 3 Mailbox 5" "No action,New message"
textline " "
bitfld.long 0x00 9. " NOTFULLSTATUSU3MB4 ,NotFull Raw Status bit for User 3 Mailbox 4" "Full,Not full"
bitfld.long 0x00 8. " NEWMSGSTATUSU3MB4 ,NewMessage Raw Status bit for User 3 Mailbox 4" "No action,New message"
textline " "
bitfld.long 0x00 7. " NOTFULLSTATUSU3MB3 ,NotFull Raw Status bit for User 3 Mailbox 3" "Full,Not full"
bitfld.long 0x00 6. " NEWMSGSTATUSU3MB3 ,NewMessage Raw Status bit for User 3 Mailbox 3" "No action,New message"
textline " "
bitfld.long 0x00 5. " NOTFULLSTATUSU3MB2 ,NotFull Raw Status bit for User 3 Mailbox 2" "Full,Not full"
bitfld.long 0x00 4. " NEWMSGSTATUSU3MB2 ,NewMessage Raw Status bit for User 3 Mailbox 2" "No action,New message"
textline " "
bitfld.long 0x00 3. " NOTFULLSTATUSU3MB1 ,NotFull Raw Status bit for User 3 Mailbox 1" "Full,Not full"
bitfld.long 0x00 2. " NEWMSGSTATUSU3MB1 ,NewMessage Raw Status bit for User 3 Mailbox 1" "No action,New message"
textline " "
bitfld.long 0x00 1. " NOTFULLSTATUSU3MB0 ,NotFull Raw Status bit for User 3 Mailbox 0" "Full,Not full"
bitfld.long 0x00 0. " NEWMSGSTATUSU3MB0 ,NewMessage Raw Status bit for User 3 Mailbox 0" "No action,New message"
line.long 0x04 "MAILBOX_IRQSTATUS_CLR_3,Mailbox IRQ Clear Status Register"
eventfld.long 0x04 23. " NOTFULLSTATUSU3MB11 ,NotFull Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
eventfld.long 0x04 22. " NEWMSGSTATUSU3MB11 ,NewMessage Clear Status bit for User 3 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x04 21. " NOTFULLSTATUSU3MB10 ,NotFull Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
eventfld.long 0x04 20. " NEWMSGSTATUSU3MB10 ,NewMessage Clear Status bit for User 3 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x04 19. " NOTFULLSTATUSU3MB9 ,NotFull Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
eventfld.long 0x04 18. " NEWMSGSTATUSU3MB9 ,NewMessage Clear Status bit for User 3 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x04 17. " NOTFULLSTATUSU3MB8 ,NotFull Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
eventfld.long 0x04 16. " NEWMSGSTATUSU3MB8 ,NewMessage Clear Status bit for User 3 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x04 15. " NOTFULLSTATUSU3MB7 ,NotFull Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
eventfld.long 0x04 14. " NEWMSGSTATUSU3MB7 ,NewMessage Clear Status bit for User 3 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x04 13. " NOTFULLSTATUSU3MB6 ,NotFull Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
eventfld.long 0x04 12. " NEWMSGSTATUSU3MB6 ,NewMessage Clear Status bit for User 3 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x04 11. " NOTFULLSTATUSU3MB5 ,NotFull Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
eventfld.long 0x04 10. " NEWMSGSTATUSU3MB5 ,NewMessage Clear Status bit for User 3 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x04 9. " NOTFULLSTATUSU3MB4 ,NotFull Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
eventfld.long 0x04 8. " NEWMSGSTATUSU3MB4 ,NewMessage Clear Status bit for User 3 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x04 7. " NOTFULLSTATUSU3MB3 ,NotFull Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
eventfld.long 0x04 6. " NEWMSGSTATUSU3MB3 ,NewMessage Clear Status bit for User 3 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x04 5. " NOTFULLSTATUSU3MB2 ,NotFull Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
eventfld.long 0x04 4. " NEWMSGSTATUSU3MB2 ,NewMessage Clear Status bit for User 3 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x04 3. " NOTFULLSTATUSU3MB1 ,NotFull Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
eventfld.long 0x04 2. " NEWMSGSTATUSU3MB1 ,NewMessage Clear Status bit for User 3 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x04 1. " NOTFULLSTATUSU3MB0 ,NotFull Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
eventfld.long 0x04 0. " NEWMSGSTATUSU3MB0 ,NewMessage Clear Status bit for User 3 Mailbox 0" "Not pending,Pending"
line.long 0x08 "MAILBOX_IRQENABLE_SET_3,Mailbox IRQ Enable Set Register"
bitfld.long 0x08 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
bitfld.long 0x08 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Set bit for User 3 Mailbox 11" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
bitfld.long 0x08 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Set bit for User 3 Mailbox 10" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
bitfld.long 0x08 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Set bit for User 3 Mailbox 9" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
bitfld.long 0x08 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Set bit for User 3 Mailbox 8" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
bitfld.long 0x08 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Set bit for User 3 Mailbox 7" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
bitfld.long 0x08 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Set bit for User 3 Mailbox 6" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
bitfld.long 0x08 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Set bit for User 3 Mailbox 5" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
bitfld.long 0x08 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Set bit for User 3 Mailbox 4" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
bitfld.long 0x08 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Set bit for User 3 Mailbox 3" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
bitfld.long 0x08 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Set bit for User 3 Mailbox 2" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
bitfld.long 0x08 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Set bit for User 3 Mailbox 1" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
bitfld.long 0x08 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Set bit for User 3 Mailbox 0" "Disabled,Enabled"
line.long 0x0c "MAILBOX_IRQENABLE_CLR_3,Mailbox IRQ Enable Clear Register"
eventfld.long 0x0c 23. " NOTFULLENABLEU3MB11 ,NotFull Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
eventfld.long 0x0c 22. " NEWMSGENABLEU3MB11 ,NewMessage Enable Clear bit for User 3 Mailbox 11" "Not pending,Pending"
textline " "
eventfld.long 0x0c 21. " NOTFULLENABLEU3MB10 ,NotFull Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
eventfld.long 0x0c 20. " NEWMSGENABLEU3MB10 ,NewMessage Enable Clear bit for User 3 Mailbox 10" "Not pending,Pending"
textline " "
eventfld.long 0x0c 19. " NOTFULLENABLEU3MB9 ,NotFull Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
eventfld.long 0x0c 18. " NEWMSGENABLEU3MB9 ,NewMessage Enable Clear bit for User 3 Mailbox 9" "Not pending,Pending"
textline " "
eventfld.long 0x0c 17. " NOTFULLENABLEU3MB8 ,NotFull Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
eventfld.long 0x0c 16. " NEWMSGENABLEU3MB8 ,NewMessage Enable Clear bit for User 3 Mailbox 8" "Not pending,Pending"
textline " "
eventfld.long 0x0c 15. " NOTFULLENABLEU3MB7 ,NotFull Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
eventfld.long 0x0c 14. " NEWMSGENABLEU3MB7 ,NewMessage Enable Clear bit for User 3 Mailbox 7" "Not pending,Pending"
textline " "
eventfld.long 0x0c 13. " NOTFULLENABLEU3MB6 ,NotFull Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
eventfld.long 0x0c 12. " NEWMSGENABLEU3MB6 ,NewMessage Enable Clear bit for User 3 Mailbox 6" "Not pending,Pending"
textline " "
eventfld.long 0x0c 11. " NOTFULLENABLEU3MB5 ,NotFull Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
eventfld.long 0x0c 10. " NEWMSGENABLEU3MB5 ,NewMessage Enable Clear bit for User 3 Mailbox 5" "Not pending,Pending"
textline " "
eventfld.long 0x0c 9. " NOTFULLENABLEU3MB4 ,NotFull Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
eventfld.long 0x0c 8. " NEWMSGENABLEU3MB4 ,NewMessage Enable Clear bit for User 3 Mailbox 4" "Not pending,Pending"
textline " "
eventfld.long 0x0c 7. " NOTFULLENABLEU3MB3 ,NotFull Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
eventfld.long 0x0c 6. " NEWMSGENABLEU3MB3 ,NewMessage Enable Clear bit for User 3 Mailbox 3" "Not pending,Pending"
textline " "
eventfld.long 0x0c 5. " NOTFULLENABLEU3MB2 ,NotFull Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
eventfld.long 0x0c 4. " NEWMSGENABLEU3MB2 ,NewMessage Enable Clear bit for User 3 Mailbox 2" "Not pending,Pending"
textline " "
eventfld.long 0x0c 3. " NOTFULLENABLEU3MB1 ,NotFull Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
eventfld.long 0x0c 2. " NEWMSGENABLEU3MB1 ,NewMessage Enable Clear bit for User 3 Mailbox 1" "Not pending,Pending"
textline " "
eventfld.long 0x0c 1. " NOTFULLENABLEU3MB0 ,NotFull Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
eventfld.long 0x0c 0. " NEWMSGENABLEU3MB0 ,NewMessage Enable Clear bit for User 3 Mailbox 0" "Not pending,Pending"
tree.end
width 0xb
tree.end
tree "SPINLOCK (Spinlock Registers)"
base ad:0x480ca000
width 18.
rgroup.long 0x00++0x3
line.long 0x00 "SPINLOCK_REV,IP Revision Register"
group.long 0x10++0x3
line.long 0x00 "SPINLOCK_SYSCFG,System Configuration Register"
rbitfld.long 0x00 8. " CLOCKACTIVITY ,Clock activity during IDLE mode" "Not required,Required"
rbitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
rbitfld.long 0x00 2. " ENWAKEUP ,Asynchronous wakeup generation" "Disabled,Enabled"
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No action,Reset"
rbitfld.long 0x00 0. " AUTOGATING ,Internal interface clock gating strategy" "Free-running,Applied"
rgroup.long 0x14++0x3
line.long 0x00 "SPINLOCK_SYSSTAT,System Status Register"
hexmask.long.byte 0x00 24.--31. 1. " NUMLOCKS ,Number of lock registers implemented"
bitfld.long 0x00 15. " IU7 ,In-Use flag 7" "Low,High"
bitfld.long 0x00 14. " IU6 ,In-Use flag 6" "Low,High"
bitfld.long 0x00 13. " IU5 ,In-Use flag 5" "Low,High"
bitfld.long 0x00 12. " IU4 ,In-Use flag 4" "Low,High"
textline " "
bitfld.long 0x00 11. " IU3 ,In-Use flag 3" "Low,High"
bitfld.long 0x00 10. " IU2 ,In-Use flag 2" "Low,High"
bitfld.long 0x00 9. " IU1 ,In-Use flag 1" "Low,High"
bitfld.long 0x00 8. " IU0 ,In-Use flag 0" "Low,High"
bitfld.long 0x00 0. " RESETDONE ,Reset done status" "In progress,Completed"
width 22.
tree "Lock Registers"
group.long (0x800+0x0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_0,Lock Register 0"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_1,Lock Register 1"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_2,Lock Register 2"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_3,Lock Register 3"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x10)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_4,Lock Register 4"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x14)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_5,Lock Register 5"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x18)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_6,Lock Register 6"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x1C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_7,Lock Register 7"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x20)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_8,Lock Register 8"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x24)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_9,Lock Register 9"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x28)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_10,Lock Register 10"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x2C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_11,Lock Register 11"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x30)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_12,Lock Register 12"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x34)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_13,Lock Register 13"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x38)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_14,Lock Register 14"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x3C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_15,Lock Register 15"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x40)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_16,Lock Register 16"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x44)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_17,Lock Register 17"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x48)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_18,Lock Register 18"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x4C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_19,Lock Register 19"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x50)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_20,Lock Register 20"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x54)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_21,Lock Register 21"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x58)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_22,Lock Register 22"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x5C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_23,Lock Register 23"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x60)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_24,Lock Register 24"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x64)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_25,Lock Register 25"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x68)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_26,Lock Register 26"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x6C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_27,Lock Register 27"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x70)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_28,Lock Register 28"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x74)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_29,Lock Register 29"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x78)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_30,Lock Register 30"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x7C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_31,Lock Register 31"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x80)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_32,Lock Register 32"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x84)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_33,Lock Register 33"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x88)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_34,Lock Register 34"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x8C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_35,Lock Register 35"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x90)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_36,Lock Register 36"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x94)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_37,Lock Register 37"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x98)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_38,Lock Register 38"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0x9C)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_39,Lock Register 39"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xA0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_40,Lock Register 40"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xA4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_41,Lock Register 41"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xA8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_42,Lock Register 42"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xAC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_43,Lock Register 43"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xB0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_44,Lock Register 44"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xB4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_45,Lock Register 45"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xB8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_46,Lock Register 46"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xBC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_47,Lock Register 47"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xC0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_48,Lock Register 48"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xC4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_49,Lock Register 49"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xC8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_50,Lock Register 50"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xCC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_51,Lock Register 51"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xD0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_52,Lock Register 52"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xD4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_53,Lock Register 53"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xD8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_54,Lock Register 54"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xDC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_55,Lock Register 55"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xE0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_56,Lock Register 56"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xE4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_57,Lock Register 57"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xE8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_58,Lock Register 58"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xEC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_59,Lock Register 59"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xF0)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_60,Lock Register 60"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xF4)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_61,Lock Register 61"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xF8)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_62,Lock Register 62"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
group.long (0x800+0xFC)++0x3
line.long 0x00 "SPINLOCK_LOCK_REG_63,Lock Register 63"
bitfld.long 0x00 0. " TAKEN ,Lock State" "Not taken,Taken"
tree.end
width 11.
tree.end
tree "ELM (Error Location Module)"
base ad:0x48080000
width 21.
rgroup.long 0x000++0x03
line.long 0x00 "ELM_REVISION,ELM Revision Register"
group.long 0x010++0x03
line.long 0x00 "ELM_SYSCONFIG,ELM System Configuration Register"
bitfld.long 0x00 8. " CLOCKACTIVITYOCP ,OCP Clock activity when module is in IDLE mode" "OFF,ON"
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management (IDLE req/ack control)" "Force idle,No idle,Smart idle,?..."
bitfld.long 0x00 1. " SOFTRESET ,Module Software Reset" "No reset,Reset"
textline " "
bitfld.long 0x00 0. " AUTOGATING ,Internal OCP clock gating strategy" "Free-running,Auto-gating"
rgroup.long 0x014++0x03
line.long 0x00 "ELM_SYSSTATUS,ELM System Status Register"
bitfld.long 0x00 0. " RESETDONE ,Internal Reset monitoring (OCP domain)" "On-going,Completed"
group.long 0x018++0x03
line.long 0x00 "ELM_IRQSTATUS,ELM Interrupt Status Register"
eventfld.long 0x00 8. " PAGE_VALID ,Error location status for a full page" "Invalid,Valid"
eventfld.long 0x00 7. " LOC_VALID_7 ,Error location status for syndrome polynomial 7" "In progress,Completed"
eventfld.long 0x00 6. " LOC_VALID_6 ,Error location status for syndrome polynomial 6" "In progress,Completed"
textline " "
eventfld.long 0x00 5. " LOC_VALID_5 ,Error location status for syndrome polynomial 5" "In progress,Completed"
eventfld.long 0x00 4. " LOC_VALID_4 ,Error location status for syndrome polynomial 4" "In progress,Completed"
eventfld.long 0x00 3. " LOC_VALID_3 ,Error location status for syndrome polynomial 3" "In progress,Completed"
textline " "
eventfld.long 0x00 2. " LOC_VALID_2 ,Error location status for syndrome polynomial 2" "In progress,Completed"
eventfld.long 0x00 1. " LOC_VALID_1 ,Error location status for syndrome polynomial 1" "In progress,Completed"
eventfld.long 0x00 0. " LOC_VALID_0 ,Error location status for syndrome polynomial 0" "In progress,Completed"
group.long 0x01C++0x03
line.long 0x00 "ELM_IRQENABLE,ELM Interrupt Enable Register"
bitfld.long 0x00 8. " PAGE_MASK ,Error location interrupt enable for a full page" "Disabled,Enabled"
bitfld.long 0x00 7. " LOCATION_MASK_7 ,Error location interrupt enable for syndrome polynomial 7" "Disabled,Enabled"
bitfld.long 0x00 6. " LOCATION_MASK_6 ,Error location interrupt enable for syndrome polynomial 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " LOCATION_MASK_5 ,Error location interrupt enable for syndrome polynomial 5" "Disabled,Enabled"
bitfld.long 0x00 4. " LOCATION_MASK_4 ,Error location interrupt enable for syndrome polynomial 4" "Disabled,Enabled"
bitfld.long 0x00 3. " LOCATION_MASK_3 ,Error location interrupt enable for syndrome polynomial 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " LOCATION_MASK_2 ,Error location interrupt enable for syndrome polynomial 2" "Disabled,Enabled"
bitfld.long 0x00 1. " LOCATION_MASK_1 ,Error location interrupt enable for syndrome polynomial 1" "Disabled,Enabled"
bitfld.long 0x00 0. " LOCATION_MASK_0 ,Error location interrupt enable for syndrome polynomial 0" "Disabled,Enabled"
group.long 0x020++0x03
line.long 0x00 "ELM_LOCATION_CONFIG,ELM Location Configuration Register"
hexmask.long.word 0x00 16.--26. 1. " ECC_SIZE ,Maximum size of the buffers (number of nibbles)"
bitfld.long 0x00 0.--1. " ECC_BCH_LEVEL ,Error correction level" "4 bits,8 bits,16 bits,?..."
group.long 0x080++0x03
line.long 0x00 "ELM_PAGE_CTRL,ELM Page Definition Register"
bitfld.long 0x00 7. " SECTOR_7 ,Syndrome polynomial 7 is part of the page in page mode" "Not used,Used"
bitfld.long 0x00 6. " SECTOR_6 ,Syndrome polynomial 6 is part of the page in page mode" "Not used,Used"
bitfld.long 0x00 5. " SECTOR_5 ,Syndrome polynomial 5 is part of the page in page mode" "Not used,Used"
textline " "
bitfld.long 0x00 4. " SECTOR_4 ,Syndrome polynomial 4 is part of the page in page mode" "Not used,Used"
bitfld.long 0x00 3. " SECTOR_3 ,Syndrome polynomial 3 is part of the page in page mode" "Not used,Used"
bitfld.long 0x00 2. " SECTOR_2 ,Syndrome polynomial 2 is part of the page in page mode" "Not used,Used"
textline " "
bitfld.long 0x00 1. " SECTOR_1 ,Syndrome polynomial 1 is part of the page in page mode" "Not used,Used"
bitfld.long 0x00 0. " SECTOR_0 ,Syndrome polynomial 0 is part of the page in page mode" "Not used,Used"
width 27.
tree "Syndrome Polynomial 0"
group.long (0x400+0x0)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_0,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_0,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_0,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_0,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_0,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_0,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_0,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x0)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_0,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x0)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_0,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_0,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_0,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_0,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_0,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_0,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_0,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_0,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_0,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_0,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_0,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_0,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_0,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_0,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_0,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_0,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 1"
group.long (0x400+0x40)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_1,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_1,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_1,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_1,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_1,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_1,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_1,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x100)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_1,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x100)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_1,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_1,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_1,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_1,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_1,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_1,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_1,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_1,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_1,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_1,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_1,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_1,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_1,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_1,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_1,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_1,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 2"
group.long (0x400+0x80)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_2,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_2,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_2,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_2,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_2,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_2,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_2,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x200)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_2,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x200)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_2,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_2,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_2,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_2,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_2,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_2,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_2,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_2,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_2,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_2,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_2,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_2,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_2,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_2,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_2,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_2,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 3"
group.long (0x400+0xC0)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_3,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_3,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_3,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_3,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_3,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_3,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_3,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x300)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_3,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x300)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_3,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_3,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_3,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_3,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_3,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_3,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_3,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_3,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_3,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_3,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_3,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_3,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_3,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_3,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_3,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_3,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 4"
group.long (0x400+0x100)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_4,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_4,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_4,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_4,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_4,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_4,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_4,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x400)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_4,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x400)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_4,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_4,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_4,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_4,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_4,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_4,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_4,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_4,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_4,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_4,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_4,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_4,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_4,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_4,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_4,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_4,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 5"
group.long (0x400+0x140)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_5,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_5,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_5,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_5,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_5,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_5,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_5,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x500)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_5,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x500)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_5,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_5,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_5,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_5,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_5,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_5,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_5,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_5,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_5,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_5,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_5,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_5,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_5,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_5,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_5,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_5,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 6"
group.long (0x400+0x180)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_6,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_6,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_6,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_6,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_6,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_6,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_6,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x600)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_6,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x600)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_6,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_6,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_6,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_6,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_6,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_6,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_6,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_6,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_6,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_6,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_6,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_6,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_6,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_6,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_6,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_6,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
tree "Syndrome Polynomial 7"
group.long (0x400+0x1C0)++0x1b
line.long 0x00 "ELM_SYNDROME_FRAGMENT_0_7,Input syndrome polynomial bits 0 to 31"
line.long 0x04 "ELM_SYNDROME_FRAGMENT_1_7,Input syndrome polynomial bits 32 to 63"
line.long 0x08 "ELM_SYNDROME_FRAGMENT_2_7,Input syndrome polynomial bits 64 to 95"
line.long 0x0c "ELM_SYNDROME_FRAGMENT_3_7,Input syndrome polynomial bits 96 to 127"
line.long 0x10 "ELM_SYNDROME_FRAGMENT_4_7,Input syndrome polynomial bits 128 to 159"
line.long 0x14 "ELM_SYNDROME_FRAGMENT_5_7,Input syndrome polynomial bits 160 to 191"
line.long 0x18 "ELM_SYNDROME_FRAGMENT_6_7,Input syndrome polynomial bits 192 to 207"
bitfld.long 0x18 16. " SYNDROME_VALID ,Syndrome valid bit" "Invalid,Valid"
hexmask.long.word 0x18 0.--15. 1. " SYNDROME_6 ,Syndrome bits 192 to 207"
rgroup.long (0x800+0x700)++0x03
line.long 0x00 "ELM_LOCATION_STATUS_7,Error Location Status Register"
bitfld.long 0x00 8. " ECC_CORRECTABLE ,Error location process exit status" "Failed,Successful"
bitfld.long 0x00 0.--4. " ECC_NB_ERRORS ,Number of errors detected and located" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long (0x880+0x700)++0x3f
line.long 0x00 "ELM_ERROR_LOCATION_0_7,Error Location Register"
hexmask.long.word 0x00 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x04 "ELM_ERROR_LOCATION_1_7,Error Location Register"
hexmask.long.word 0x04 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x08 "ELM_ERROR_LOCATION_2_7,Error Location Register"
hexmask.long.word 0x08 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x0c "ELM_ERROR_LOCATION_3_7,Error Location Register"
hexmask.long.word 0x0c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x10 "ELM_ERROR_LOCATION_4_7,Error Location Register"
hexmask.long.word 0x10 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x14 "ELM_ERROR_LOCATION_5_7,Error Location Register"
hexmask.long.word 0x14 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x18 "ELM_ERROR_LOCATION_6_7,Error Location Register"
hexmask.long.word 0x18 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x1c "ELM_ERROR_LOCATION_7_7,Error Location Register"
hexmask.long.word 0x1c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x20 "ELM_ERROR_LOCATION_8_7,Error Location Register"
hexmask.long.word 0x20 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x24 "ELM_ERROR_LOCATION_9_7,Error Location Register"
hexmask.long.word 0x24 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x28 "ELM_ERROR_LOCATION_10_7,Error Location Register"
hexmask.long.word 0x28 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x2c "ELM_ERROR_LOCATION_11_7,Error Location Register"
hexmask.long.word 0x2c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x30 "ELM_ERROR_LOCATION_12_7,Error Location Register"
hexmask.long.word 0x30 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x34 "ELM_ERROR_LOCATION_13_7,Error Location Register"
hexmask.long.word 0x34 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x38 "ELM_ERROR_LOCATION_14_7,Error Location Register"
hexmask.long.word 0x38 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
line.long 0x3c "ELM_ERROR_LOCATION_15_7,Error Location Register"
hexmask.long.word 0x3c 0.--12. 1. " ECC_ERROR_LOCATION ,Error location bit address"
tree.end
width 11.
tree.end
tree.open "CM (Control Module)"
base ad:0x48140000
width 16.
tree "Device BOOT Registers"
rgroup.long 0x40++0x3
line.long 0x00 "CONTROL_STATUS,Control Status Register"
bitfld.long 0x00 18.--19. " ADMUX ,GPMC CS0 Default Address Muxing" "No Addr/Data,Addr/Data,Addr/Addr/Data,?..."
bitfld.long 0x00 17. " WAITEN ,GPMC CS0 Default Wait Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " BW ,GPMC CS0 Default Bus Width" "8-bit,16-bit"
bitfld.long 0x00 0.--4. " SYSBOOT ,System Boot Type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x44++0x3
line.long 0x00 "BOOTSTAT,Boot Status Register"
bitfld.long 0x00 16.--19. " BOOTERR ,Boot Error" "No error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error,Error"
bitfld.long 0x00 0. " BC ,Boot Complete" "Not completed,Completed"
sif (cpuis("C6A816*DSP")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
rgroup.long 0x48++0x3
line.long 0x00 "DSPBOOTADDR,DSP Boot Address Register"
hexmask.long.tbyte 0x00 10.--31. 0x4 " BOOTADDR ,DSP Boot Address (upper 22 bits)"
bitfld.long 0x00 0. " RSTDONE ,DSP Reset Done" "Not done,Done"
endif
tree.end
width 16.
tree "PLL Control Registers"
group.long 0x400++0x7 "Main PLL"
line.long 0x00 "MAINPLL_CTRL,Main PLL Control Register"
hexmask.long.word 0x00 16.--31. 1. " MAIN_N ,Main PLL N multiplier value"
hexmask.long.byte 0x00 8.--15. 1. " MAIN_P ,Main PLL P divider value"
bitfld.long 0x00 7. " MAIN_LOCK ,Main PLL lock status" "Low,High"
bitfld.long 0x00 3. " MAIN_PLLEN ,Main PLL enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " MAIN_BP ,Main PLL bypass enable" "Disabled,Enabled"
bitfld.long 0x00 0. " MAIN_LOC_CTL ,Select the source to detect PLL lock" "0,1"
line.long 0x04 "MAINPLL_PWD,Main Powerdown Register"
bitfld.long 0x04 7. " PWD_CLK7 ,Main PLL Clock7 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 6. " PWD_CLK6 ,Main PLL Clock6 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 5. " PWD_CLK5 ,Main PLL Clock5 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 4. " PWD_CLK4 ,Main PLL Clock4 Powerdown" "Powered up,Powered down"
textline " "
bitfld.long 0x04 2. " PWD_CLK2 ,Main PLL Clock2 Powerdown" "Powered up,Powered down"
sif (cpuis("C6A816*")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
bitfld.long 0x04 1. " PWD_CLK1 ,Main PLL Clock1 Powerdown" "Powered up,Powered down"
endif
sif (cpuis("C6A816*")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
group.long 0x408++0x7
line.long 0x00 "MAINPLL_FREQ1,Main PLL Frequency 1 Register"
bitfld.long 0x00 31. " MAIN_LDFREQ1 ,Load Synth1 FREQ value" "Not loaded,Loaded"
bitfld.long 0x00 28. " MAIN_TRUNC1 ,Synth1 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x00 24.--27. " MAIN_INTFREQ1 ,Synth1 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--23. 1. " MAIN_FRACFREQ1 ,Synth1 Frequency fractional divider"
line.long 0x04 "MAINPLL_DIV1,Main PLL Divider 1 Register"
bitfld.long 0x04 8. " MAIN_LDMDIV1 ,Load Synth1 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x04 0.--7. 1. " MAIN_MDIV1 ,Synth1 Frequency M Post Divider"
endif
group.long 0x410++0x7
line.long 0x00 "MAINPLL_FREQ2,Main PLL Frequency 2 Register"
bitfld.long 0x00 31. " MAIN_LDFREQ2 ,Load Synth2 FREQ value" "Not loaded,Loaded"
bitfld.long 0x00 28. " MAIN_TRUNC2 ,Synth2 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x00 24.--27. " MAIN_INTFREQ2 ,Synth2 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--23. 1. " MAIN_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long 0x04 "MAINPLL_DIV2,Main PLL Divider 2 Register"
bitfld.long 0x04 8. " MAIN_LDMDIV2 ,Load Synth2 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x04 0.--7. 1. " MAIN_MDIV2 ,Synth2 Frequency M Post Divider"
sif (cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
group.long 0x418++0x3
line.long 0x00 "MAINPLL_FREQ3,Main PLL Frequency 3 Register"
bitfld.long 0x00 31. " MAIN_LDFREQ3 ,Load Synth3 FREQ value" "Not loaded,Loaded"
bitfld.long 0x00 28. " MAIN_TRUNC3 ,Synth3 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x00 24.--27. " MAIN_INTFREQ3 ,Synth3 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--23. 1. " MAIN_FRACFREQ3 ,Synth3 Frequency fractional divider"
group.long 0x41c++0x3
line.long 0x00 "MAINPLL_DIV3,Main PLL Divider 3 Register"
bitfld.long 0x00 8. " MAIN_LDMDIV3 ,Load Synth3 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x00 0.--7. 1. " MAIN_MDIV3 ,Synth3 Frequency M Post Divider"
endif
group.long 0x420++0xf
line.long 0x00 "MAINPLL_FREQ4,Main PLL Frequency 4 Register"
bitfld.long 0x00 31. " MAIN_LDFREQ4 ,Load Synth4 FREQ value" "Not loaded,Loaded"
bitfld.long 0x00 28. " MAIN_TRUNC4 ,Synth4 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x00 24.--27. " MAIN_INTFREQ4 ,Synth4 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x00 0.--23. 1. " MAIN_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long 0x04 "MAINPLL_DIV4,Main PLL Divider 4 Register"
bitfld.long 0x04 8. " MAIN_LDMDIV4 ,Load Synth4 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x04 0.--7. 1. " MAIN_MDIV4 ,Synth4 Frequency M Post Divider"
line.long 0x08 "MAINPLL_FREQ5,Main PLL Frequency 5 Register"
bitfld.long 0x08 31. " MAIN_LDFREQ5 ,Load Synth5 FREQ value" "Not loaded,Loaded"
bitfld.long 0x08 28. " MAIN_TRUNC5 ,Synth5 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x08 24.--27. " MAIN_INTFREQ5 ,Synth5 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x08 0.--23. 1. " MAIN_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long 0x0c "MAINPLL_DIV5,Main PLL Divider 5 Register"
bitfld.long 0x0c 8. " MAIN_LDMDIV5 ,Load Synth5 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x0c 0.--7. 1. " MAIN_MDIV5 ,Synth5 Frequency M Post Divider"
group.long 0x434++0x3
line.long 0x00 "MAINPLL_DIV6,Main PLL Divider 6 Register"
bitfld.long 0x00 8. " MAIN_LDMDIV6 ,Load M Divider 6 value" "Not loaded,Loaded"
hexmask.long.byte 0x00 0.--7. 1. " MAIN_MDIV6 ,Frequency M Post Divider 6"
group.long 0x43c++0x3
line.long 0x00 "MAINPLL_DIV7,Main PLL Divider 7 Register"
bitfld.long 0x00 8. " MAIN_LDMDIV7 ,Load M Divider 7 value" "Not loaded,Loaded"
hexmask.long.byte 0x00 0.--7. 1. " MAIN_MDIV7 ,Frequency M Post Divider 7"
group.long 0x440++0x7 "DDR PLL"
line.long 0x00 "DDRPLL_CTRL,DDR PLL Control Register"
hexmask.long.word 0x00 16.--31. 1. " DDR_N ,DDR PLL N multiplier value"
hexmask.long.byte 0x00 8.--15. 1. " DDR_P ,DDR PLL P divider value"
bitfld.long 0x00 7. " DDR_LOCK ,DDR PLL lock status" "Low,High"
bitfld.long 0x00 3. " DDR_PLLEN ,DDR PLL enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " DDR_BP ,DDR PLL bypass enable" "Disabled,Enabled"
bitfld.long 0x00 0. " DDR_LOC_CTL ,Select the source to detect PLL lock" "0,1"
line.long 0x04 "DDRPLL_PWD,DDR Powerdown Register"
bitfld.long 0x04 5. " PWD_CLK5 ,DDR PLL Clock5 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 4. " PWD_CLK4 ,DDR PLL Clock4 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 3. " PWD_CLK3 ,DDR PLL Clock3 Powerdown" "Powered up,Powered down"
textline " "
bitfld.long 0x04 2. " PWD_CLK2 ,DDR PLL Clock2 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 1. " PWD_CLK1 ,DDR PLL Clock1 Powerdown" "Powered up,Powered down"
group.long 0x44c++0x23
line.long 0x00 "DDRPLL_DIV1,DDR PLL Divider 1 Register"
bitfld.long 0x00 8. " DDR_LDMDIV1 ,Load Synth1 M Divider value" "Not loaded,Loaded"
hexmask.long.byte 0x00 0.--7. 1. " DDR_MDIV1 ,Synth1 Frequency M Post Divider"
line.long 0x4 "DDRPLL_FREQ2,DDR PLL Frequency 2 Register"
bitfld.long 0x4 31. " DDR_LDFREQ2 ,Load Synth2 FREQ value" "Not loaded,Loaded"
bitfld.long 0x4 28. " DDR_TRUNC2 ,Synth2 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x4 24.--27. " DDR_INTFREQ2 ,Synth2 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x4 0.--23. 1. " DDR_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long (0x4+0x4) "DDRPLL_DIV2,DDR PLL Divider 2 Register"
bitfld.long (0x4+0x4) 8. " DDR_LDMDIV2 ,Load Synth2 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x4+0x4) 0.--7. 1. " DDR_MDIV2 ,Synth2 Frequency M Post Divider"
line.long 0xC "DDRPLL_FREQ3,DDR PLL Frequency 3 Register"
bitfld.long 0xC 31. " DDR_LDFREQ3 ,Load Synth3 FREQ value" "Not loaded,Loaded"
bitfld.long 0xC 28. " DDR_TRUNC3 ,Synth3 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0xC 24.--27. " DDR_INTFREQ3 ,Synth3 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0xC 0.--23. 1. " DDR_FRACFREQ3 ,Synth3 Frequency fractional divider"
line.long (0xC+0x4) "DDRPLL_DIV3,DDR PLL Divider 3 Register"
bitfld.long (0xC+0x4) 8. " DDR_LDMDIV3 ,Load Synth3 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0xC+0x4) 0.--7. 1. " DDR_MDIV3 ,Synth3 Frequency M Post Divider"
line.long 0x14 "DDRPLL_FREQ4,DDR PLL Frequency 4 Register"
bitfld.long 0x14 31. " DDR_LDFREQ4 ,Load Synth4 FREQ value" "Not loaded,Loaded"
bitfld.long 0x14 28. " DDR_TRUNC4 ,Synth4 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x14 24.--27. " DDR_INTFREQ4 ,Synth4 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x14 0.--23. 1. " DDR_FRACFREQ4 ,Synth4 Frequency fractional divider"
line.long (0x14+0x4) "DDRPLL_DIV4,DDR PLL Divider 4 Register"
bitfld.long (0x14+0x4) 8. " DDR_LDMDIV4 ,Load Synth4 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x14+0x4) 0.--7. 1. " DDR_MDIV4 ,Synth4 Frequency M Post Divider"
line.long 0x1C "DDRPLL_FREQ5,DDR PLL Frequency 5 Register"
bitfld.long 0x1C 31. " DDR_LDFREQ5 ,Load Synth5 FREQ value" "Not loaded,Loaded"
bitfld.long 0x1C 28. " DDR_TRUNC5 ,Synth5 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x1C 24.--27. " DDR_INTFREQ5 ,Synth5 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x1C 0.--23. 1. " DDR_FRACFREQ5 ,Synth5 Frequency fractional divider"
line.long (0x1C+0x4) "DDRPLL_DIV5,DDR PLL Divider 5 Register"
bitfld.long (0x1C+0x4) 8. " DDR_LDMDIV5 ,Load Synth5 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x1C+0x4) 0.--7. 1. " DDR_MDIV5 ,Synth5 Frequency M Post Divider"
group.long 0x470++0x1f "Video PLL"
line.long 0x00 "VIDEOPLL_CTRL,Video PLL Control Register"
hexmask.long.word 0x00 16.--31. 1. " VIDEO_N ,Video PLL N multiplier value"
hexmask.long.byte 0x00 8.--15. 1. " VIDEO_P ,Video PLL P divider value"
bitfld.long 0x00 7. " VIDEO_LOCK ,Video PLL lock status" "Low,High"
bitfld.long 0x00 3. " VIDEO_PLLEN ,Video PLL enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " VIDEO_BP ,Video PLL bypass enable" "Disabled,Enabled"
bitfld.long 0x00 0. " VIDEO_LOC_CTL ,Select the source to detect PLL lock" "0,1"
line.long 0x04 "VIDEOPLL_PWD,Video Powerdown Register"
bitfld.long 0x04 3. " PWD_CLK3 ,Video PLL Clock3 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 2. " PWD_CLK2 ,Video PLL Clock2 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 1. " PWD_CLK1 ,Video PLL Clock1 Powerdown" "Powered up,Powered down"
line.long 0x8 "VIDEOPLL_FREQ1,Video PLL Frequency 1 Register"
bitfld.long 0x8 31. " VIDEO_LDFREQ1 ,Load Synth1 FREQ value" "Not loaded,Loaded"
bitfld.long 0x8 28. " VIDEO_TRUNC1 ,Synth1 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x8 24.--27. " VIDEO_INTFREQ1 ,Synth1 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x8 0.--23. 1. " VIDEO_FRACFREQ1 ,Synth1 Frequency fractional divider"
line.long (0x8+0x4) "VIDEOPLL_DIV1,Video PLL Divider 1 Register"
bitfld.long (0x8+0x4) 8. " VIDEO_LDMDIV1 ,Load Synth1 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x8+0x4) 0.--7. 1. " VIDEO_MDIV1 ,Synth1 Frequency M Post Divider"
line.long 0x10 "VIDEOPLL_FREQ2,Video PLL Frequency 2 Register"
bitfld.long 0x10 31. " VIDEO_LDFREQ2 ,Load Synth2 FREQ value" "Not loaded,Loaded"
bitfld.long 0x10 28. " VIDEO_TRUNC2 ,Synth2 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x10 24.--27. " VIDEO_INTFREQ2 ,Synth2 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x10 0.--23. 1. " VIDEO_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long (0x10+0x4) "VIDEOPLL_DIV2,Video PLL Divider 2 Register"
bitfld.long (0x10+0x4) 8. " VIDEO_LDMDIV2 ,Load Synth2 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x10+0x4) 0.--7. 1. " VIDEO_MDIV2 ,Synth2 Frequency M Post Divider"
line.long 0x18 "VIDEOPLL_FREQ3,Video PLL Frequency 3 Register"
bitfld.long 0x18 31. " VIDEO_LDFREQ3 ,Load Synth3 FREQ value" "Not loaded,Loaded"
bitfld.long 0x18 28. " VIDEO_TRUNC3 ,Synth3 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x18 24.--27. " VIDEO_INTFREQ3 ,Synth3 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x18 0.--23. 1. " VIDEO_FRACFREQ3 ,Synth3 Frequency fractional divider"
line.long (0x18+0x4) "VIDEOPLL_DIV3,Video PLL Divider 3 Register"
bitfld.long (0x18+0x4) 8. " VIDEO_LDMDIV3 ,Load Synth3 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x18+0x4) 0.--7. 1. " VIDEO_MDIV3 ,Synth3 Frequency M Post Divider"
group.long 0x4a0++0x7 "Audio PLL"
line.long 0x00 "AUDIOPLL_CTRL,Audio PLL Control Register"
hexmask.long.word 0x00 16.--31. 1. " AUDIO_N ,Audio PLL N multiplier value"
hexmask.long.byte 0x00 8.--15. 1. " AUDIO_P ,Audio PLL P divider value"
bitfld.long 0x00 7. " AUDIO_LOCK ,Audio PLL lock status" "Low,High"
bitfld.long 0x00 3. " AUDIO_PLLEN ,Audio PLL enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " AUDIO_BP ,Audio PLL bypass enable" "Disabled,Enabled"
bitfld.long 0x00 0. " AUDIO_LOC_CTL ,Select the source to detect PLL lock" "0,1"
line.long 0x04 "AUDIOPLL_PWD,Audio Powerdown Register"
bitfld.long 0x04 5. " PWD_CLK5 ,Audio PLL Clock5 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 4. " PWD_CLK4 ,Audio PLL Clock4 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 3. " PWD_CLK3 ,Audio PLL Clock3 Powerdown" "Powered up,Powered down"
bitfld.long 0x04 2. " PWD_CLK2 ,Audio PLL Clock2 Powerdown" "Powered up,Powered down"
group.long 0x4b0++0x1f
line.long 0x0 "AUDIOPLL_FREQ2,Audio PLL Frequency 2 Register"
bitfld.long 0x0 31. " AUDIO_LDFREQ2 ,Load Synth2 FREQ value" "Not loaded,Loaded"
bitfld.long 0x0 28. " AUDIO_TRUNC2 ,Synth2 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x0 24.--27. " AUDIO_INTFREQ2 ,Synth2 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x0 0.--23. 1. " AUDIO_FRACFREQ2 ,Synth2 Frequency fractional divider"
line.long (0x0+0x4) "AUDIOPLL_DIV2,Audio PLL Divider 2 Register"
bitfld.long (0x0+0x4) 8. " AUDIO_LDMDIV2 ,Load Synth2 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x0+0x4) 0.--7. 1. " AUDIO_MDIV2 ,Synth2 Frequency M Post Divider"
line.long 0x8 "AUDIOPLL_FREQ3,Audio PLL Frequency 3 Register"
bitfld.long 0x8 31. " AUDIO_LDFREQ3 ,Load Synth3 FREQ value" "Not loaded,Loaded"
bitfld.long 0x8 28. " AUDIO_TRUNC3 ,Synth3 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x8 24.--27. " AUDIO_INTFREQ3 ,Synth3 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x8 0.--23. 1. " AUDIO_FRACFREQ3 ,Synth3 Frequency fractional divider"
line.long (0x8+0x4) "AUDIOPLL_DIV3,Audio PLL Divider 3 Register"
bitfld.long (0x8+0x4) 8. " AUDIO_LDMDIV3 ,Load Synth3 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x8+0x4) 0.--7. 1. " AUDIO_MDIV3 ,Synth3 Frequency M Post Divider"
line.long 0x10 "AUDIOPLL_FREQ4,Audio PLL Frequency 4 Register"
bitfld.long 0x10 31. " AUDIO_LDFREQ4 ,Load Synth4 FREQ value" "Not loaded,Loaded"
bitfld.long 0x10 28. " AUDIO_TRUNC4 ,Synth4 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x10 24.--27. " AUDIO_INTFREQ4 ,Synth4 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x10 0.--23. 1. " AUDIO_FRACFREQ4 ,Synth4 Frequency fractional divider"
line.long (0x10+0x4) "AUDIOPLL_DIV4,Audio PLL Divider 4 Register"
bitfld.long (0x10+0x4) 8. " AUDIO_LDMDIV4 ,Load Synth4 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x10+0x4) 0.--7. 1. " AUDIO_MDIV4 ,Synth4 Frequency M Post Divider"
line.long 0x18 "AUDIOPLL_FREQ5,Audio PLL Frequency 5 Register"
bitfld.long 0x18 31. " AUDIO_LDFREQ5 ,Load Synth5 FREQ value" "Not loaded,Loaded"
bitfld.long 0x18 28. " AUDIO_TRUNC5 ,Synth5 Enable Truncate Correction" "Disabled,Enabled"
bitfld.long 0x18 24.--27. " AUDIO_INTFREQ5 ,Synth5 Frequency integer divider" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.tbyte 0x18 0.--23. 1. " AUDIO_FRACFREQ5 ,Synth5 Frequency fractional divider"
line.long (0x18+0x4) "AUDIOPLL_DIV5,Audio PLL Divider 5 Register"
bitfld.long (0x18+0x4) 8. " AUDIO_LDMDIV5 ,Load Synth5 M Divider value" "Not loaded,Loaded"
hexmask.long.byte (0x18+0x4) 0.--7. 1. " AUDIO_MDIV5 ,Synth5 Frequency M Post Divider"
tree.end
width 18.
tree "Device Configuration Registers"
rgroup.long 0x600++0x3
line.long 0x00 "DEVICE_ID,Device Identification Register"
bitfld.long 0x00 28.--31. " DEVREV ,Device revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 12.--27. 1. " PARTNUM ,Device part number"
hexmask.long.word 0x00 1.--11. 1. " MFGR ,Manufacturer's JTAG ID"
group.long 0x608++0x7
line.long 0x00 "INIT_PRESSURE_0,Initiator Pressure 0 Register"
bitfld.long 0x00 30.--31. " TCWR3 ,TPTC 3 Write Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 28.--29. " TCRD3 ,TPTC 3 Read Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 26.--27. " TCWR2 ,TPTC 2 Write Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 24.--25. " TCRD2 ,TPTC 2 Read Port initiator pressure" "0,1,2,3"
textline " "
bitfld.long 0x00 22.--23. " TCWR1 ,TPTC 1 Write Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 20.--21. " TCRD1 ,TPTC 1 Read Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 18.--19. " TCWR0 ,TPTC 0 Write Port initiator pressure" "0,1,2,3"
bitfld.long 0x00 16.--17. " TCRD0 ,TPTC 0 Read Port initiator pressure" "0,1,2,3"
textline " "
bitfld.long 0x00 14.--15. " JTAG ,JTAG Interface Port Initiator pressure" "0,1,2,3"
bitfld.long 0x00 10.--11. " DSS1 ,Display Subsystem Port 1 initiator pressure" "0,1,2,3"
bitfld.long 0x00 8.--9. " DSS0 ,Display Subsystem Port 0 initiator pressure" "0,1,2,3"
bitfld.long 0x00 6.--7. " DEMMU ,System DEMMU initiator pressure" "0,1,2,3"
textline " "
sif (cpuis("C6A816*DSP")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
bitfld.long 0x00 4.--5. " GEM_CFG ,C674x CFG port initiator pressure" "0,1,2,3"
bitfld.long 0x00 2.--3. " GEM_MDMA ,C674x MDMA port initiator pressure" "0,1,2,3"
bitfld.long 0x00 0.--1. " HOST_ARM ,Host Cortex A8 initiator pressure" "0,1,2,3"
else
bitfld.long 0x00 0.--1. " HOST_ARM ,Cortex A8 initiator pressure" "0,1,2,3"
endif
line.long 0x04 "INIT_PRESSURE_1,Initiator Pressure 1 Register"
sif (cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
bitfld.long 0x04 30.--31. "IVAHD2,IVAHD2 (HDVICP2-2) initiator pressure" "0,1,2,3"
bitfld.long 0x04 28.--29. "IVAHD1,IVAHD1 (HDVICP2-1) initiator pressure" "0,1,2,3"
bitfld.long 0x04 26.--27. "IVAHD0,IVAHD0 (HDVICP2-0) initiator pressure" "0,1,2,3"
textline " "
endif
bitfld.long 0x04 24.--25. " DEBUG ,Debug Subsystem initiator pressure" "0,1,2,3"
bitfld.long 0x04 22.--23. " EXP ,Expansion Slot Port initiator pressure" "0,1,2,3"
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="C6A8168DSP"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
bitfld.long 0x04 20.--21. " GRFX ,SGX530 initiator pressure" "0,1,2,3"
endif
textline " "
bitfld.long 0x04 16.--17. " PCIE ,PCIe initiator pressure" "0,1,2,3"
bitfld.long 0x04 14.--15. " DSS_CTLR ,HDVPSS Controller (Ducati) initiator pressure" "0,1,2,3"
bitfld.long 0x04 8.--9. " SATA ,SATA initiator pressure" "0,1,2,3"
bitfld.long 0x04 6.--7. " USB_QMGR ,USB Queue Manager initiator pressure" "0,1,2,3"
textline " "
bitfld.long 0x04 4.--5. " USB_DMA ,USB DMA port initiator pressure" "0,1,2,3"
bitfld.long 0x04 2.--3. " CPGMAC1 ,CPGMAC1 initiator pressure" "0,1,2,3"
bitfld.long 0x04 0.--1. " CPGMAC0 ,CPGMAC0 initiator pressure" "0,1,2,3"
width 18.
sif (cpuis("C6A816*DSP")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
group.long 0x610++0x3
line.long 0x00 "MMU_CFG,MMU Configuration Register"
bitfld.long 0x00 15. " MMU_ABORT ,MMU abort operation enable" "Disabled,Enabled"
bitfld.long 0x00 7. " MMU_EN ,MMU Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " EXPMMU ,Expansion Slot Uses MMU" "Low,High"
bitfld.long 0x00 0. " TC0MMU ,TPTC0 Uses MMU" "Low,High"
endif
group.long 0x614++0x7
line.long 0x00 "TPTC_CFG,TPTC Configuration Register"
bitfld.long 0x00 6.--7. " TC3DBS ,TC3 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
bitfld.long 0x00 4.--5. " TC2DBS ,TC2 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
bitfld.long 0x00 2.--3. " TC1DBS ,TC1 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
bitfld.long 0x00 0.--1. " TC0DBS ,TC0 Default Burst Size" "16 byte,32 byte,64 byte,128 byte"
line.long 0x04 "DDR_CTRL,DDR Control Register"
bitfld.long 0x04 29. " FORCE_PHY_RST ,Force DDR Phy Reset" "Not forced,Forced"
bitfld.long 0x04 28. " DIS_DEV_RST ,Disable DDR Device Reset" "No,Yes"
bitfld.long 0x04 25. " KEEPSREF1 ,Keep DDR1 Self Refreshed" "Not refreshed,Refreshed"
bitfld.long 0x04 24. " SREF1 ,Enable DDR1 Self Refresh" "Disabled,Enabled"
textline " "
bitfld.long 0x04 18.--19. " DDRDATA_SLEW1 ,DDR1 Data Slew" "0,1,2,3"
bitfld.long 0x04 16.--17. " DDRCMD_SLEW1 ,DDR1 CMD Slew" "0,1,2,3"
bitfld.long 0x04 9. " KEEPSREF0 ,Keep DDR0 Self Refreshed" "Not refreshed,Refreshed"
bitfld.long 0x04 8. " SREF0 ,Enable DDR0 Self Refresh" "Disabled,Enabled"
textline " "
bitfld.long 0x04 2.--3. " DDRDATA_SLEW0 ,DDR0 Data Slew" "0,1,2,3"
bitfld.long 0x04 0.--1. " DDRCMD_SLEW0 ,DDR0 CMD Slew" "0,1,2,3"
sif (cpuis("C6A816*DSP")||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
width 18.
group.long 0x61c++0x3
line.long 0x00 "DSP_IDLE_CFG,DSP Standby/Idle Management Register"
sif (cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
bitfld.long 0x00 15. " DSPSTBY ,Assert DSP Standby" "De-asserted,Asserted"
textline " "
endif
bitfld.long 0x00 4.--5. " STBYMODE ,Initiator state management mode" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup-capable"
textline " "
bitfld.long 0x00 2.--3. " IDLEMODE ,Target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
endif
width 18.
group.long 0x620++0x3
line.long 0x00 "USB_CTRL,USB Control Register"
bitfld.long 0x00 8. " PHYCLKSRC ,USB PHY reference clock source" "PLL,USB"
bitfld.long 0x00 1. " PHYSLEEP1 ,USB PHY1 sleep mode control" "Sleep,Normal"
bitfld.long 0x00 0. " PHYSLEEP0 ,USB PHY0 sleep mode control" "Sleep,Normal"
group.long 0x624++0x3
line.long 0x00 "USBPHY_CTRL0,USB Phy Control Register 0"
bitfld.long 0x00 28.--30. " COMPDISTUNE ,Disconnect Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. " OTGTUNE ,VBUS Valid Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. " SQRXTUNE ,Squelch Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. " TXFSLSTUNE ,FS/LS Source Impedance Adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 13.--14. " TXPREEMTUNE ,HS Transmit Pre-Emphasis Enable" "0,1,2,3"
bitfld.long 0x00 12. " TXRISETUNE ,HS Transmit Rise/Fall Time Adjust" "0,1"
bitfld.long 0x00 8.--11. " TXVREFTUNE ,HS DC Voltage Level Adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--5. " TXHSXVTUNE ,Transmit High-Speed Crossover Adjust" "0,1,2,3"
group.long 0x62C++0x3
line.long 0x00 "USBPHY_CTRL1,USB Phy Control Register 1"
bitfld.long 0x00 28.--30. " COMPDISTUNE ,Disconnect Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. " OTGTUNE ,VBUS Valid Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 20.--22. " SQRXTUNE ,Squelch Threshold Adjust" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--19. " TXFSLSTUNE ,FS/LS Source Impedance Adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 13.--14. " TXPREEMTUNE ,HS Transmit Pre-Emphasis Enable" "0,1,2,3"
bitfld.long 0x00 12. " TXRISETUNE ,HS Transmit Rise/Fall Time Adjust" "0,1"
bitfld.long 0x00 8.--11. " TXVREFTUNE ,HS DC Voltage Level Adjust" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--5. " TXHSXVTUNE ,Transmit High-Speed Crossover Adjust" "0,1,2,3"
rgroup.long 0x630++0xf
line.long 0x0 "MAC_ID0_LO,Ethernet MAC ID0 Low Register"
hexmask.long.byte 0x0 8.--15. 1. " MACADDR[7:0] ,MAC0 Address - Byte 0"
hexmask.long.byte 0x0 0.--7. 1. " MACADDR[15:8] ,MAC0 Address - Byte 1"
line.long (0x0+0x4) "MAC_ID0_HI,Ethernet MAC ID0 High Register"
hexmask.long.byte (0x0+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC0 Address - Byte 2"
hexmask.long.byte (0x0+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC0 Address - Byte 3"
hexmask.long.byte (0x0+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC0 Address - Byte 4"
hexmask.long.byte (0x0+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC0 Address - Byte 5"
line.long 0x8 "MAC_ID0_LO,Ethernet MAC ID1 Low Register"
hexmask.long.byte 0x8 8.--15. 1. " MACADDR[7:0] ,MAC1 Address - Byte 0"
hexmask.long.byte 0x8 0.--7. 1. " MACADDR[15:8] ,MAC1 Address - Byte 1"
line.long (0x8+0x4) "MAC_ID0_HI,Ethernet MAC ID1 High Register"
hexmask.long.byte (0x8+0x4) 24.--31. 1. " MACADDR[23:16] ,MAC1 Address - Byte 2"
hexmask.long.byte (0x8+0x4) 16.--23. 1. " MACADDR[31:24] ,MAC1 Address - Byte 3"
hexmask.long.byte (0x8+0x4) 8.--15. 1. " MACADDR[39:32] ,MAC1 Address - Byte 4"
hexmask.long.byte (0x8+0x4) 0.--7. 1. " MACADDR[47:40] ,MAC1 Address - Byte 5"
group.long 0x640++0x3
line.long 0x00 "PCIE_CFG,PCIE Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " PCIE_CFGPLL ,PCIe PLL Configuration"
bitfld.long 0x00 8.--11. " PCIE_STSPLL ,PCIe PLL Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--1. " PCIE_DEVTYPE ,PCIe Module Device Type" "EP,Legacy EP,RC,?..."
width 18.
group.long 0x648++0x7
line.long 0x00 "CLK_CTL,Clock Control Register"
bitfld.long 0x00 3. " DEVRSELECT ,Device (27 MHz) Oscillator Bias Resistor" "Connected,Disconnected"
bitfld.long 0x00 1.--2. " DEVSW ,Device Oscillator Frequency Selection" "5-20 MHz,20-30 MHz,30-40 MHz,40-50 MHz"
line.long 0x04 "AUD_CTRL,Audio Interface Control Register"
bitfld.long 0x04 17. " MCB_LBFSX ,McBSP FSX Loopback enable" "Disabled,Enabled"
bitfld.long 0x04 16. " MCB_LBCLKX ,McBSP CLKX Loopback enable" "Disabled,Enabled"
bitfld.long 0x04 2. " ASP2MUTESRC ,McASP2 AMUTEIN source select" "MCA2_AMUTEIN,MCA0_AMUTEIN"
bitfld.long 0x04 1. " ASP1MUTESRC ,McASP1 AMUTEIN source select" "MCA1_AMUTEIN,MCA0_AMUTEIN"
sif (cpuis("C6A816*DSP")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
group.long 0x650++0x3
line.long 0x00 "DSPMEM_SLEEP,DSP L2 Memory Sleep Mode Register"
bitfld.long 0x00 2. " DSPMEM_SD ,DSP L2 Memory in Shutdown Mode" "Normal,Shutdown"
bitfld.long 0x00 1. " DSPMEM_DS ,DSP L2 Memory in Deep Sleep Mode" "Normal,Deep Sleep"
bitfld.long 0x00 0. " DSPMEM_LS ,DSP L2 Memory in Light Sleep Mode" "Normal,Light Sleep"
endif
group.long 0x650++0x03
line.long 0x00 "DSPMEM_SLEEP,DSP L2 Memory Sleep Mode Register"
bitfld.long 0x00 2. " DSPMEM_SD ,OCM0 Memory in Shutdown Mode" "Normal,Shutdown"
bitfld.long 0x00 1. " DSPMEM_DS ,OCM0 Memory in Deep Sleep Mode" "Normal,Deep Sleep"
bitfld.long 0x00 0. " DSPMEM_LS ,OCM0 Memory in Light Sleep Mode" "Normal,Light Sleep"
group.long 0x654++0x3
line.long 0x00 "OCMEM_SLEEP,On-Chip Memory Sleep Mode Register"
bitfld.long 0x00 6. " OCM1_SD ,OCM1 Memory in Shutdown Mode" "Normal,Shutdown"
bitfld.long 0x00 5. " OCM1_DS ,OCM1 Memory in Deep Sleep Mode" "Normal,Deep Sleep"
bitfld.long 0x00 4. " OCM1_LS ,OCM1 Memory in Light Sleep Mode" "Normal,Light Sleep"
textline " "
bitfld.long 0x00 2. " OCM0_SD ,OCM0 Memory in Shutdown Mode" "Normal,Shutdown"
bitfld.long 0x00 1. " OCM0_DS ,OCM0 Memory in Deep Sleep Mode" "Normal,Deep Sleep"
bitfld.long 0x00 0. " OCM0_LS ,OCM0 Memory in Light Sleep Mode" "Normal,Light Sleep"
group.long 0x660++0x3f
line.long 0x00 "HD_DAC_CTRL,HD DAC Control Register"
bitfld.long 0x00 3. " HD_CALSEL ,HD DAC Calibration Select" "Normal,Output"
bitfld.long 0x00 1.--2. " HD_MIDRND ,HD DAC MID randomizer mode" "Bypass,Swap 1,Swap 2,Bit shift"
bitfld.long 0x00 0. " RESET_HD ,Reset HD DAC" "No reset,Reset"
line.long 0x04 "HD_DACA_CAL,HD DAC A Calibration Register"
hexmask.long.word 0x04 0.--11. 1. " HDDAC_A_CAL ,HD DAC A calibration value"
line.long 0x08 "HD_DACB_CAL,HD DAC B Calibration Register"
hexmask.long.word 0x08 0.--11. 1. " HDDAC_B_CAL ,HD DAC B calibration value"
line.long 0x0c "HD_DACC_CAL,HD DAC C Calibration Register"
hexmask.long.word 0x0c 0.--11. 1. " HDDAC_C_CAL ,HD DAC C calibration value"
line.long 0x10 "SD_DAC_CTRL,SD DAC Control Register"
bitfld.long 0x10 3. " SD_CALSEL ,SD DAC Calibration Select" "Normal,Output"
bitfld.long 0x10 1.--2. " SD_MIDRND ,SD DAC MID randomizer mode" "Bypass,Swap 1,Swap 2,Bit shift"
bitfld.long 0x10 0. " RESET_SD ,Reset SD DAC" "No reset,Reset"
line.long 0x14 "SD_DACA_CAL,SD DAC A Calibration Register"
hexmask.long.word 0x14 0.--9. 1. " SDDAC_A_CAL ,SD DAC A calibration value"
line.long 0x18 "SD_DACB_CAL,SD DAC B Calibration Register"
hexmask.long.word 0x18 0.--9. 1. " SDDAC_B_CAL ,SD DAC B calibration value"
line.long 0x1c "SD_DACC_CAL,SD DAC C Calibration Register"
hexmask.long.word 0x1c 0.--9. 1. " SDDAC_C_CAL ,SD DAC C calibration value"
line.long 0x20 "SD_DACD_CAL,SD DAC D Calibration Register"
hexmask.long.word 0x20 0.--9. 1. " SDDAC_D_CAL ,SD DAC D calibration value"
sif ((!cpuis("DM8165"))&&(!cpuis("DM8166"))&&(!cpuis("DM8167"))&&(!cpuis("DM8168"))&&(!cpuis("DM8165DSP"))&&(!cpuis("DM8166DSP"))&&(!cpuis("DM8167DSP"))&&(!cpuis("DM8168DSP")))
line.long 0x24 "RF_DAC_CTRL,RF DAC Control Register"
bitfld.long 0x24 9.--11. " VREF_RF_SEL ,RF Voltage Reference Select" "44 mV,66 mV,88 mV,110 mV,132 mV,154 mV,176 mV,198mV"
bitfld.long 0x24 8. " BG_PWD ,Internal reference VREF enable" "Disabled,Enabled"
bitfld.long 0x24 3. " RF_CALSEL ,RF DAC Calibration Select" "Normal,Output"
bitfld.long 0x24 1.--2. " RF_MIDRND ,RF DAC MID randomizer mode" "Bypass,Swap 1,Swap 2,Bit shift"
bitfld.long 0x24 0. " RESET_RF ,Reset RF DAC" "No reset,Reset"
line.long 0x28 "RF_DAC_CAL,RF DAC Calibration Register"
hexmask.long.word 0x28 0.--9. 1. " RFDAC_CAL ,RF DAC D calibration value"
line.long 0x2c "BANDGAP_CTRL,Band Gap Control Register"
hexmask.long.tbyte 0x2c 0.--23. 1. " CTRL_BG ,Band gap control value"
endif
line.long 0x30 "HW_EVT_SEL_GRP1,HW Event Select (Group 1) Register"
bitfld.long 0x30 24.--29. " EVENT4 ,Select 4th trace event from group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 16.--21. " EVENT3 ,Select 3rd trace event from group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 8.--13. " EVENT2 ,Select 2nd trace event from group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 0.--5. " EVENT1 ,Select 1st trace event from group 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x34 "HW_EVT_SEL_GRP2,HW Event Select (Group 2) Register"
bitfld.long 0x34 24.--29. " EVENT4 ,Select 4th trace event from group 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x34 16.--21. " EVENT3 ,Select 3rd trace event from group 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x34 8.--13. " EVENT2 ,Select 2nd trace event from group 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x34 0.--5. " EVENT1 ,Select 1st trace event from group 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "HW_EVT_SEL_GRP3,HW Event Select (Group 3) Register"
bitfld.long 0x38 24.--29. " EVENT4 ,Select 4th trace event from group 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x38 16.--21. " EVENT3 ,Select 3rd trace event from group 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x38 8.--13. " EVENT2 ,Select 2nd trace event from group 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x38 0.--5. " EVENT1 ,Select 1st trace event from group 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x3C "HW_EVT_SEL_GRP4,HW Event Select (Group 4) Register"
bitfld.long 0x3C 24.--29. " EVENT4 ,Select 4th trace event from group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x3C 16.--21. " EVENT3 ,Select 3rd trace event from group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x3C 8.--13. " EVENT2 ,Select 2nd trace event from group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x3C 0.--5. " EVENT1 ,Select 1st trace event from group 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 18.
if ((d.l(ad:0x48140000+0x6f8)&0x4)==0x0)
group.long 0x6f8++0x3
line.long 0x00 "HDMI_OBSCLK_CTRL,HDMI Observe Clock Control Register"
bitfld.long 0x00 9. " SUBLVDS_EN ,Sub-LVDS Mode Enable" "Disabled (1.2V),Enabled (0.9V)"
bitfld.long 0x00 7.--8. " BIAS_TRIM ,Badgap Reference Trimming" "1.2V-3%,1.2V,1.2V+3%,1.2V-1%"
bitfld.long 0x00 6. " BIAS_TRIMEN ,Bandgap Bias eFuse Trim Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " BIAS_EFUSESET ,Bandgap Reference eFuse Set" "Enabled,Disabled"
textline " "
bitfld.long 0x00 4. " BIAS_PWRDN ,Bandgap Reference Powerdown" "Powered up,Powered down"
bitfld.long 0x00 3. " PWRDN ,Buffer Powerdown" "Powered up,Powered down"
bitfld.long 0x00 2. " LPSEL ,Internal termination between PAD and /PAD select" "100 ohms,200 ohms"
bitfld.long 0x00 0.--1. " LOPWR ,Low power operation output current select" "2.5 mA,3.0 mA,3.5 mA,4.0 mA"
else
group.long 0x6f8++0x3
line.long 0x00 "HDMI_OBSCLK_CTRL,HDMI Observe Clock Control Register"
bitfld.long 0x00 9. " SUBLVDS_EN ,Sub-LVDS Mode Enable" "Disabled (1.2V),Enabled (0.9V)"
bitfld.long 0x00 7.--8. " BIAS_TRIM ,Badgap Reference Trimming" "1.2V-3%,1.2V,1.2V+3%,1.2V-1%"
bitfld.long 0x00 6. " BIAS_TRIMEN ,Bandgap Bias eFuse Trim Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " BIAS_EFUSESET ,Bandgap Reference eFuse Set" "Enabled,Disabled"
textline " "
bitfld.long 0x00 4. " BIAS_PWRDN ,Bandgap Reference Powerdown" "Powered up,Powered down"
bitfld.long 0x00 3. " PWRDN ,Buffer Powerdown" "Powered up,Powered down"
bitfld.long 0x00 2. " LPSEL ,Internal termination between PAD and /PAD select" "100 ohms,200 ohms"
bitfld.long 0x00 0.--1. " LOPWR ,Low power operation output current select" "2.0 mA,2.66 mA,3.33 mA,4.0 mA"
endif
group.long 0x6fc++0x3
line.long 0x00 "SERDES_CTRL,Serdes Control Register"
bitfld.long 0x00 1. " SERDES_PWRDN ,Serdes reference clock input buffer powerdown" "Powered up,Powered down"
bitfld.long 0x00 0. " RCD_PWRDN ,Serdes Reference Clock Distribution powerdown" "Powered up,Powered down"
rgroup.long 0x700++0x3
line.long 0x00 "USB_CLK_CTL,USB Clock Control Register"
bitfld.long 0x00 0.--1. " USBSW ,USB Oscillator Frequency Selection" "5-20 MHz,20-30 MHz,30-40 MHz,40-50 MHz"
group.long 0x704++0x3
line.long 0x00 "PLL_OBSCLK_CTRL,PLL Observe Clock Control Register"
bitfld.long 0x00 1. " CML_PWRDN ,PLL Observe clock CML driver powerdown" "Powered up,Powered down"
bitfld.long 0x00 0. " RCD_PWRDN ,PLL Observe clock Reference Clock Distribution powerdown" "Powered up,Powered down"
group.long 0x70c++0x3
line.long 0x00 "DDR_RCD,DDR RCD Register"
bitfld.long 0x00 0. " PWRDN ,Power enable/disable for RCD" "Powered down,Powered up"
tree.end
width 11.
tree.end
tree "DMM (Dynamic Memory Manager)"
base ad:0x4e000000
width 23.
rgroup.long 0x00++0x3
line.long 0x00 "DMM_REVISION,DMM Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatibility level"
hexmask.long.byte 0x00 11.--15. 1. " RRTL ,RTL Version (R)"
bitfld.long 0x00 8.--10. " XMAJOR ,Major Revision (X)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Special DMM version" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision (Y)"
group.long 0x10++0x3
line.long 0x00 "DMM_SYSCONFIG,DMM Clock Management Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No idle,Smart-idle,?..."
group.long 0x1C++0x3
line.long 0x00 "DMM_LISA_LOCK,LISA Configuration Locking Register"
bitfld.long 0x00 0. " LOCK ,DMM lock map" "Unlocked,Locked"
group.long 0x40++0xf
line.long 0x0 "DMM_LISA_MAP[0],DMM LISA MAP 0 Register"
hexmask.long.byte 0x0 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
bitfld.long 0x0 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
bitfld.long 0x0 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
bitfld.long 0x0 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
textline " "
hexmask.long.byte 0x0 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
line.long 0x4 "DMM_LISA_MAP[1],DMM LISA MAP 1 Register"
hexmask.long.byte 0x4 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
bitfld.long 0x4 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
bitfld.long 0x4 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
bitfld.long 0x4 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
textline " "
hexmask.long.byte 0x4 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
line.long 0x8 "DMM_LISA_MAP[2],DMM LISA MAP 2 Register"
hexmask.long.byte 0x8 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
bitfld.long 0x8 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
bitfld.long 0x8 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
bitfld.long 0x8 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
textline " "
hexmask.long.byte 0x8 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
line.long 0xC "DMM_LISA_MAP[3],DMM LISA MAP 3 Register"
hexmask.long.byte 0xC 24.--31. 1. " SYS_ADDR ,DMM system section address MSB"
bitfld.long 0xC 20.--22. " SYS_SIZE ,DMM system section size" "16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB"
bitfld.long 0xC 18.--19. " SDRC_INTL ,EMIF controller interleaving mode" "No interleaving,128-byte,256-byte,512-byte"
bitfld.long 0xC 8.--9. " SDRC_MAP ,EMIF controller mapping" "Un-mapped,SDRC 0 (not interleaved),SDRC 1 (not interleaved),SDRC 0/1 (interleaved)"
textline " "
hexmask.long.byte 0xC 0.--7. 1. " SDRC_ADDR ,EMIF controller address MSB"
width 23.
group.long 0x220++0x7
line.long 0x0 "DMM_TILER_OR[0],DMM TILER Orientation 0 Register"
bitfld.long 0x0 31. " W7 ,Write-enable for OR7 bit-field" "Disabled,Enabled"
bitfld.long 0x0 28.--30. " OR7 ,Orientation for initiator 8.0+7" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 27. " W6 ,Write-enable for OR6 bit-field" "Disabled,Enabled"
bitfld.long 0x0 24.--26. " OR6 ,Orientation for initiator 8.0+6" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 23. " W5 ,Write-enable for OR5 bit-field" "Disabled,Enabled"
bitfld.long 0x0 20.--22. " OR5 ,Orientation for initiator 8.0+5" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 19. " W4 ,Write-enable for OR4 bit-field" "Disabled,Enabled"
bitfld.long 0x0 16.--18. " OR4 ,Orientation for initiator 8.0+4" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x0 15. " W3 ,Write-enable for OR3 bit-field" "Disabled,Enabled"
bitfld.long 0x0 12.--14. " OR3 ,Orientation for initiator 8.0+3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. " W2 ,Write-enable for OR2 bit-field" "Disabled,Enabled"
bitfld.long 0x0 8.--10. " OR2 ,Orientation for initiator 8.0+2" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. " W1 ,Write-enable for OR1 bit-field" "Disabled,Enabled"
bitfld.long 0x0 4.--6. " OR1 ,Orientation for initiator 8.0+1" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. " W0 ,Write-enable for OR0 bit-field" "Disabled,Enabled"
bitfld.long 0x0 0.--2. " OR0 ,Orientation for initiator 8.0" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMM_TILER_OR[1],DMM TILER Orientation 1 Register"
bitfld.long 0x4 31. " W7 ,Write-enable for OR7 bit-field" "Disabled,Enabled"
bitfld.long 0x4 28.--30. " OR7 ,Orientation for initiator 8.1+7" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 27. " W6 ,Write-enable for OR6 bit-field" "Disabled,Enabled"
bitfld.long 0x4 24.--26. " OR6 ,Orientation for initiator 8.1+6" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 23. " W5 ,Write-enable for OR5 bit-field" "Disabled,Enabled"
bitfld.long 0x4 20.--22. " OR5 ,Orientation for initiator 8.1+5" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 19. " W4 ,Write-enable for OR4 bit-field" "Disabled,Enabled"
bitfld.long 0x4 16.--18. " OR4 ,Orientation for initiator 8.1+4" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x4 15. " W3 ,Write-enable for OR3 bit-field" "Disabled,Enabled"
bitfld.long 0x4 12.--14. " OR3 ,Orientation for initiator 8.1+3" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. " W2 ,Write-enable for OR2 bit-field" "Disabled,Enabled"
bitfld.long 0x4 8.--10. " OR2 ,Orientation for initiator 8.1+2" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. " W1 ,Write-enable for OR1 bit-field" "Disabled,Enabled"
bitfld.long 0x4 4.--6. " OR1 ,Orientation for initiator 8.1+1" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. " W0 ,Write-enable for OR0 bit-field" "Disabled,Enabled"
bitfld.long 0x4 0.--2. " OR0 ,Orientation for initiator 8.1" "0,1,2,3,4,5,6,7"
group.long 0x410++0x3
line.long 0x00 "DMM_PAT_CONFIG,DMM PAT Configuration Register"
bitfld.long 0x00 3. " MODE3 ,Mode of refill engine 3" "Normal,Direct LUT"
bitfld.long 0x00 2. " MODE2 ,Mode of refill engine 2" "Normal,Direct LUT"
bitfld.long 0x00 1. " MODE1 ,Mode of refill engine 1" "Normal,Direct LUT"
bitfld.long 0x00 0. " MODE0 ,Mode of refill engine 0" "Normal,Direct LUT"
group.long 0x420++0xf
line.long 0x0 "DMM_PAT_VIEW[0],DMM PAT View 0 Register"
bitfld.long 0x0 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
bitfld.long 0x0 28.--29. " V7 ,PAT view for initiator 8.0+7" "0,1,2,3"
bitfld.long 0x0 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
bitfld.long 0x0 24.--25. " V6 ,PAT view for initiator 8.0+6" "0,1,2,3"
bitfld.long 0x0 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
bitfld.long 0x0 20.--21. " V5 ,PAT view for initiator 8.0+5" "0,1,2,3"
bitfld.long 0x0 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
bitfld.long 0x0 16.--17. " V4 ,PAT view for initiator 8.0+4" "0,1,2,3"
textline " "
bitfld.long 0x0 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
bitfld.long 0x0 12.--13. " V3 ,PAT view for initiator 8.0+3" "0,1,2,3"
bitfld.long 0x0 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
bitfld.long 0x0 8.--9. " V2 ,PAT view for initiator 8.0+2" "0,1,2,3"
bitfld.long 0x0 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
bitfld.long 0x0 4.--5. " V1 ,PAT view for initiator 8.0+1" "0,1,2,3"
bitfld.long 0x0 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
bitfld.long 0x0 0.--1. " V0 ,PAT view for initiator 8.0+0" "0,1,2,3"
line.long 0x4 "DMM_PAT_VIEW[1],DMM PAT View 1 Register"
bitfld.long 0x4 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
bitfld.long 0x4 28.--29. " V7 ,PAT view for initiator 8.1+7" "0,1,2,3"
bitfld.long 0x4 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
bitfld.long 0x4 24.--25. " V6 ,PAT view for initiator 8.1+6" "0,1,2,3"
bitfld.long 0x4 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
bitfld.long 0x4 20.--21. " V5 ,PAT view for initiator 8.1+5" "0,1,2,3"
bitfld.long 0x4 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
bitfld.long 0x4 16.--17. " V4 ,PAT view for initiator 8.1+4" "0,1,2,3"
textline " "
bitfld.long 0x4 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
bitfld.long 0x4 12.--13. " V3 ,PAT view for initiator 8.1+3" "0,1,2,3"
bitfld.long 0x4 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
bitfld.long 0x4 8.--9. " V2 ,PAT view for initiator 8.1+2" "0,1,2,3"
bitfld.long 0x4 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
bitfld.long 0x4 4.--5. " V1 ,PAT view for initiator 8.1+1" "0,1,2,3"
bitfld.long 0x4 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
bitfld.long 0x4 0.--1. " V0 ,PAT view for initiator 8.1+0" "0,1,2,3"
line.long 0x8 "DMM_PAT_VIEW[2],DMM PAT View 2 Register"
bitfld.long 0x8 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
bitfld.long 0x8 28.--29. " V7 ,PAT view for initiator 8.2+7" "0,1,2,3"
bitfld.long 0x8 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
bitfld.long 0x8 24.--25. " V6 ,PAT view for initiator 8.2+6" "0,1,2,3"
bitfld.long 0x8 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
bitfld.long 0x8 20.--21. " V5 ,PAT view for initiator 8.2+5" "0,1,2,3"
bitfld.long 0x8 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
bitfld.long 0x8 16.--17. " V4 ,PAT view for initiator 8.2+4" "0,1,2,3"
textline " "
bitfld.long 0x8 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
bitfld.long 0x8 12.--13. " V3 ,PAT view for initiator 8.2+3" "0,1,2,3"
bitfld.long 0x8 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
bitfld.long 0x8 8.--9. " V2 ,PAT view for initiator 8.2+2" "0,1,2,3"
bitfld.long 0x8 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
bitfld.long 0x8 4.--5. " V1 ,PAT view for initiator 8.2+1" "0,1,2,3"
bitfld.long 0x8 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
bitfld.long 0x8 0.--1. " V0 ,PAT view for initiator 8.2+0" "0,1,2,3"
line.long 0xC "DMM_PAT_VIEW[3],DMM PAT View 3 Register"
bitfld.long 0xC 31. " W7 ,Write-enable for V7 bit-field" "Disabled,Enabled"
bitfld.long 0xC 28.--29. " V7 ,PAT view for initiator 8.3+7" "0,1,2,3"
bitfld.long 0xC 27. " W6 ,Write-enable for V6 bit-field" "Disabled,Enabled"
bitfld.long 0xC 24.--25. " V6 ,PAT view for initiator 8.3+6" "0,1,2,3"
bitfld.long 0xC 23. " W5 ,Write-enable for V5 bit-field" "Disabled,Enabled"
bitfld.long 0xC 20.--21. " V5 ,PAT view for initiator 8.3+5" "0,1,2,3"
bitfld.long 0xC 19. " W4 ,Write-enable for V4 bit-field" "Disabled,Enabled"
bitfld.long 0xC 16.--17. " V4 ,PAT view for initiator 8.3+4" "0,1,2,3"
textline " "
bitfld.long 0xC 15. " W3 ,Write-enable for V3 bit-field" "Disabled,Enabled"
bitfld.long 0xC 12.--13. " V3 ,PAT view for initiator 8.3+3" "0,1,2,3"
bitfld.long 0xC 11. " W2 ,Write-enable for V2 bit-field" "Disabled,Enabled"
bitfld.long 0xC 8.--9. " V2 ,PAT view for initiator 8.3+2" "0,1,2,3"
bitfld.long 0xC 7. " W1 ,Write-enable for V1 bit-field" "Disabled,Enabled"
bitfld.long 0xC 4.--5. " V1 ,PAT view for initiator 8.3+1" "0,1,2,3"
bitfld.long 0xC 3. " W0 ,Write-enable for V0 bit-field" "Disabled,Enabled"
bitfld.long 0xC 0.--1. " V0 ,PAT view for initiator 8.3+0" "0,1,2,3"
width 23.
group.long 0x440++0xf
line.long 0x0 "DMM_PAT_VIEW_MAP[0],DMM View Map 0 Register"
bitfld.long 0x0 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
bitfld.long 0x0 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
bitfld.long 0x0 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
bitfld.long 0x0 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
bitfld.long 0x0 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4 "DMM_PAT_VIEW_MAP[1],DMM View Map 1 Register"
bitfld.long 0x4 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
bitfld.long 0x4 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
bitfld.long 0x4 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x4 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
bitfld.long 0x4 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
bitfld.long 0x4 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8 "DMM_PAT_VIEW_MAP[2],DMM View Map 2 Register"
bitfld.long 0x8 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
bitfld.long 0x8 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
bitfld.long 0x8 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x8 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
bitfld.long 0x8 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x8 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
bitfld.long 0x8 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC "DMM_PAT_VIEW_MAP[3],DMM View Map 3 Register"
bitfld.long 0xC 31. " ACCESS_PAGE ,Kind of access for this page mode container" "Direct,LUT"
bitfld.long 0xC 24.--27. " CONT_PAGE ,Container for page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 23. " ACCESS_32 ,Kind of access for this 32-bit mode container" "Direct,LUT"
bitfld.long 0xC 16.--19. " CONT_32 ,Container for 32-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0xC 15. " ACCESS_16 ,Kind of access for this 16-bit mode container" "Direct,LUT"
bitfld.long 0xC 8.--11. " CONT_16 ,Container for 16-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xC 7. " ACCESS_8 ,Kind of access for this 8-bit mode container" "Direct,LUT"
bitfld.long 0xC 0.--3. " CONT_8 ,Container for 8-bit mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x460++0x3
line.long 0x00 "DMM_PAT_VIEW_MAP_BASE,DMM PAT View Mapping Base Address Register"
bitfld.long 0x00 31. " BASE_ADDR ,MSB of the PAT view mapping base address" "0,1"
width 23.
group.long 0x478++0x3
line.long 0x00 "DMM_PAT_IRQ_EOI,DMM PAT End Of Interrupt (Status/Set) Register"
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
group.long 0x480++0x3
line.long 0x00 "DMM_PAT_IRQSTATUS_RAW,PDMM PAT Raw Interrupt Status/Set Register"
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
group.long 0x490++0x3
line.long 0x00 "DMM_PAT_IRQSTATUS,PDMM PAT Interrupt Status/Clear Register"
eventfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "No interrupt,Interrupt"
eventfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "No interrupt,Interrupt"
eventfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "No interrupt,Interrupt"
eventfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "No interrupt,Interrupt"
eventfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "No interrupt,Interrupt"
group.long 0x4a0++0x3
line.long 0x00 "DMM_PAT_IRQENABLE_SET,PDMM PAT Raw Interrupt Enable Register"
bitfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "Disabled,Enabled"
bitfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "Disabled,Enabled"
bitfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "Disabled,Enabled"
bitfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "Disabled,Enabled"
bitfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "Disabled,Enabled"
bitfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "Disabled,Enabled"
bitfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "Disabled,Enabled"
bitfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "Disabled,Enabled"
bitfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "Disabled,Enabled"
bitfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "Disabled,Enabled"
bitfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "Disabled,Enabled"
bitfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "Disabled,Enabled"
bitfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "Disabled,Enabled"
bitfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "Disabled,Enabled"
bitfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "Disabled,Enabled"
bitfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "Disabled,Enabled"
bitfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "Disabled,Enabled"
bitfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "Disabled,Enabled"
bitfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "Disabled,Enabled"
bitfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "Disabled,Enabled"
bitfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "Disabled,Enabled"
bitfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "Disabled,Enabled"
bitfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "Disabled,Enabled"
bitfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "Disabled,Enabled"
bitfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "Disabled,Enabled"
group.long 0x4b0++0x3
line.long 0x00 "DMM_PAT_IRQENABLE_CLR,PDMM PAT Interrupt Disable Register"
eventfld.long 0x00 31. " ERR_LUT_MISS3 ,Unexpected Access to a yet-to-be-refilled area event in area 3" "Disabled,Enabled"
eventfld.long 0x00 30. " ERR_UPD_DATA3 ,Data register update whilst refilling error event in area 3" "Disabled,Enabled"
eventfld.long 0x00 29. " ERR_UPD_CTRL3 ,Control register update whilst refilling error event in area 3" "Disabled,Enabled"
eventfld.long 0x00 28. " ERR_UPD_AREA3 ,Area register update whilst refilling error event in area 3" "Disabled,Enabled"
textline " "
eventfld.long 0x00 27. " ERR_INV_DATA3 ,Invalid entry-table pointer error event in area 3" "Disabled,Enabled"
eventfld.long 0x00 26. " ERR_INV_DSC3 ,Invalid descriptor pointer error event in area 3" "Disabled,Enabled"
eventfld.long 0x00 25. " FILL_LST3 ,End of refill event for the last descriptor in area 3" "Disabled,Enabled"
eventfld.long 0x00 24. " FILL_DSC3 ,End of refill event for any descriptor in area 3" "Disabled,Enabled"
textline " "
eventfld.long 0x00 23. " ERR_LUT_MISS2 ,Unexpected Access to a yet-to-be-refilled area event in area 2" "Disabled,Enabled"
eventfld.long 0x00 22. " ERR_UPD_DATA2 ,Data register update whilst refilling error event in area 2" "Disabled,Enabled"
eventfld.long 0x00 21. " ERR_UPD_CTRL2 ,Control register update whilst refilling error event in area 2" "Disabled,Enabled"
eventfld.long 0x00 20. " ERR_UPD_AREA2 ,Area register update whilst refilling error event in area 2" "Disabled,Enabled"
textline " "
eventfld.long 0x00 19. " ERR_INV_DATA2 ,Invalid entry-table pointer error event in area 2" "Disabled,Enabled"
eventfld.long 0x00 18. " ERR_INV_DSC2 ,Invalid descriptor pointer error event in area 2" "Disabled,Enabled"
eventfld.long 0x00 17. " FILL_LST2 ,End of refill event for the last descriptor in area 2" "Disabled,Enabled"
eventfld.long 0x00 16. " FILL_DSC2 ,End of refill event for any descriptor in area 2" "Disabled,Enabled"
textline " "
eventfld.long 0x00 15. " ERR_LUT_MISS1 ,Unexpected Access to a yet-to-be-refilled area event in area 1" "Disabled,Enabled"
eventfld.long 0x00 14. " ERR_UPD_DATA1 ,Data register update whilst refilling error event in area 1" "Disabled,Enabled"
eventfld.long 0x00 13. " ERR_UPD_CTRL1 ,Control register update whilst refilling error event in area 1" "Disabled,Enabled"
eventfld.long 0x00 12. " ERR_UPD_AREA1 ,Area register update whilst refilling error event in area 1" "Disabled,Enabled"
textline " "
eventfld.long 0x00 11. " ERR_INV_DATA1 ,Invalid entry-table pointer error event in area 1" "Disabled,Enabled"
eventfld.long 0x00 10. " ERR_INV_DSC1 ,Invalid descriptor pointer error event in area 1" "Disabled,Enabled"
eventfld.long 0x00 9. " FILL_LST1 ,End of refill event for the last descriptor in area 1" "Disabled,Enabled"
eventfld.long 0x00 8. " FILL_DSC1 ,End of refill event for any descriptor in area 1" "Disabled,Enabled"
textline " "
eventfld.long 0x00 7. " ERR_LUT_MISS0 ,Unexpected Access to a yet-to-be-refilled area event in area 0" "Disabled,Enabled"
eventfld.long 0x00 6. " ERR_UPD_DATA0 ,Data register update whilst refilling error event in area 0" "Disabled,Enabled"
eventfld.long 0x00 5. " ERR_UPD_CTRL0 ,Control register update whilst refilling error event in area 0" "Disabled,Enabled"
eventfld.long 0x00 4. " ERR_UPD_AREA0 ,Area register update whilst refilling error event in area 0" "Disabled,Enabled"
textline " "
eventfld.long 0x00 3. " ERR_INV_DATA0 ,Invalid entry-table pointer error event in area 0" "Disabled,Enabled"
eventfld.long 0x00 2. " ERR_INV_DSC0 ,Invalid descriptor pointer error event in area 0" "Disabled,Enabled"
eventfld.long 0x00 1. " FILL_LST0 ,End of refill event for the last descriptor in area 0" "Disabled,Enabled"
eventfld.long 0x00 0. " FILL_DSC0 ,End of refill event for any descriptor in area 0" "Disabled,Enabled"
width 23.
rgroup.long 0x4c0++0xf
line.long 0x0 "DMM_PAT_STATUS[0],DMM PAT Status 0 Register"
bitfld.long 0x0 10.--15. " ERROR ,Error occurred in engine 0" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
textline " "
hexmask.long.word 0x0 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 0"
bitfld.long 0x0 7. " BYPASSED ,Engine 0 bypass" "Not bypassed,Bypassed"
bitfld.long 0x0 3. " DONE ,Area reloading finished for engine 0" "Not finished,Finished"
textline " "
bitfld.long 0x0 2. " RUN ,Area currently reloading for engine 0" "Not reloading,Reloading"
bitfld.long 0x0 1. " VALID ,Valid area description for engine 0" "Invalid,Valid"
bitfld.long 0x0 0. " READY ,Area registers ready for engine 0" "Not ready,Ready"
line.long 0x4 "DMM_PAT_STATUS[1],DMM PAT Status 1 Register"
bitfld.long 0x4 10.--15. " ERROR ,Error occurred in engine 1" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
textline " "
hexmask.long.word 0x4 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 1"
bitfld.long 0x4 7. " BYPASSED ,Engine 1 bypass" "Not bypassed,Bypassed"
bitfld.long 0x4 3. " DONE ,Area reloading finished for engine 1" "Not finished,Finished"
textline " "
bitfld.long 0x4 2. " RUN ,Area currently reloading for engine 1" "Not reloading,Reloading"
bitfld.long 0x4 1. " VALID ,Valid area description for engine 1" "Invalid,Valid"
bitfld.long 0x4 0. " READY ,Area registers ready for engine 1" "Not ready,Ready"
line.long 0x8 "DMM_PAT_STATUS[2],DMM PAT Status 2 Register"
bitfld.long 0x8 10.--15. " ERROR ,Error occurred in engine 2" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
textline " "
hexmask.long.word 0x8 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 2"
bitfld.long 0x8 7. " BYPASSED ,Engine 2 bypass" "Not bypassed,Bypassed"
bitfld.long 0x8 3. " DONE ,Area reloading finished for engine 2" "Not finished,Finished"
textline " "
bitfld.long 0x8 2. " RUN ,Area currently reloading for engine 2" "Not reloading,Reloading"
bitfld.long 0x8 1. " VALID ,Valid area description for engine 2" "Invalid,Valid"
bitfld.long 0x8 0. " READY ,Area registers ready for engine 2" "Not ready,Ready"
line.long 0xC "DMM_PAT_STATUS[3],DMM PAT Status 3 Register"
bitfld.long 0xC 10.--15. " ERROR ,Error occurred in engine 3" "No error,Invalid descriptor,Invalid data pointer,Reserved,Unexpected area register update,Reserved,Reserved,Reserved,Unexpected control register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected data register update,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Unexpected access to a yet-to-be-refilled location,?..."
textline " "
hexmask.long.word 0xC 16.--24. 1. " CNT ,Counter of remaining lines to re-load for engine 3"
bitfld.long 0xC 7. " BYPASSED ,Engine 3 bypass" "Not bypassed,Bypassed"
bitfld.long 0xC 3. " DONE ,Area reloading finished for engine 3" "Not finished,Finished"
textline " "
bitfld.long 0xC 2. " RUN ,Area currently reloading for engine 3" "Not reloading,Reloading"
bitfld.long 0xC 1. " VALID ,Valid area description for engine 3" "Invalid,Valid"
bitfld.long 0xC 0. " READY ,Area registers ready for engine 3" "Not ready,Ready"
width 23.
group.long 0x500++0x3f
line.long 0x0 "DMM_PAT_DESCR[0],DMM PAT Descriptor 0 Register"
hexmask.long 0x0 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
line.long (0x0+0x4) "DMM_PAT_AREA[0],DMM PAT Area Geometry 0 Register"
hexmask.long.byte (0x0+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x0+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x0+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
hexmask.long.byte (0x0+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
line.long (0x0+0x8) "DMM_PAT_CTRL[0],DMM PAT Control 0 Register"
bitfld.long (0x0+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long (0x0+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
bitfld.long (0x0+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
textline " "
bitfld.long (0x0+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
bitfld.long (0x0+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
line.long (0x0+0xc) "DMM_PAT_DATA[0],DMM PAT Area Entry Data 0 Register"
hexmask.long (0x0+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
line.long 0x10 "DMM_PAT_DESCR[1],DMM PAT Descriptor 1 Register"
hexmask.long 0x10 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
line.long (0x10+0x4) "DMM_PAT_AREA[1],DMM PAT Area Geometry 1 Register"
hexmask.long.byte (0x10+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x10+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x10+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
hexmask.long.byte (0x10+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
line.long (0x10+0x8) "DMM_PAT_CTRL[1],DMM PAT Control 1 Register"
bitfld.long (0x10+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long (0x10+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
bitfld.long (0x10+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
textline " "
bitfld.long (0x10+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
bitfld.long (0x10+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
line.long (0x10+0xc) "DMM_PAT_DATA[1],DMM PAT Area Entry Data 1 Register"
hexmask.long (0x10+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
line.long 0x20 "DMM_PAT_DESCR[2],DMM PAT Descriptor 2 Register"
hexmask.long 0x20 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
line.long (0x20+0x4) "DMM_PAT_AREA[2],DMM PAT Area Geometry 2 Register"
hexmask.long.byte (0x20+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x20+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x20+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
hexmask.long.byte (0x20+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
line.long (0x20+0x8) "DMM_PAT_CTRL[2],DMM PAT Control 2 Register"
bitfld.long (0x20+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long (0x20+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
bitfld.long (0x20+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
textline " "
bitfld.long (0x20+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
bitfld.long (0x20+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
line.long (0x20+0xc) "DMM_PAT_DATA[2],DMM PAT Area Entry Data 2 Register"
hexmask.long (0x20+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
line.long 0x30 "DMM_PAT_DESCR[3],DMM PAT Descriptor 3 Register"
hexmask.long 0x30 4.--31. 0x10 " ADDR ,Physical address of the next table refill descriptor"
line.long (0x30+0x4) "DMM_PAT_AREA[3],DMM PAT Area Geometry 3 Register"
hexmask.long.byte (0x30+0x4) 24.--30. 1. " Y1 ,Y-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x30+0x4) 16.--23. 1. " X1 ,X-coordinate of the bottom right corner of the PAT area"
hexmask.long.byte (0x30+0x4) 8.--14. 1. " Y0 ,Y-coordinate of the top left corner of the PAT area "
hexmask.long.byte (0x30+0x4) 0.--7. 1. " X0 ,X-coordinate of the top left corner of the PAT area"
line.long (0x30+0x8) "DMM_PAT_CTRL[3],DMM PAT Control 3 Register"
bitfld.long (0x30+0x8) 28.--31. " INITIATOR ,DMM PAT initiator for synchronisation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long (0x30+0x8) 16. " SYNC ,DMM PAT table reload synchronisation" "Not synchronised,Synchronised"
bitfld.long (0x30+0x8) 8.--9. " LUT_ID ,PAT LUT index" "0,1,2,3"
textline " "
bitfld.long (0x30+0x8) 4.--6. " DIRECTION ,Direction of this PAT table refill" "0,1,2,3,4,5,6,7"
bitfld.long (0x30+0x8) 0. " START ,Start PAT table refill" "Not started,Started"
line.long (0x30+0xc) "DMM_PAT_DATA[3],DMM PAT Area Entry Data 3 Register"
hexmask.long (0x30+0xc) 4.--31. 0x10 " ADDR ,Physical address of the current table refill entry data or single actual entry data when in manual mode"
width 23.
group.long 0x620++0x7
line.long 0x0 "DMM_PEG_PRIO[0],DMM PEG Priority 0 Register"
bitfld.long 0x0 31. " W7 ,Write-enable for P7 bit-field" "Disabled,Enabled"
bitfld.long 0x0 28.--30. " P7 ,Priority for initiator 8.0+7" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 27. " W6 ,Write-enable for P6 bit-field" "Disabled,Enabled"
bitfld.long 0x0 24.--26. " P6 ,Priority for initiator 8.0+6" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 23. " W5 ,Write-enable for P5 bit-field" "Disabled,Enabled"
bitfld.long 0x0 20.--22. " P5 ,Priority for initiator 8.0+5" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 19. " W4 ,Write-enable for P4 bit-field" "Disabled,Enabled"
bitfld.long 0x0 16.--18. " P4 ,Priority for initiator 8.0+4" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x0 15. " W3 ,Write-enable for P3 bit-field" "Disabled,Enabled"
bitfld.long 0x0 12.--14. " P3 ,Priority for initiator 8.0+3" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 11. " W2 ,Write-enable for P2 bit-field" "Disabled,Enabled"
bitfld.long 0x0 8.--10. " P2 ,Priority for initiator 8.0+2" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 7. " W1 ,Write-enable for P1 bit-field" "Disabled,Enabled"
bitfld.long 0x0 4.--6. " P1 ,Priority for initiator 8.0+1" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 3. " W0 ,Write-enable for P0 bit-field" "Disabled,Enabled"
bitfld.long 0x0 0.--2. " P0 ,Priority for initiator 8.0" "0,1,2,3,4,5,6,7"
line.long 0x4 "DMM_PEG_PRIO[1],DMM PEG Priority 1 Register"
bitfld.long 0x4 31. " W7 ,Write-enable for P7 bit-field" "Disabled,Enabled"
bitfld.long 0x4 28.--30. " P7 ,Priority for initiator 8.1+7" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 27. " W6 ,Write-enable for P6 bit-field" "Disabled,Enabled"
bitfld.long 0x4 24.--26. " P6 ,Priority for initiator 8.1+6" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 23. " W5 ,Write-enable for P5 bit-field" "Disabled,Enabled"
bitfld.long 0x4 20.--22. " P5 ,Priority for initiator 8.1+5" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 19. " W4 ,Write-enable for P4 bit-field" "Disabled,Enabled"
bitfld.long 0x4 16.--18. " P4 ,Priority for initiator 8.1+4" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x4 15. " W3 ,Write-enable for P3 bit-field" "Disabled,Enabled"
bitfld.long 0x4 12.--14. " P3 ,Priority for initiator 8.1+3" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 11. " W2 ,Write-enable for P2 bit-field" "Disabled,Enabled"
bitfld.long 0x4 8.--10. " P2 ,Priority for initiator 8.1+2" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 7. " W1 ,Write-enable for P1 bit-field" "Disabled,Enabled"
bitfld.long 0x4 4.--6. " P1 ,Priority for initiator 8.1+1" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 3. " W0 ,Write-enable for P0 bit-field" "Disabled,Enabled"
bitfld.long 0x4 0.--2. " P0 ,Priority for initiator 8.1" "0,1,2,3,4,5,6,7"
group.long 0x640++0x3
line.long 0x00 "DMM_PEG_PRIO_PAT,DMM PEG Priority register for PAT"
bitfld.long 0x00 3. " W_PAT ,Write-enable for P_PAT bit-field" "Disabled,Enabled"
bitfld.long 0x00 0.--2. " P_PAT ,Priority for PAT engine" "0,1,2,3,4,5,6,7"
width 11.
tree.end
tree.open "EDMA3 (Enhanced Direct Memory Access)"
tree "EDMA3CC (EDMA3 Channel Controller Control Registers)"
base ad:0x49000000
width 10.
tree "Global Registers"
rgroup.long 0x00++0x03
line.long 0x00 "PID,Peripheral ID Register"
rgroup.long 0x04++0x03
line.long 0x00 "CCCFG,EDMA3CC Configuration Register"
bitfld.long 0x00 25. " MP_EXIST ,Memory protection existence" "Reserved,Included"
bitfld.long 0x00 24. " CHMAP_EXIST ,Channel mapping existence" "Reserved,Included"
bitfld.long 0x00 20.--21. " NUM_REGN ,Number of MP and shadow regions" "Reserved,Reserved,Reserved,8 regions"
textline " "
bitfld.long 0x00 16.--18. " NUM_EVQUE ,Number of queues/number of TCs" "Reserved,Reserved,Reserved,4 EDMA3TCs/Event Queues,?..."
textline " "
bitfld.long 0x00 12.--14. " NUM_PAENTRY ,Number of PaRAM sets" "Reserved,Reserved,Reserved,Reserved,Reserved,512 PaRAM sets,?..."
bitfld.long 0x00 8.--10. " NUM_INTCH ,Number of interrupt channels" "Reserved,Reserved,Reserved,Reserved,64 interrupt Ch,?..."
bitfld.long 0x00 4.--6. " NUM_QDMACH ,Number of QDMA channels" "Reserved,Reserved,Reserved,Reserved,8 QDMA Ch,?..."
textline " "
bitfld.long 0x00 0.--2. " NUM_DMACH ,Number of DMA channels" "Reserved,Reserved,Reserved,Reserved,Reserved,64 DMA Ch,?..."
group.long 0x100++0x1FF
line.long 0x0 "DCHMAP0,DMA Channel Map 0 Registers"
hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 0"
line.long 0x4 "DCHMAP1,DMA Channel Map 1 Registers"
hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 1"
line.long 0x8 "DCHMAP2,DMA Channel Map 2 Registers"
hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 2"
line.long 0xC "DCHMAP3,DMA Channel Map 3 Registers"
hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 3"
line.long 0x10 "DCHMAP4,DMA Channel Map 4 Registers"
hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 4"
line.long 0x14 "DCHMAP5,DMA Channel Map 5 Registers"
hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 5"
line.long 0x18 "DCHMAP6,DMA Channel Map 6 Registers"
hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 6"
line.long 0x1C "DCHMAP7,DMA Channel Map 7 Registers"
hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 7"
line.long 0x20 "DCHMAP8,DMA Channel Map 8 Registers"
hexmask.long.word 0x20 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 8"
line.long 0x24 "DCHMAP9,DMA Channel Map 9 Registers"
hexmask.long.word 0x24 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 9"
line.long 0x28 "DCHMAP10,DMA Channel Map 10 Registers"
hexmask.long.word 0x28 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 10"
line.long 0x2C "DCHMAP11,DMA Channel Map 11 Registers"
hexmask.long.word 0x2C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 11"
line.long 0x30 "DCHMAP12,DMA Channel Map 12 Registers"
hexmask.long.word 0x30 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 12"
line.long 0x34 "DCHMAP13,DMA Channel Map 13 Registers"
hexmask.long.word 0x34 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 13"
line.long 0x38 "DCHMAP14,DMA Channel Map 14 Registers"
hexmask.long.word 0x38 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 14"
line.long 0x3C "DCHMAP15,DMA Channel Map 15 Registers"
hexmask.long.word 0x3C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 15"
line.long 0x40 "DCHMAP16,DMA Channel Map 16 Registers"
hexmask.long.word 0x40 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 16"
line.long 0x44 "DCHMAP17,DMA Channel Map 17 Registers"
hexmask.long.word 0x44 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 17"
line.long 0x48 "DCHMAP18,DMA Channel Map 18 Registers"
hexmask.long.word 0x48 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 18"
line.long 0x4C "DCHMAP19,DMA Channel Map 19 Registers"
hexmask.long.word 0x4C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 19"
line.long 0x50 "DCHMAP20,DMA Channel Map 20 Registers"
hexmask.long.word 0x50 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 20"
line.long 0x54 "DCHMAP21,DMA Channel Map 21 Registers"
hexmask.long.word 0x54 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 21"
line.long 0x58 "DCHMAP22,DMA Channel Map 22 Registers"
hexmask.long.word 0x58 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 22"
line.long 0x5C "DCHMAP23,DMA Channel Map 23 Registers"
hexmask.long.word 0x5C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 23"
line.long 0x60 "DCHMAP24,DMA Channel Map 24 Registers"
hexmask.long.word 0x60 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 24"
line.long 0x64 "DCHMAP25,DMA Channel Map 25 Registers"
hexmask.long.word 0x64 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 25"
line.long 0x68 "DCHMAP26,DMA Channel Map 26 Registers"
hexmask.long.word 0x68 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 26"
line.long 0x6C "DCHMAP27,DMA Channel Map 27 Registers"
hexmask.long.word 0x6C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 27"
line.long 0x70 "DCHMAP28,DMA Channel Map 28 Registers"
hexmask.long.word 0x70 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 28"
line.long 0x74 "DCHMAP29,DMA Channel Map 29 Registers"
hexmask.long.word 0x74 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 29"
line.long 0x78 "DCHMAP30,DMA Channel Map 30 Registers"
hexmask.long.word 0x78 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 30"
line.long 0x7C "DCHMAP31,DMA Channel Map 31 Registers"
hexmask.long.word 0x7C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 31"
line.long 0x80 "DCHMAP32,DMA Channel Map 32 Registers"
hexmask.long.word 0x80 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 32"
line.long 0x84 "DCHMAP33,DMA Channel Map 33 Registers"
hexmask.long.word 0x84 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 33"
line.long 0x88 "DCHMAP34,DMA Channel Map 34 Registers"
hexmask.long.word 0x88 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 34"
line.long 0x8C "DCHMAP35,DMA Channel Map 35 Registers"
hexmask.long.word 0x8C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 35"
line.long 0x90 "DCHMAP36,DMA Channel Map 36 Registers"
hexmask.long.word 0x90 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 36"
line.long 0x94 "DCHMAP37,DMA Channel Map 37 Registers"
hexmask.long.word 0x94 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 37"
line.long 0x98 "DCHMAP38,DMA Channel Map 38 Registers"
hexmask.long.word 0x98 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 38"
line.long 0x9C "DCHMAP39,DMA Channel Map 39 Registers"
hexmask.long.word 0x9C 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 39"
line.long 0xA0 "DCHMAP40,DMA Channel Map 40 Registers"
hexmask.long.word 0xA0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 40"
line.long 0xA4 "DCHMAP41,DMA Channel Map 41 Registers"
hexmask.long.word 0xA4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 41"
line.long 0xA8 "DCHMAP42,DMA Channel Map 42 Registers"
hexmask.long.word 0xA8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 42"
line.long 0xAC "DCHMAP43,DMA Channel Map 43 Registers"
hexmask.long.word 0xAC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 43"
line.long 0xB0 "DCHMAP44,DMA Channel Map 44 Registers"
hexmask.long.word 0xB0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 44"
line.long 0xB4 "DCHMAP45,DMA Channel Map 45 Registers"
hexmask.long.word 0xB4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 45"
line.long 0xB8 "DCHMAP46,DMA Channel Map 46 Registers"
hexmask.long.word 0xB8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 46"
line.long 0xBC "DCHMAP47,DMA Channel Map 47 Registers"
hexmask.long.word 0xBC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 47"
line.long 0xC0 "DCHMAP48,DMA Channel Map 48 Registers"
hexmask.long.word 0xC0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 48"
line.long 0xC4 "DCHMAP49,DMA Channel Map 49 Registers"
hexmask.long.word 0xC4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 49"
line.long 0xC8 "DCHMAP50,DMA Channel Map 50 Registers"
hexmask.long.word 0xC8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 50"
line.long 0xCC "DCHMAP51,DMA Channel Map 51 Registers"
hexmask.long.word 0xCC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 51"
line.long 0xD0 "DCHMAP52,DMA Channel Map 52 Registers"
hexmask.long.word 0xD0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 52"
line.long 0xD4 "DCHMAP53,DMA Channel Map 53 Registers"
hexmask.long.word 0xD4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 53"
line.long 0xD8 "DCHMAP54,DMA Channel Map 54 Registers"
hexmask.long.word 0xD8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 54"
line.long 0xDC "DCHMAP55,DMA Channel Map 55 Registers"
hexmask.long.word 0xDC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 55"
line.long 0xE0 "DCHMAP56,DMA Channel Map 56 Registers"
hexmask.long.word 0xE0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 56"
line.long 0xE4 "DCHMAP57,DMA Channel Map 57 Registers"
hexmask.long.word 0xE4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 57"
line.long 0xE8 "DCHMAP58,DMA Channel Map 58 Registers"
hexmask.long.word 0xE8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 58"
line.long 0xEC "DCHMAP59,DMA Channel Map 59 Registers"
hexmask.long.word 0xEC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 59"
line.long 0xF0 "DCHMAP60,DMA Channel Map 60 Registers"
hexmask.long.word 0xF0 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 60"
line.long 0xF4 "DCHMAP61,DMA Channel Map 61 Registers"
hexmask.long.word 0xF4 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 61"
line.long 0xF8 "DCHMAP62,DMA Channel Map 62 Registers"
hexmask.long.word 0xF8 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 62"
line.long 0xFC "DCHMAP63,DMA Channel Map 63 Registers"
hexmask.long.word 0xFC 5.--13. 1. " PAENTRY ,Points to the PaRAM set number for DMA channel 63"
group.long 0x200++0x1F
line.long 0x0 "QCHMAP0,QDMA Channel Map 0 Registers"
hexmask.long.word 0x0 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 0"
bitfld.long 0x0 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x4 "QCHMAP1,QDMA Channel Map 1 Registers"
hexmask.long.word 0x4 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 1"
bitfld.long 0x4 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x8 "QCHMAP2,QDMA Channel Map 2 Registers"
hexmask.long.word 0x8 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 2"
bitfld.long 0x8 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0xC "QCHMAP3,QDMA Channel Map 3 Registers"
hexmask.long.word 0xC 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 3"
bitfld.long 0xC 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x10 "QCHMAP4,QDMA Channel Map 4 Registers"
hexmask.long.word 0x10 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 4"
bitfld.long 0x10 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x14 "QCHMAP5,QDMA Channel Map 5 Registers"
hexmask.long.word 0x14 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 5"
bitfld.long 0x14 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x18 "QCHMAP6,QDMA Channel Map 6 Registers"
hexmask.long.word 0x18 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 6"
bitfld.long 0x18 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
line.long 0x1C "QCHMAP7,QDMA Channel Map 7 Registers"
hexmask.long.word 0x1C 5.--13. 1. " PAENTRY ,PAENTRY points to the PaRAM set number for QDMA channel 7"
bitfld.long 0x1C 2.--4. " TRWORD ,Points to the specific trigger word of the PaRAM set defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUM0,DMA Queue Number Register 0"
bitfld.long 0x00 12.--14. " E3 ,SDRXEVT1 - SD/SDIO1 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 8.--10. " E2 ,SDTXEVT1 - SD/SDIO1 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 4.--6. " E1 ,VCPXEVT0 - VCP Transmit Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 0.--2. " E0 ,VCPREVT0 - VCP Receive Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
group.long 0x244++0x0b
line.long 0x00 "DMAQNUM1,DMA Queue Number Register 1"
bitfld.long 0x00 28.--30. " E15 ,BREVT - McBSP Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 24.--26. " E14 ,BXEVT - McBSP Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 20.--22. " E13 ,AREVT2 - McASP2 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 16.--18. " E12 ,AXEVT2 - McASP2 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x00 12.--14. " E11 ,AREVT1 - McASP1 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 8.--10. " E10 ,AXEVT1 - McASP1 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 4.--6. " E9 ,AREVT0 - McASP0 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 0.--2. " E8 ,AXEVT0 - McASP0 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
line.long 0x04 "DMAQNUM2,DMA Queue Number Register 2"
bitfld.long 0x04 28.--30. " E23 ,SPI0REVT3 - SPI0 Receive Event 3 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 24.--26. " E22 ,SPI0XEVT3 - SPI0 Transmit Event 3 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 20.--22. " E21 ,SPI0REVT2 - SPI0 Receive Event 2 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 16.--18. " E20 ,SPI0XEVT2 - SPI0 Transmit Event 2 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x04 12.--14. " E19 ,SPI0REVT1 - SPI0 Receive Event 1 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 8.--10. " E18 ,SPI0XEVT1 - SPI0 Transmit Event 1 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 4.--6. " E17 ,SPI0REVT0 - SPI0 Receive Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 0.--2. " E16 ,SPI0XEVT0 - SPI0 Transmit Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
line.long 0x08 "DMAQNUM3,DMA Queue Number Register 3"
bitfld.long 0x08 28.--30. " E31 ,URXEVT2 - UART2 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 24.--26. " E30 ,UTXEVT2 - UART2 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 20.--22. " E29 ,URXEVT1 - UART1 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 16.--18. " E28 ,UTXEVT1 - UART1 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x08 12.--14. " E27 ,URXEVT0 - UART0 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 8.--10. " E26 ,UTXEVT0 - UART0 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 4.--6. " E25 ,SDRXEVT0 - SD/SDIO0 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x08 0.--2. " E24 ,SDTXEVT0 - SD/SDIO0 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
group.long 0x250++0x07
line.long 0x00 "DMAQNUM4,DMA Queue Number Register 4"
bitfld.long 0x00 28.--30. " E39 ,ISS_DMA_REQ4 - ISS Event 4 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 24.--26. " E38 ,ISS_DMA_REQ3 - ISS Event 3 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 20.--22. " E37 ,ISS_DMA_REQ2 - ISS Event 2 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 16.--18. " E36 ,ISS_DMA_REQ1 - ISS Event 1 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
line.long 0x04 "DMAQNUM5,DMA Queue Number Register 5"
bitfld.long 0x04 28.--30. " E47 ,CAN_IF3DMA - DCAN0 IF3 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 20.--22. " E45 ,SPI1REVT1 - SPI1 Receive Event 1 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 16.--18. " E44 ,SPI1XEVT1 - SPI1 Transmit Event 1 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 12.--14. " E43 ,SPI1REVT0 - SPI1 Receive Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x04 8.--10. " E42 ,SPI1XEVT0 - SPI1 Transmit Event 0 - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 4.--6. " E41 ,CAN_IF2DMA - DCAN0 IF2 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 0.--2. " E40 ,CAN_IF1DMA - DCAN0 IF1 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
endif
group.long 0x258++0x07
line.long 0x00 "DMAQNUM6,DMA Queue Number Register 6"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 28.--30. " E55 ,PCIE_RX - PCIe Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 24.--26. " E54 ,PCIE_TX - PCIe Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
endif
bitfld.long 0x00 20.--22. " E53 ,HDMIEVT - HDMI Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 16.--18. " E52 ,GPMCEVT - GPMC Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 12.--14. " E51 ,TINT7 - Timer7 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 8.--10. " E50 ,TINT6 - Timer6 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x00 4.--6. " E49 ,TINT5 - Timer5 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x00 0.--2. " E48 ,TINT4 - Timer4 Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
line.long 0x04 "DMAQNUM7,DMA Queue Number Register 7"
bitfld.long 0x04 28.--30. " E63 ,AREVT4 - McASP4 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 24.--26. " E62 ,AXEVT4 - McASP4 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 20.--22. " E61 ,I2CRXEVT1 - I2C1 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 16.--18. " E60 ,I2CTXEVT1 - I2C1 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
textline " "
bitfld.long 0x04 12.--14. " E59 ,I2CRXEVT0 - I2C0 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 8.--10. " E58 ,I2CTXEVT0 - I2C0 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 4.--6. " E57 ,AREVT3 - McASP3 Receive Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
bitfld.long 0x04 0.--2. " E56 ,AXEVT3 - McASP3 Transmit Event - DMA Queue Number" "Q0,Q1,Q2,Q3,?..."
endif
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Channel Queue Number Register"
bitfld.long 0x00 28.--30. " E7[28:30] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
bitfld.long 0x00 24.--26. " E6[24:26] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
textline " "
bitfld.long 0x00 20.--22. " E5[20:22] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
bitfld.long 0x00 16.--18. " E4[16:18] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
textline " "
bitfld.long 0x00 12.--14. " E3[12:14] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
bitfld.long 0x00 8.--10. " E2[8:10] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
textline " "
bitfld.long 0x00 4.--6. " E1[4:6] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
bitfld.long 0x00 0.--2. " E0[0:2] ,QDMA queue number" "Q0,Q1,Q2,Q3,Q4,?..."
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x284++0x03
line.long 0x00 "QUEPRI,Queue Priority Register"
bitfld.long 0x00 12.--14. " PRIQ3 ,Priority level for queue 3" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 8.--10. " PRIQ2 ,Priority level for queue 2" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 4.--6. " PRIQ1 ,Priority level for queue 1" "Highest,1,2,3,4,5,6,Lowest"
textline " "
bitfld.long 0x00 0.--2. " PRIQ0 ,Priority level for queue 0" "Highest,1,2,3,4,5,6,Lowest"
endif
tree.end
tree "Error Registers"
rgroup.long 0x300++0x07
line.long 0x00 "EMR,Event Missed Register"
bitfld.long 0x00 31. " E31 ,Channel 31 URXEVT2 event missed" "Not occurred,Occurred"
bitfld.long 0x00 30. " E30 ,Channel 30 UTXEVT2 event missed" "Not occurred,Occurred"
bitfld.long 0x00 29. " E29 ,Channel 29 URXEVT1 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 28. " E28 ,Channel 28 UTXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 27. " E27 ,Channel 27 URXEVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x00 26. " E26 ,Channel 26 UTXEVT0 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 25. " E25 ,Channel 25 SDRXEVT event missed" "Not occurred,Occurred"
bitfld.long 0x00 24. " E24 ,Channel 24 SDTXEVT event missed" "Not occurred,Occurred"
bitfld.long 0x00 23. " E23 ,Channel 23 SPIREVT3 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 22. " E22 ,Channel 22 SPIXEVT3 event missed" "Not occurred,Occurred"
bitfld.long 0x00 21. " E21 ,Channel 21 SPIREVT2 event missed" "Not occurred,Occurred"
bitfld.long 0x00 20. " E20 ,Channel 20 SPIXEVT2 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 19. " E19 ,Channel 19 SPIREVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 18. " E18 ,Channel 18 SPIXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 17. " E17 ,Channel 17 SPIREVT0 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 16. " E16 ,Channel 16 SPIXEVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x00 15. " E15 ,Channel 15 BREVT event missed" "Not occurred,Occurred"
bitfld.long 0x00 14. " E14 ,Channel 14 BXEVT event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 13. " E13 ,Channel 13 AREVT2 event missed" "Not occurred,Occurred"
bitfld.long 0x00 12. " E12 ,Channel 12 AXEVT2 event missed" "Not occurred,Occurred"
bitfld.long 0x00 11. " E11 ,Channel 11 AREVT1 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 10. " E10 ,Channel 10 AXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 9. " E9 ,Channel 9 AREVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x00 8. " E8 ,Channel 8 AXEVT0 event missed" "Not occurred,Occurred"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Channel 3 VCPXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 2. " E2 ,Channel 2 VCPREVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 1. " E1 ,Channel 1 VCPXEVT0 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 0. " E0 ,Channel 0 VCPREVT0 event missed" "Not occurred,Occurred"
endif
line.long 0x04 "EMRH,Event Missed Register High"
bitfld.long 0x04 29. " E61 ,Channel 61 I2CRXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x04 28. " E60 ,Channel 60 I2CTXEVT1 event missed" "Not occurred,Occurred"
bitfld.long 0x04 27. " E59 ,Channel 59 I2CRXEVT0 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 26. " E58 ,Channel 58 I2CTXEVT0 event missed" "Not occurred,Occurred"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Channel 47 AREVT3 event missed" "Not occurred,Occurred"
bitfld.long 0x04 24. " E56 ,Channel 45 AXEVT3 event missed" "Not occurred,Occurred"
bitfld.long 0x04 23. " E55 ,Channel 44 PCIE_RX event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 22. " E54 ,Channel 53 PCIE_TX event missed" "Not occurred,Occurred"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Channel 53 HDMIEVT event missed" "Not occurred,Occurred"
bitfld.long 0x04 20. " E52 ,Channel 52 GPMCEVT event missed" "Not occurred,Occurred"
bitfld.long 0x04 19. " E51 ,Channel 51 TINT7 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 18. " E50 ,Channel 50 TINT6 event missed" "Not occurred,Occurred"
bitfld.long 0x04 17. " E49 ,Channel 49 TINT5 event missed" "Not occurred,Occurred"
bitfld.long 0x04 16. " E48 ,Channel 48 TINT4 event missed" "Not occurred,Occurred"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Channel 47 CAN_IF3DMA event missed" "Not occurred,Occurred"
bitfld.long 0x04 13. " E45 ,Channel 45 SPI1REVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x04 12. " E44 ,Channel 44 SPI1XEVT1 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 11. " E43 ,Channel 43 SPI1REVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x04 10. " E42 ,Channel 42 SPI1XEVT0 event missed" "Not occurred,Occurred"
bitfld.long 0x04 9. " E41 ,Channel 41 CAN_IF2DMA event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 8. " E40 ,Channel 40 CAN_IF1DMA event missed" "Not occurred,Occurred"
bitfld.long 0x04 7. " E39 ,Channel 39 ISS_DMA_REQ4 event missed" "Not occurred,Occurred"
bitfld.long 0x04 6. " E38 ,Channel 38 ISS_DMA_REQ3 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 5. " E37 ,Channel 37 ISS_DMA_REQ2 event missed" "Not occurred,Occurred"
bitfld.long 0x04 4. " E36 ,Channel 36 ISS_DMA_REQ1 event missed" "Not occurred,Occurred"
endif
wgroup.long 0x308++0x07
line.long 0x00 "EMCR,Event Missed Clear Registers"
bitfld.long 0x00 31. " E31 ,Channel 31 URXEVT2 event clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Channel 30 UTXEVT2 event clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Channel 29 URXEVT1 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Channel 28 UTXEVT1 event clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Channel 27 URXEVT0 event clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Channel 26 UTXEVT0 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Channel 25 SDRXEVT event clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Channel 24 SDTXEVT event clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Channel 23 SPIREVT4 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Channel 22 SPIXEVT3 event clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Channel 21 SPIREVT2 event clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Channel 20 SPIXEVT2 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Channel 19 SPIREVT1 event clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Channel 18 SPIXEVT1 event clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Channel 17 SPIREVT0 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Channel 16 SPIXEVT0 event clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Channel 15 BREVT event clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Channel 14 BXEVT event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Channel 13 AREVT2 event clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Channel 12 AXEVT2 event clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Channel 11 AREVT1 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Channel 10 AXEVT1 event clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Channel 9 AREVT0 event clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Channel 8 AXEVT0 event clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Channel 3 VCPXEVT1 event clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Channel 2 VCPREVT1 event clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Channel 1 VCPXEVT0 event clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Channel 0 VCPREVT0 event clear" "No effect,Clear"
endif
line.long 0x04 "EMCRH,Event Missed Clear Register High"
bitfld.long 0x04 29. " E61 ,Channel 61 I2CRXEVT1 event clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Channel 60 I2CTXEVT1 event clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Channel 59 I2CRXEVT0 event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Channel 58 I2CTXEVT0 event clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Channel 47 AREVT3 event clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Channel 45 AXEVT3 event clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Channel 44 PCIE_RX event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Channel 53 PCIE_TX event clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Channel 53 HDMIEVT event clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Channel 52 GPMCEVT event clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Channel 51 TINTEVT7 event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Channel 50 TINTEVT6 event clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Channel 49 TINTEVT5 event clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Channel 48 TINTEVT4 event clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Channel 47 CAN_IF3DMA event clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Channel 45 SPI1REVT0 event clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Channel 44 SPI1XEVT1 event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Channel 43 SPI1REVT0 event clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Channel 42 SPI1XEVT0 event clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Channel 41 CAN_IF2DMA event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Channel 40 CAN_IF1DMA event clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Channel 39 ISS_DMA_REQ4 event clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Channel 38 ISS_DMA_REQ3 event clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Channel 37 ISS_DMA_REQ2 event clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Channel 36 ISS_DMA_REQ1 event clear" "No effect,Clear"
endif
rgroup.long 0x310++0x03
line.long 0x00 "QEMR,QDMA Event Missed Register"
bitfld.long 0x00 7. " E7 ,Channel 7 event missed" "Not occurred,Occurred"
bitfld.long 0x00 6. " E6 ,Channel 6 event missed" "Not occurred,Occurred"
bitfld.long 0x00 5. " E5 ,Channel 5 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 4. " E4 ,Channel 4 event missed" "Not occurred,Occurred"
bitfld.long 0x00 3. " E3 ,Channel 3 event missed" "Not occurred,Occurred"
bitfld.long 0x00 2. " E2 ,Channel 2 event missed" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 1. " E1 ,Channel 1 event missed" "Not occurred,Occurred"
bitfld.long 0x00 0. " E0 ,Channel 0 event missed" "Not occurred,Occurred"
wgroup.long 0x314++0x03
line.long 0x00 "QEMCR,QDMA Event Missed Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA event missed clear" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA event missed clear" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA event missed clear" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event missed clear" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA event missed clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA event missed clear" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event missed clear" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA event missed clear" "No effect,Clear"
rgroup.long 0x318++0x03
line.long 0x00 "CCERR,EDMA3CC Error Register"
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error" "No error,Error"
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error for queue 3" "No error,Error"
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error for queue 2" "No error,Error"
textline " "
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error for queue 1" "No error,Error"
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error for queue 0" "No error,Error"
wgroup.long 0x31C++0x03
line.long 0x00 "CCERR,EDMA3CC Error Clear Register"
bitfld.long 0x00 16. " TCCERR ,Transfer completion code error clear" "No effect,Clear"
bitfld.long 0x00 3. " QTHRXCD3 ,Queue threshold error clear for queue 3" "No effect,Clear"
bitfld.long 0x00 2. " QTHRXCD2 ,Queue threshold error clear for queue 2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " QTHRXCD1 ,Queue threshold error clear for queue 1" "No effect,Clear"
bitfld.long 0x00 0. " QTHRXCD0 ,Queue threshold error clear for queue 0" "No effect,Clear"
wgroup.long 0x320++0x03
line.long 0x00 "EEVAL,Error Evaluation Register"
bitfld.long 0x00 0. " EVAL ,Error interrupt evaluate" "No effect,Evaluate"
tree.end
tree "Region Access Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
group.long 0x340++0x07
line.long 0x00 "DRAE0,DMA Region Access Enable Register for Region 0"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 0" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 0" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 0" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 0" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 0" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 0" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 0" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 0" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 0" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 0" "Disabled,Enabled"
line.long 0x04 "DRAEH0,DMA Region Access Enable High Register for Region 0"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 0" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 0" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 0" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 0" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 0" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 0" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 0" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 0" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 0" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 0" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 0" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 0" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 0" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 0" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 0" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 0" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 0" "Disabled,Enabled"
group.long 0x348++0x07
line.long 0x00 "DRAE1,DMA Region Access Enable Register for Region 1"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 1" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 1" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 1" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 1" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 1" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 1" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 1" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 1" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 1" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 1" "Disabled,Enabled"
line.long 0x04 "DRAEH1,DMA Region Access Enable High Register for Region 1"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 1" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 1" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 1" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 1" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 1" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 1" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 1" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 1" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 1" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 1" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 1" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 1" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 1" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 1" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 1" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 1" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 1" "Disabled,Enabled"
group.long 0x350++0x07
line.long 0x00 "DRAE2,DMA Region Access Enable Register for Region 2"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 2" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 2" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 2" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 2" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 2" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 2" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 2" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 2" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 2" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 2" "Disabled,Enabled"
line.long 0x04 "DRAEH2,DMA Region Access Enable High Register for Region 2"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 2" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 2" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 2" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 2" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 2" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 2" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 2" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 2" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 2" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 2" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 2" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 2" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 2" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 2" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 2" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 2" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 2" "Disabled,Enabled"
group.long 0x358++0x07
line.long 0x00 "DRAE3,DMA Region Access Enable Register for Region 3"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 3" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 3" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 3" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 3" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 3" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 3" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 3" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 3" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 3" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 3" "Disabled,Enabled"
line.long 0x04 "DRAEH3,DMA Region Access Enable High Register for Region 3"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 3" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 3" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 3" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 3" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 3" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 3" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 3" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 3" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 3" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 3" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 3" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 3" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 3" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 3" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 3" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 3" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 3" "Disabled,Enabled"
group.long 0x360++0x07
line.long 0x00 "DRAE4,DMA Region Access Enable Register for Region 4"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 4" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 4" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 4" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 4" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 4" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 4" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 4" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 4" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 4" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 4" "Disabled,Enabled"
line.long 0x04 "DRAEH4,DMA Region Access Enable High Register for Region 4"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 4" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 4" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 4" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 4" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 4" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 4" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 4" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 4" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 4" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 4" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 4" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 4" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 4" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 4" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 4" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 4" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 4" "Disabled,Enabled"
group.long 0x368++0x07
line.long 0x00 "DRAE5,DMA Region Access Enable Register for Region 5"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 5" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 5" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 5" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 5" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 5" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 5" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 5" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 5" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 5" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 5" "Disabled,Enabled"
line.long 0x04 "DRAEH5,DMA Region Access Enable High Register for Region 5"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 5" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 5" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 5" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 5" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 5" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 5" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 5" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 5" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 5" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 5" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 5" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 5" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 5" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 5" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 5" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 5" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 5" "Disabled,Enabled"
group.long 0x370++0x07
line.long 0x00 "DRAE6,DMA Region Access Enable Register for Region 6"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 6" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 6" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 6" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 6" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 6" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 6" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 6" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 6" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 6" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 6" "Disabled,Enabled"
line.long 0x04 "DRAEH6,DMA Region Access Enable High Register for Region 6"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 6" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 6" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 6" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 6" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 6" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 6" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 6" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 6" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 6" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 6" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 6" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 6" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 6" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 6" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 6" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 6" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 6" "Disabled,Enabled"
group.long 0x378++0x07
line.long 0x00 "DRAE7,DMA Region Access Enable Register for Region 7"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region 7" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region 7" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region 7" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region 7" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region 7" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region 7" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region 7" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region 7" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region 7" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,DMA region access enable for bit 3 /SDRXEVT1 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " E2 ,DMA region access enable for bit 2 /SDTXEVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 1. " E1 ,DMA region access enable for bit 1 /VCPXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,DMA region access enable for bit 0 /VCPREVT0 in region 7" "Disabled,Enabled"
line.long 0x04 "DRAEH7,DMA Region Access Enable High Register for Region 7"
bitfld.long 0x04 31. " E63 ,DMA region access enable for bit 63 /AREVT4 in region 7" "Disabled,Enabled"
bitfld.long 0x04 30. " E62 ,DMA region access enable for bit 62 /AXEVT4 in region 7" "Disabled,Enabled"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 61 /I2CRXEVT1 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 60 /I2CTXEVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 59 /I2CRXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 58 /I2CTXEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x04 25. " E57 ,DMA region access enable for bit 57 /AREVT3 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " E56 ,DMA region access enable for bit 56 /AXEVT3 in region 7" "Disabled,Enabled"
bitfld.long 0x04 23. " E55 ,DMA region access enable for bit 55 /PCIE_RX in region 7" "Disabled,Enabled"
bitfld.long 0x04 22. " E54 ,DMA region access enable for bit 54 /PCIE_TX in region 7" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 53 /HDMIEVT in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 52 /GPMCEVT in region 7" "Disabled,Enabled"
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 51 /TINT7 in region 7" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 50 /TINT6 in region 7" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 49 /TINT5 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 48 /TINT4 in region 7" "Disabled,Enabled"
bitfld.long 0x04 15. " E47 ,DMA region access enable for bit 47 /CAN_IF3DMA in region 7" "Disabled,Enabled"
bitfld.long 0x04 13. " E45 ,DMA region access enable for bit 45 /SPI1REVT1 in region 7" "Disabled,Enabled"
bitfld.long 0x04 12. " E44 ,DMA region access enable for bit 44 /SPI1XEVT1 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " E43 ,DMA region access enable for bit 43 /SPI1REVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x04 10. " E42 ,DMA region access enable for bit 42 /SPI1XEVT0 in region 7" "Disabled,Enabled"
bitfld.long 0x04 9. " E41 ,DMA region access enable for bit 41 /CAN_IF2DMA in region 7" "Disabled,Enabled"
bitfld.long 0x04 8. " E40 ,DMA region access enable for bit 40 /CAN_IF1DMA in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " E39 ,DMA region access enable for bit 39 /ISS_DMA_REQ4 in region 7" "Disabled,Enabled"
bitfld.long 0x04 6. " E38 ,DMA region access enable for bit 38 /ISS_DMA_REQ3 in region 7" "Disabled,Enabled"
bitfld.long 0x04 5. " E37 ,DMA region access enable for bit 37 /ISS_DMA_REQ2 in region 7" "Disabled,Enabled"
bitfld.long 0x04 4. " E36 ,DMA region access enable for bit 36 /ISS_DMA_REQ1 in region 7" "Disabled,Enabled"
group.long 0x380++0x03
line.long 0x00 "QRAE0,QDMA Region Access Enable Registers 0"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 0" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 0" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 0" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 0" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 0" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 0" "Disabled,Enabled"
group.long 0x384++0x03
line.long 0x00 "QRAE1,QDMA Region Access Enable Registers 1"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 1" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 1" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 1" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 1" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 1" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 1" "Disabled,Enabled"
group.long 0x388++0x03
line.long 0x00 "QRAE2,QDMA Region Access Enable Registers 2"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 2" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 2" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 2" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 2" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 2" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 2" "Disabled,Enabled"
group.long 0x38C++0x03
line.long 0x00 "QRAE3,QDMA Region Access Enable Registers 3"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 3" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 3" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 3" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 3" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 3" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 3" "Disabled,Enabled"
group.long 0x390++0x03
line.long 0x00 "QRAE4,QDMA Region Access Enable Registers 4"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 4" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 4" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 4" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 4" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 4" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 4" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 4" "Disabled,Enabled"
group.long 0x394++0x03
line.long 0x00 "QRAE5,QDMA Region Access Enable Registers 5"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 5" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 5" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 5" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 5" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 5" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 5" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 5" "Disabled,Enabled"
group.long 0x398++0x03
line.long 0x00 "QRAE6,QDMA Region Access Enable Registers 6"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 6" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 6" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 6" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 6" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 6" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 6" "Disabled,Enabled"
group.long 0x39C++0x03
line.long 0x00 "QRAE7,QDMA Region Access Enable Registers 7"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region 7" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region 7" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region 7" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region 7" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region 7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region 7" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region 7" "Disabled,Enabled"
else
group.long 0x340++0x07
line.long 0x00 "DRAE0,DMA Region Access Enable Register for Region 0 Cortex-A8"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
line.long 0x04 "DRAEH0,DMA Region Access Enable High Register for Region 0 Cortex-A8"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region0 Cortex-A8" "Disabled,Enabled"
group.long 0x348++0x07
line.long 0x00 "DRAE1,DMA Region Access Enable Register for Region 1 DSP"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region1 DSP" "Disabled,Enabled"
line.long 0x04 "DRAEH1,DMA Region Access Enable High Register for Region 1 DSP"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region1 DSP" "Disabled,Enabled"
group.long 0x350++0x07
line.long 0x00 "DRAE2,DMA Region Access Enable Register for Region 2"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region2" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region2" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region2" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region2" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region2" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region2" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region2" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region2" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region2" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region2" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region2" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region2" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region2" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region2" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region2" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region2" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region2" "Disabled,Enabled"
line.long 0x04 "DRAEH2,DMA Region Access Enable High Register for Region 2"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region2" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region2" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region2" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region2" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region2" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region2" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region2" "Disabled,Enabled"
group.long 0x358++0x07
line.long 0x00 "DRAE3,DMA Region Access Enable Register for Region 3"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region3" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region3" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region3" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region3" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region3" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region3" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region3" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region3" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region3" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region3" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region3" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region3" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region3" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region3" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region3" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region3" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region3" "Disabled,Enabled"
line.long 0x04 "DRAEH3,DMA Region Access Enable High Register for Region 3"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region3" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region3" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region3" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region3" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region3" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region3" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region3" "Disabled,Enabled"
group.long 0x360++0x07
line.long 0x00 "DRAE4,DMA Region Access Enable Register for Region 4 Media Controller 0"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
line.long 0x04 "DRAEH4,DMA Region Access Enable High Register for Region 4 Media Controller 0"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region4 Media Controller 0" "Disabled,Enabled"
group.long 0x368++0x07
line.long 0x00 "DRAE5,DMA Region Access Enable Register for Region 5 Media Controller 1"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
line.long 0x04 "DRAEH5,DMA Region Access Enable High Register for Region 5 Media Controller 1"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region5 Media Controller 1" "Disabled,Enabled"
group.long 0x370++0x07
line.long 0x00 "DRAE6,DMA Region Access Enable Register for Region 6"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region6" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region6" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region6" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region6" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region6" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region6" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region6" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region6" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region6" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region6" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region6" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region6" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region6" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region6" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region6" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region6" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region6" "Disabled,Enabled"
line.long 0x04 "DRAEH6,DMA Region Access Enable High Register for Region 6"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region6" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region6" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region6" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region6" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region6" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region6" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region6" "Disabled,Enabled"
group.long 0x378++0x07
line.long 0x00 "DRAE7,DMA Region Access Enable Register for Region 7"
bitfld.long 0x00 31. " E31 ,DMA region access enable for bit 31 /URXEVT2 in region7" "Disabled,Enabled"
bitfld.long 0x00 30. " E30 ,DMA region access enable for bit 30 /UTXEVT2 in region7" "Disabled,Enabled"
bitfld.long 0x00 29. " E29 ,DMA region access enable for bit 29 /URXEVT1 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " E28 ,DMA region access enable for bit 28 /UTXEVT1 in region7" "Disabled,Enabled"
bitfld.long 0x00 27. " E27 ,DMA region access enable for bit 27 /URXEVT0 in region7" "Disabled,Enabled"
bitfld.long 0x00 26. " E26 ,DMA region access enable for bit 26 /UTXEVT0 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " E25 ,DMA region access enable for bit 25 /SDRXEVT in region7" "Disabled,Enabled"
bitfld.long 0x00 24. " E24 ,DMA region access enable for bit 24 /SDTXEVT in region7" "Disabled,Enabled"
bitfld.long 0x00 23. " E23 ,DMA region access enable for bit 23 /SPIREVT4 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " E22 ,DMA region access enable for bit 22 /SPIXEVT3 in region7" "Disabled,Enabled"
bitfld.long 0x00 21. " E21 ,DMA region access enable for bit 21 /SPIREVT2 in region7" "Disabled,Enabled"
bitfld.long 0x00 20. " E20 ,DMA region access enable for bit 20 /SPIXEVT2 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " E19 ,DMA region access enable for bit 19 /SPIREVT1 in region7" "Disabled,Enabled"
bitfld.long 0x00 18. " E18 ,DMA region access enable for bit 18 /SPIXEVT1 in region7" "Disabled,Enabled"
bitfld.long 0x00 17. " E17 ,DMA region access enable for bit 17 /SPIREVT0 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " E16 ,DMA region access enable for bit 16 /SPIXEVT0 in region7" "Disabled,Enabled"
bitfld.long 0x00 15. " E15 ,DMA region access enable for bit 15 /BREVT in region7" "Disabled,Enabled"
bitfld.long 0x00 14. " E14 ,DMA region access enable for bit 14 /BXEVT in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " E13 ,DMA region access enable for bit 13 /AREVT2 in region7" "Disabled,Enabled"
bitfld.long 0x00 12. " E12 ,DMA region access enable for bit 12 /AXEVT2 in region7" "Disabled,Enabled"
bitfld.long 0x00 11. " E11 ,DMA region access enable for bit 11 /AREVT1 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " E10 ,DMA region access enable for bit 10 /AXEVT1 in region7" "Disabled,Enabled"
bitfld.long 0x00 9. " E9 ,DMA region access enable for bit 9 /AREVT0 in region7" "Disabled,Enabled"
bitfld.long 0x00 8. " E8 ,DMA region access enable for bit 8 /AXEVT0 in region7" "Disabled,Enabled"
line.long 0x04 "DRAEH7,DMA Region Access Enable High Register for Region 7"
bitfld.long 0x04 29. " E61 ,DMA region access enable for bit 29 /I2CRXEVT1 in region7" "Disabled,Enabled"
bitfld.long 0x04 28. " E60 ,DMA region access enable for bit 28 /I2CTXEVT1 in region7" "Disabled,Enabled"
bitfld.long 0x04 27. " E59 ,DMA region access enable for bit 27 /I2CRXEVT0 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " E58 ,DMA region access enable for bit 26 /I2CTXEVT0 in region7" "Disabled,Enabled"
bitfld.long 0x04 21. " E53 ,DMA region access enable for bit 21 /HDMIEVT in region7" "Disabled,Enabled"
bitfld.long 0x04 20. " E52 ,DMA region access enable for bit 20 /GPMCEVT in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " E51 ,DMA region access enable for bit 19 /TINTEVT7 in region7" "Disabled,Enabled"
bitfld.long 0x04 18. " E50 ,DMA region access enable for bit 18 /TINTEVT6 in region7" "Disabled,Enabled"
bitfld.long 0x04 17. " E49 ,DMA region access enable for bit 17 /TINTEVT5 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " E48 ,DMA region access enable for bit 16 /TINTEVT4 in region7" "Disabled,Enabled"
group.long 0x380++0x03
line.long 0x00 "QRAE0,QDMA Region Access Enable Registers 0 Cortex-A8"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region0 Cortex-A8" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region0 Cortex-A8" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region0 Cortex-A8" "Disabled,Enabled"
group.long 0x384++0x03
line.long 0x00 "QRAE1,QDMA Region Access Enable Registers 1 DSP"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region1 DSP" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region1 DSP" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region1 DSP" "Disabled,Enabled"
group.long 0x388++0x03
line.long 0x00 "QRAE2,QDMA Region Access Enable Registers 2"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region2" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region2" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region2" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region2" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region2" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region2" "Disabled,Enabled"
group.long 0x38C++0x03
line.long 0x00 "QRAE3,QDMA Region Access Enable Registers 3"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region3" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region3" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region3" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region3" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region3" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region3" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region3" "Disabled,Enabled"
group.long 0x390++0x03
line.long 0x00 "QRAE4,QDMA Region Access Enable Registers 4 Media Controller 0"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region4 Media Controller 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region4 Media Controller 0" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region4 Media Controller 0" "Disabled,Enabled"
group.long 0x394++0x03
line.long 0x00 "QRAE5,QDMA Region Access Enable Registers 5 Media Controller 1"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region5 Media Controller 1" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region5 Media Controller 1" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region5 Media Controller 1" "Disabled,Enabled"
group.long 0x398++0x03
line.long 0x00 "QRAE6,QDMA Region Access Enable Registers 6"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region6" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region6" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region6" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region6" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region6" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region6" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region6" "Disabled,Enabled"
group.long 0x39C++0x03
line.long 0x00 "QRAE7,QDMA Region Access Enable Registers 7"
bitfld.long 0x00 7. " E7 ,QDMA region access enable for bit 7 /channel 7 in region7" "Disabled,Enabled"
bitfld.long 0x00 6. " E6 ,QDMA region access enable for bit 6 /channel 6 in region7" "Disabled,Enabled"
bitfld.long 0x00 5. " E5 ,QDMA region access enable for bit 5 /channel 5 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA region access enable for bit 4 /channel 4 in region7" "Disabled,Enabled"
bitfld.long 0x00 3. " E3 ,QDMA region access enable for bit 3 /channel 3 in region7" "Disabled,Enabled"
bitfld.long 0x00 2. " E2 ,QDMA region access enable for bit 2 /channel 2 in region7" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA region access enable for bit 1 /channel 1 in region7" "Disabled,Enabled"
bitfld.long 0x00 0. " E0 ,QDMA region access enable for bit 0 /channel 0 in region7" "Disabled,Enabled"
endif
tree.end
tree "Status/Debug Visibility Registers"
rgroup.long 0x400++0x03
line.long 0x00 "Q0E0,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 0 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x404++0x03
line.long 0x00 "Q0E1,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 1 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x408++0x03
line.long 0x00 "Q0E2,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 2 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x40C++0x03
line.long 0x00 "Q0E3,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 3 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x410++0x03
line.long 0x00 "Q0E4,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 4 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x414++0x03
line.long 0x00 "Q0E5,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 5 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x418++0x03
line.long 0x00 "Q0E6,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 6 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x41C++0x03
line.long 0x00 "Q0E7,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 7 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x420++0x03
line.long 0x00 "Q0E8,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 8 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x424++0x03
line.long 0x00 "Q0E9,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 9 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x428++0x03
line.long 0x00 "Q0E10,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 10 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x42C++0x03
line.long 0x00 "Q0E11,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 11 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x430++0x03
line.long 0x00 "Q0E12,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 12 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x434++0x03
line.long 0x00 "Q0E13,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 13 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x438++0x03
line.long 0x00 "Q0E14,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 14 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x43C++0x03
line.long 0x00 "Q0E15,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 15 in queue 0" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x440++0x03
line.long 0x00 "Q1E0,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 0 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x444++0x03
line.long 0x00 "Q1E1,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 1 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x448++0x03
line.long 0x00 "Q1E2,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 2 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x44C++0x03
line.long 0x00 "Q1E3,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 3 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x450++0x03
line.long 0x00 "Q1E4,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 4 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x454++0x03
line.long 0x00 "Q1E5,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 5 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x458++0x03
line.long 0x00 "Q1E6,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 6 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x45C++0x03
line.long 0x00 "Q1E7,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 7 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x460++0x03
line.long 0x00 "Q1E8,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 8 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x464++0x03
line.long 0x00 "Q1E9,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 9 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x468++0x03
line.long 0x00 "Q1E10,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 10 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x46C++0x03
line.long 0x00 "Q1E11,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 11 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x470++0x03
line.long 0x00 "Q1E12,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 12 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x474++0x03
line.long 0x00 "Q1E13,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 13 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x478++0x03
line.long 0x00 "Q1E14,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 14 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x47C++0x03
line.long 0x00 "Q1E15,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 15 in queue 1" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x480++0x03
line.long 0x00 "Q2E0,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 0 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x484++0x03
line.long 0x00 "Q2E1,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 1 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x488++0x03
line.long 0x00 "Q2E2,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 2 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x48C++0x03
line.long 0x00 "Q2E3,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 3 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x490++0x03
line.long 0x00 "Q2E4,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 4 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x494++0x03
line.long 0x00 "Q2E5,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 5 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x498++0x03
line.long 0x00 "Q2E6,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 6 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x49C++0x03
line.long 0x00 "Q2E7,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 7 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4A0++0x03
line.long 0x00 "Q2E8,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 8 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4A4++0x03
line.long 0x00 "Q2E9,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 9 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4A8++0x03
line.long 0x00 "Q2E10,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 10 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4AC++0x03
line.long 0x00 "Q2E11,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 11 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4B0++0x03
line.long 0x00 "Q2E12,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 12 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4B4++0x03
line.long 0x00 "Q2E13,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 13 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4B8++0x03
line.long 0x00 "Q2E14,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 14 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4BC++0x03
line.long 0x00 "Q2E15,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 15 in queue 2" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4C0++0x03
line.long 0x00 "Q3E0,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 0 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 0 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4C4++0x03
line.long 0x00 "Q3E1,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 1 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 1 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4C8++0x03
line.long 0x00 "Q3E2,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 2 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 2 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4CC++0x03
line.long 0x00 "Q3E3,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 3 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 3 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4D0++0x03
line.long 0x00 "Q3E4,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 4 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 4 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4D4++0x03
line.long 0x00 "Q3E5,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 5 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 5 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4D8++0x03
line.long 0x00 "Q3E6,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 6 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 6 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4DC++0x03
line.long 0x00 "Q3E7,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 7 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 7 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4E0++0x03
line.long 0x00 "Q3E8,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 8 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 8 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4E4++0x03
line.long 0x00 "Q3E9,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 9 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 9 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4E8++0x03
line.long 0x00 "Q3E10,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 10 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 10 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4EC++0x03
line.long 0x00 "Q3E11,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 11 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 11 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4F0++0x03
line.long 0x00 "Q3E12,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 12 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 12 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4F4++0x03
line.long 0x00 "Q3E13,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 13 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 13 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4F8++0x03
line.long 0x00 "Q3E14,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 14 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 14 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x4FC++0x03
line.long 0x00 "Q3E15,Event Queue Entry Registers"
bitfld.long 0x00 6.--7. " ETYPE ,Event entry 15 in queue 3" "Event via ER,Manual via ESR,Chain via CER,Auto via QER"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "VCPREVT0,VCPXEVT0,SDTXEVT1,SDRXEVT1,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,ISS_DMA_REQ1,ISS_DMA_REQ2,ISS_DMA_REQ3,ISS_DMA_REQ4,CAN_IF1DMA,CAN_IF2DMA,SPI1XEVT0,SPI1REVT0,SPI1XEVT1,SPI1REVT1,Unused,CAN_IF3DMA,TINT4,TINT5,TINT6,TINT7,GPMCEVT,HDMIEVT,PCIE_TX,PCIE_RX,AXEVT3,AREVT3,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,AXEVT4,AREVT4"
else
bitfld.long 0x00 0.--5. " ENUM ,Event entry 15 in queue 0" "Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,AXEVT0,AREVT0,AXEVT1,AREVT1,AXEVT2,AREVT2,BXEVT,BREVT,SPIXEVT0,SPIREVT0,SPIXEVT1,SPIREVT1,SPIXEVT2,SPIREVT2,SPIXEVT3,SPIREVT4,SDTXEVT,SDRXEVT,UTXEVT0,URXEVT0,UTXEVT1,URXEVT1,UTXEVT2,URXEVT2,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,Unused,TINTEVT4,TINTEVT5,TINTEVT6,TINTEVT7,GPMCEVT,HDMIEVT,Unused,Unused,Unused,Unused,I2CTXEVT0,I2CRXEVT0,I2CTXEVT1,I2CRXEVT1,Unused,Unused"
endif
rgroup.long 0x600++0x03
line.long 0x00 "QSTAT0,Queue Status Registers"
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 0" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
textline " "
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x604++0x03
line.long 0x00 "QSTAT1,Queue Status Registers"
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 1" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
textline " "
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x608++0x03
line.long 0x00 "QSTAT2,Queue Status Registers"
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 2" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
textline " "
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x60C++0x03
line.long 0x00 "QSTAT3,Queue Status Registers"
bitfld.long 0x00 24. " THRXCD ,Threshold exceeded" "Not exceeded,Exceeded"
bitfld.long 0x00 16.--20. " WM ,Watermark for maximum queue usage" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
bitfld.long 0x00 8.--12. " NUMVAL ,Number of valid entries in queue 3" "Empty,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Full,?..."
textline " "
bitfld.long 0x00 0.--3. " STRTPTR ,Start pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x3
line.long 0x00 "QWMTHRA,Queue Watermark Threshold A Register"
bitfld.long 0x00 24.--28. " Q3 ,Queue threshold for queue 3 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Maximum,Disabled,?..."
bitfld.long 0x00 16.--20. " Q2 ,Queue threshold for queue 2 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Maximum,Disabled,?..."
bitfld.long 0x00 8.--12. " Q1 ,Queue threshold for queue 1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Maximum,Disabled,?..."
textline " "
bitfld.long 0x00 0.--4. " Q0 ,Queue threshold for queue 0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,Maximum,Disabled,?..."
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,EDMA3CC Status Register"
bitfld.long 0x00 19. " QUEACTV3 ,Queue 3 active" "Inactive,Active"
bitfld.long 0x00 18. " QUEACTV2 ,Queue 2 active" "Inactive,Active"
bitfld.long 0x00 17. " QUEACTV1 ,Queue 1 active" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " QUEACTV0 ,Queue 0 active" "Inactive,Active"
bitfld.long 0x00 8.--13. " COMPACTV ,Completion request active" "No completion,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 4. " ACTV ,Channel controller active" "Idle,Busy"
textline " "
bitfld.long 0x00 2. " TRACTV ,Transfer request active" "Inactive,Active"
bitfld.long 0x00 1. " QEVTACTV ,QDMA event active" "No enabled,Active QER"
bitfld.long 0x00 0. " EVTACTV ,DMA event active" "No enabled,Active ER&EER/ESR/CER"
tree.end
tree "Memory Protection Address Space"
rgroup.long 0x800++0x07
line.long 0x00 "MPFAR,Memory Protection Fault Address Register"
line.long 0x04 "MPFSR,Memory Protection Fault Status Register"
bitfld.long 0x04 9.--12. " FID ,Faulted identification" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 5. " SRE ,Supervisor read error" "No error,Error"
bitfld.long 0x04 4. " SWE ,Supervisor write error" "No error,Error"
textline " "
bitfld.long 0x04 3. " SXE ,Supervisor execute error" "No error,Error"
bitfld.long 0x04 2. " URE ,User read error" "No error,Error"
bitfld.long 0x04 1. " UWE ,User write error" "No error,Error"
textline " "
bitfld.long 0x04 0. " UXE ,User execute error" "No error,Error"
wgroup.long 0x808++0x03
line.long 0x00 "MPFCR,Memory Protection Fault Command Register"
bitfld.long 0x00 0. " MPFCLR ,Fault clear register" "No effect,Clear"
group.long 0x810++0x03
line.long 0x00 "MPPA0,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 0" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 0" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 0" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 0" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 0" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 0" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x814++0x03
line.long 0x00 "MPPA1,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 1" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 1" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 1" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 1" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 1" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 1" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x818++0x03
line.long 0x00 "MPPA2,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 2" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 2" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 2" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 2" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 2" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 2" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x81C++0x03
line.long 0x00 "MPPA3,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 3" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 3" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 3" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 3" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 3" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 3" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x820++0x03
line.long 0x00 "MPPA4,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 4" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 4" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 4" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 4" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 4" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 4" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x824++0x03
line.long 0x00 "MPPA5,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 5" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 5" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 5" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 5" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 5" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 5" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x828++0x03
line.long 0x00 "MPPA6,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 6" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 6" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 6" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 6" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 6" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 6" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
group.long 0x82C++0x03
line.long 0x00 "MPPA7,Memory Protection Page Attribute Register"
bitfld.long 0x00 15. " AID5 ,Allowed ID 7" "Not allowed,Allowed"
bitfld.long 0x00 14. " AID4 ,Allowed ID 7" "Not allowed,Allowed"
bitfld.long 0x00 13. " AID3 ,Allowed ID 7" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 12. " AID2 ,Allowed ID 7" "Not allowed,Allowed"
bitfld.long 0x00 11. " AID1 ,Allowed ID 7" "Not allowed,Allowed"
bitfld.long 0x00 10. " AID0 ,Allowed ID 7" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 9. " EXT ,External Allowed ID" "Not allowed,Allowed"
bitfld.long 0x00 5. " SR ,Supervisor read permission" "Read/Not allowed,Write/Allowed"
bitfld.long 0x00 4. " SW ,Supervisor write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 3. " SX ,Supervisor execute permission" "Not allowed,Allowed"
bitfld.long 0x00 2. " UR ,User read permission" "Not allowed,Allowed"
bitfld.long 0x00 1. " UW ,User write permission" "Not allowed,Allowed"
textline " "
bitfld.long 0x00 0. " UX ,User execute permission" "Not allowed,Allowed"
tree.end
tree "DMA Channel Registers"
group.long 0x1000++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Events 31 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long 0x1004++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long 0x1018++0x07
line.long 0x00 "CER,Chained Event Register"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E12 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long 0x1020++0x03
line.long 0x00 "EER,Event Enable Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long 0x1024++0x03
line.long 0x00 "EERH,Event Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Events AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Events AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Events AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Events AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Events PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Events PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Events CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Events SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Events SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Events SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Events SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Events CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Events CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Events ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Events ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Events ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Events ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long 0x1038++0x07
line.long 0x00 "SER,Secondary Event Register"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long 0x1040++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
tree.end
tree "Interrupt Registers"
group.long 0x1050++0x03
line.long 0x00 "IER,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long 0x1054++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long 0x1068++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long 0x1070++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long 0x1078++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long 0x1080++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long 0x1084++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long 0x1090++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long 0x1094++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
tree "Shadow Channels Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 0 Channel Registers"
else
tree "Shadow Region 0 Cortex-A8Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2000++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2000+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2000+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2000+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2000+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2000+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2000+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2000+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2000+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2000+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2000+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2000+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2000+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2000+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2000+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2000+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 1 Channel Registers"
else
tree "Shadow Region 1 DSPChannel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2200++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2200+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2200+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2200+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2200+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2200+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2200+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2200+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2200+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2200+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2200+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2200+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2200+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2200+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2200+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2200+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 2 Channel Registers"
else
tree "Shadow Region 2Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2400++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2400+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2400+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2400+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2400+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2400+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2400+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2400+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2400+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2400+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2400+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2400+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2400+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2400+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2400+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2400+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 3 Channel Registers"
else
tree "Shadow Region 3Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2600++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2600+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2600+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2600+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2600+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2600+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2600+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2600+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2600+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2600+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2600+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2600+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2600+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2600+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2600+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2600+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 4 Channel Registers"
else
tree "Shadow Region 4 Media Controller 0Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2800++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2800+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2800+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2800+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2800+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2800+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2800+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2800+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2800+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2800+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2800+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2800+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2800+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2800+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2800+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2800+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 5 Channel Registers"
else
tree "Shadow Region 5 Media Controller 1Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2A00++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2A00+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2A00+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2A00+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2A00+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2A00+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2A00+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2A00+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2A00+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2A00+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2A00+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2A00+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2A00+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2A00+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2A00+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2A00+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 6 Channel Registers"
else
tree "Shadow Region 6Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2C00++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2C00+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2C00+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2C00+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2C00+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2C00+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2C00+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2C00+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2C00+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2C00+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2C00+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2C00+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2C00+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2C00+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2C00+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2C00+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "Shadow Region 7 Channel Registers"
else
tree "Shadow Region 7Channel Registers"
endif
tree "DMA Channel Registers"
group.long 0x2E00++0x03
line.long 0x00 "ER,Event Register"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,URXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,UTXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,URXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,UTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,URXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,UTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,SDRXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,SDTXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,SPIREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,SPIXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,SPIREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,SPIXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,SPIREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,SPIXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,SPIREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,SPIXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,BREVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,BXEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,AREVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,AXEVT2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,AREVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,AXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,AREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,AXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,SDRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,SDTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,VCPXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,VCPREVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
group.long (0x2E00+0x04)++0x03
line.long 0x00 "ERH,Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,AREVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,AXEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,I2CRXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,I2CTXEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,I2CRXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,I2CTXEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,AREVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,AXEVT3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,PCIE_RX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,PCIE_TX are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,HDMIEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,GPMCEVT are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,TINTEVT7 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,TINTEVT6 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,TINTEVT5 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,TINTEVT4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,CAN_IF3DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,SPI1REVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,SPI1XEVT1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,SPI1REVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,SPI1XEVT0 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,CAN_IF2DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,CAN_IF1DMA are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,ISS_DMA_REQ4 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,ISS_DMA_REQ3 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,ISS_DMA_REQ2 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,ISS_DMA_REQ1 are captured by the EDMA3CC and are latched into ER" "Not asserted,Asserted"
endif
rgroup.long (0x2E00+0x18)++0x07
line.long 0x00 "CER,Chained Event Registers"
bitfld.long 0x00 31. " E31 ,Chained event for URXEVT2" "No effect,Chained"
bitfld.long 0x00 30. " E30 ,Chained event for UTXEVT2" "No effect,Chained"
bitfld.long 0x00 29. " E29 ,Chained event for URXEVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 28. " E28 ,Chained event for UTXEVT1" "No effect,Chained"
bitfld.long 0x00 27. " E27 ,Chained event for URXEVT0" "No effect,Chained"
bitfld.long 0x00 26. " E26 ,Chained event for UTXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 25. " E25 ,Chained event for SDRXEVT" "No effect,Chained"
bitfld.long 0x00 24. " E24 ,Chained event for SDTXEVT" "No effect,Chained"
bitfld.long 0x00 23. " E23 ,Chained event for SPIREVT4" "No effect,Chained"
textline " "
bitfld.long 0x00 22. " E22 ,Chained event for SPIXEVT3" "No effect,Chained"
bitfld.long 0x00 21. " E21 ,Chained event for SPIREVT2" "No effect,Chained"
bitfld.long 0x00 20. " E20 ,Chained event for SPIXEVT2" "No effect,Chained"
textline " "
bitfld.long 0x00 19. " E19 ,Chained event for SPIREVT1" "No effect,Chained"
bitfld.long 0x00 18. " E18 ,Chained event for SPIXEVT1" "No effect,Chained"
bitfld.long 0x00 17. " E17 ,Chained event for SPIREVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 16. " E16 ,Chained event for SPIXEVT0" "No effect,Chained"
bitfld.long 0x00 15. " E15 ,Chained event for BREVT" "No effect,Chained"
bitfld.long 0x00 14. " E14 ,Chained event for BXEVT" "No effect,Chained"
textline " "
bitfld.long 0x00 13. " E13 ,Chained event for AREVT2" "No effect,Chained"
bitfld.long 0x00 12. " E12 ,Chained event for AXEVT2" "No effect,Chained"
bitfld.long 0x00 11. " E11 ,Chained event for AREVT1" "No effect,Chained"
textline " "
bitfld.long 0x00 10. " E10 ,Chained event for AXEVT1" "No effect,Chained"
bitfld.long 0x00 9. " E9 ,Chained event for AREVT0" "No effect,Chained"
bitfld.long 0x00 8. " E8 ,Chained event for AXEVT0" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Chained event for SDRXEVT1" "No effect,Chained"
bitfld.long 0x00 2. " E2 ,Chained event for SDTXEVT1" "No effect,Chained"
bitfld.long 0x00 1. " E1 ,Chained event for VCPXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x00 0. " E0 ,Chained event for VCPREVT0" "No effect,Chained"
endif
line.long 0x04 "CERH,Chained Event Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Chained event for AREVT4" "No effect,Chained"
bitfld.long 0x04 30. " E62 ,Chained event for AXEVT4" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Chained event for I2CRXEVT1" "No effect,Chained"
bitfld.long 0x04 28. " E60 ,Chained event for I2CTXEVT1" "No effect,Chained"
bitfld.long 0x04 27. " E59 ,Chained event for I2CRXEVT0" "No effect,Chained"
textline " "
bitfld.long 0x04 26. " E58 ,Chained event for I2CTXEVT0" "No effect,Chained"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Chained event for AREVT3" "No effect,Chained"
bitfld.long 0x04 24. " E56 ,Chained event for AXEVT3" "No effect,Chained"
bitfld.long 0x04 23. " E55 ,Chained event for PCIE_RX" "No effect,Chained"
textline " "
bitfld.long 0x04 22. " E54 ,Chained event for PCIE_TX" "No effect,Chained"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Chained event for HDMIEVT" "No effect,Chained"
bitfld.long 0x04 20. " E52 ,Chained event for GPMCEVT" "No effect,Chained"
bitfld.long 0x04 19. " E51 ,Chained event for TINTEVT7" "No effect,Chained"
textline " "
bitfld.long 0x04 18. " E50 ,Chained event for TINTEVT6" "No effect,Chained"
bitfld.long 0x04 17. " E49 ,Chained event for TINTEVT5" "No effect,Chained"
bitfld.long 0x04 16. " E48 ,Chained event for TINTEVT4" "No effect,Chained"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Chained event for CAN_IF3DMA" "No effect,Chained"
bitfld.long 0x04 13. " E45 ,Chained event for SPI1REVT1" "No effect,Chained"
bitfld.long 0x04 12. " E44 ,Chained event for SPI1XEVT1" "No effect,Chained"
textline " "
bitfld.long 0x04 11. " E43 ,Chained event for SPI1REVT0" "No effect,Chained"
bitfld.long 0x04 10. " E42 ,Chained event for SPI1XEVT0" "No effect,Chained"
bitfld.long 0x04 9. " E41 ,Chained event for CAN_IF2DMA" "No effect,Chained"
textline " "
bitfld.long 0x04 8. " E40 ,Chained event for CAN_IF1DMA" "No effect,Chained"
bitfld.long 0x04 7. " E39 ,Chained event for ISS_DMA_REQ4" "No effect,Chained"
bitfld.long 0x04 6. " E38 ,Chained event for ISS_DMA_REQ3" "No effect,Chained"
textline " "
bitfld.long 0x04 5. " E37 ,Chained event for ISS_DMA_REQ2" "No effect,Chained"
bitfld.long 0x04 4. " E36 ,Chained event for ISS_DMA_REQ1" "No effect,Chained"
endif
group.long (0x2E00+0x20)++0x03
line.long 0x00 "EER,Event Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E31_set/clr ,Event URXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E30_set/clr ,Event UTXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E29_set/clr ,Event URXEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E28_set/clr ,Event UTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E27_set/clr ,Event URXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E26_set/clr ,Event UTXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E25_set/clr ,Event SDRXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E24_set/clr ,Event SDTXEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E23_set/clr ,Event SPIREVT4 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E22_set/clr ,Event SPIXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E21_set/clr ,Event SPIREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E20_set/clr ,Event SPIXEVT2 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E19_set/clr ,Event SPIREVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E18_set/clr ,Event SPIXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E17_set/clr ,Event SPIREVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E16_set/clr ,Event SPIXEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E15_set/clr ,Event BREVT enable" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " E14_set/clr ,Event BXEVT enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E13_set/clr ,Event AREVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E12_set/clr ,Event AXEVT2 enable" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E11_set/clr ,Event AREVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E10_set/clr ,Event AXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E9_set/clr ,Event AREVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E8_set/clr ,Event AXEVT0 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " E3_set/clr ,Event SDRXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " E2_set/clr ,Event SDTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " E1_set/clr ,Event VCPXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " E0_set/clr ,Event VCPREVT0 enable" "Disabled,Enabled"
endif
group.long (0x2E00+0x24)++0x03
line.long 0x00 "EERH,Event Enable Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " E63_set/clr ,Event AREVT4 enable" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " E62_set/clr ,Event AXEVT4 enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " E61_set/clr ,Events I2CRXEVT1 61 enable" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " E60_set/clr ,Events I2CTXEVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " E59_set/clr ,Events I2CRXEVT0 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " E58_set/clr ,Events I2CTXEVT0 enable" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " E57_set/clr ,Event AREVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " E56_set/clr ,Event AXEVT3 enable" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " E55_set/clr ,Event PCIE_RX enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " E54_set/clr ,Event PCIE_TX enable" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " E53_set/clr ,Events HDMIEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " E52_set/clr ,Events GPMCEVT enable" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " E51_set/clr ,Events TINTEVT7 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " E50_set/clr ,Events TINTEVT6 enable" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " E49_set/clr ,Events TINTEVT5 enable" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " E48_set/clr ,Events TINTEVT4 enable" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " E47_set/clr ,Event CAN_IF3DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " E45_set/clr ,Event SPI1REVT1 enable" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " E44_set/clr ,Event SPI1XEVT1 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " E43_set/clr ,Event SPI1REVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " E42_set/clr ,Event SPI1XEVT0 enable" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " E41_set/clr ,Event CAN_IF2DMA enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " E40_set/clr ,Event CAN_IF1DMA enable" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " E39_set/clr ,Event ISS_DMA_REQ4 enable" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " E38_set/clr ,Event ISS_DMA_REQ3 enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " E37_set/clr ,Event ISS_DMA_REQ2 enable" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " E36_set/clr ,Event ISS_DMA_REQ1 enable" "Disabled,Enabled"
endif
rgroup.long (0x2E00+0x38)++0x07
line.long 0x00 "SER,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT store" "Not stored,Stored"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT store" "Not stored,Stored"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 store" "Not stored,Stored"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 store" "Not stored,Stored"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 store" "Not stored,Stored"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 store" "Not stored,Stored"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT store" "Not stored,Stored"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT store" "Not stored,Stored"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 store" "Not stored,Stored"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 store" "Not stored,Stored"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 store" "Not stored,Stored"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 store" "Not stored,Stored"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 store" "Not stored,Stored"
endif
line.long 0x04 "SERH,Secondary event stores"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 store" "Not stored,Stored"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 store" "Not stored,Stored"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 store" "Not stored,Stored"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 store" "Not stored,Stored"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 store" "Not stored,Stored"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX store" "Not stored,Stored"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX store" "Not stored,Stored"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT store" "Not stored,Stored"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT store" "Not stored,Stored"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 store" "Not stored,Stored"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 store" "Not stored,Stored"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 store" "Not stored,Stored"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA store" "Not stored,Stored"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 store" "Not stored,Stored"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 store" "Not stored,Stored"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 store" "Not stored,Stored"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA store" "Not stored,Stored"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA store" "Not stored,Stored"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 store" "Not stored,Stored"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 store" "Not stored,Stored"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 store" "Not stored,Stored"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 store" "Not stored,Stored"
endif
wgroup.long (0x2E00+0x40)++0x07
line.long 0x00 "SECR,Secondary Event Registers"
bitfld.long 0x00 31. " E31 ,Secondary event URXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 30. " E30 ,Secondary event UTXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 29. " E29 ,Secondary event URXEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " E28 ,Secondary event UTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 27. " E27 ,Secondary event URXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 26. " E26 ,Secondary event UTXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " E25 ,Secondary event SDRXEVT clear" "No effect,Clear"
bitfld.long 0x00 24. " E24 ,Secondary event SDTXEVT clear" "No effect,Clear"
bitfld.long 0x00 23. " E23 ,Secondary event SPIREVT4 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " E22 ,Secondary event SPIXEVT3 clear" "No effect,Clear"
bitfld.long 0x00 21. " E21 ,Secondary event SPIREVT2 clear" "No effect,Clear"
bitfld.long 0x00 20. " E20 ,Secondary event SPIXEVT2 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " E19 ,Secondary event SPIREVT1 clear" "No effect,Clear"
bitfld.long 0x00 18. " E18 ,Secondary event SPIXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 17. " E17 ,Secondary event SPIREVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " E16 ,Secondary event SPIXEVT0 clear" "No effect,Clear"
bitfld.long 0x00 15. " E15 ,Secondary event BREVT clear" "No effect,Clear"
bitfld.long 0x00 14. " E14 ,Secondary event BXEVT clear" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " E13 ,Secondary event AREVT2 clear" "No effect,Clear"
bitfld.long 0x00 12. " E12 ,Secondary event AXEVT2 clear" "No effect,Clear"
bitfld.long 0x00 11. " E11 ,Secondary event AREVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " E10 ,Secondary event AXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 9. " E9 ,Secondary event AREVT0 clear" "No effect,Clear"
bitfld.long 0x00 8. " E8 ,Secondary event AXEVT0 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " E3 ,Secondary event SDRXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,Secondary event SDTXEVT1 clear" "No effect,Clear"
bitfld.long 0x00 1. " E1 ,Secondary event VCPXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " E0 ,Secondary event VCPREVT0 clear" "No effect,Clear"
endif
line.long 0x04 "SECRH,Secondary Event Clear Registers"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " E63 ,Secondary event AREVT4 clear" "No effect,Clear"
bitfld.long 0x04 30. " E62 ,Secondary event AXEVT4 clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " E61 ,Secondary event I2CRXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 28. " E60 ,Secondary event I2CTXEVT1 clear" "No effect,Clear"
bitfld.long 0x04 27. " E59 ,Secondary event I2CRXEVT0 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " E58 ,Secondary event I2CTXEVT0 clear" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " E57 ,Secondary event AREVT3 clear" "No effect,Clear"
bitfld.long 0x04 24. " E56 ,Secondary event AXEVT3 clear" "No effect,Clear"
bitfld.long 0x04 23. " E55 ,Secondary event PCIE_RX clear" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " E54 ,Secondary event PCIE_TX clear" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " E53 ,Secondary event HDMIEVT clear" "No effect,Clear"
bitfld.long 0x04 20. " E52 ,Secondary event GPMCEVT clear" "No effect,Clear"
bitfld.long 0x04 19. " E51 ,Secondary event TINTEVT7 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " E50 ,Secondary event TINTEVT6 clear" "No effect,Clear"
bitfld.long 0x04 17. " E49 ,Secondary event TINTEVT5 clear" "No effect,Clear"
bitfld.long 0x04 16. " E48 ,Secondary event TINTEVT4 clear" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " E47 ,Secondary event CAN_IF3DMA clear" "No effect,Clear"
bitfld.long 0x04 13. " E45 ,Secondary event SPI1REVT1 clear" "No effect,Clear"
bitfld.long 0x04 12. " E44 ,Secondary event SPI1XEVT1 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " E43 ,Secondary event SPI1REVT0 clear" "No effect,Clear"
bitfld.long 0x04 10. " E42 ,Secondary event SPI1XEVT0 clear" "No effect,Clear"
bitfld.long 0x04 9. " E41 ,Secondary event CAN_IF2DMA clear" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " E40 ,Secondary event CAN_IF1DMA clear" "No effect,Clear"
bitfld.long 0x04 7. " E39 ,Secondary event ISS_DMA_REQ4 clear" "No effect,Clear"
bitfld.long 0x04 6. " E38 ,Secondary event ISS_DMA_REQ3 clear" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " E37 ,Secondary event ISS_DMA_REQ2 clear" "No effect,Clear"
bitfld.long 0x04 4. " E36 ,Secondary event ISS_DMA_REQ1 clear" "No effect,Clear"
endif
group.long (0x2E00+0x50)++0x03
line.long 0x00 "IER,Interrupt Enable Registers"
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I31_set/clr ,Interrupt enable for UART2 / URXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I30_set/clr ,Interrupt enable for UART2 / UTXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I29_set/clr ,Interrupt enable for UART1 / URXEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I28_set/clr ,Interrupt enable for UART1 / UTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I27_set/clr ,Interrupt enable for UART0 / URXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I26_set/clr ,Interrupt enable for UART0 / UTXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I25_set/clr ,Interrupt enable for SD / SDRXEVT" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I24_set/clr ,Interrupt enable for SD / SDTXEVT" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I23_set/clr ,Interrupt enable for SPI / SPIREVT4" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I22_set/clr ,Interrupt enable for SPI / SPIXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I21_set/clr ,Interrupt enable for SPI / SPIREVT2" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I20_set/clr ,Interrupt enable for SPI / SPIXEVT2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I19_set/clr ,Interrupt enable for SPI / SPIREVT1" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I18_set/clr ,Interrupt enable for SPI / SPIXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I17_set/clr ,Interrupt enable for SPI / SPIREVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I16_set/clr ,Interrupt enable for SPI / SPIXEVT0" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I15_set/clr ,Interrupt enable for McBSP / BREVT" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x10 14. 0x08 14. " I14_set/clr ,Interrupt enable for McBSP / BXEVT" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I13_set/clr ,Interrupt enable for McASP2 / AREVT2" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I12_set/clr ,Interrupt enable for McASP2 / AXEVT2" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I11_set/clr ,Interrupt enable for McASP1 / AREVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I10_set/clr ,Interrupt enable for McASP1 / AXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I9_set/clr ,Interrupt enable for McASP0 / AREVT0" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I8_set/clr ,Interrupt enable for McASP0 / AXEVT0" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 3. 0x10 3. 0x08 3. " I3_set/clr ,Interrupt enable for SD/SDIO1 / SDRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x10 2. 0x08 2. " I2_set/clr ,Interrupt enable for SD/SDIO1 / SDTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 1. 0x10 1. 0x08 1. " I1_set/clr ,Interrupt enable for VCP / VCPXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 0. 0x10 0. 0x08 0. " I0_set/clr ,Interrupt enable for VCP / VCPREVT0" "Disabled,Enabled"
endif
group.long (0x2E00+0x54)++0x03
line.long 0x00 "IERH,Interrupt Enable Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 31. 0x10 31. 0x08 31. " I63_set/clr ,Interrupt enable for McASP4 / AREVT4" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x10 30. 0x08 30. " I62_set/clr ,Interrupt enable for McASP4 / AXEVT4" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 29. 0x10 29. 0x08 29. " I61_set/clr ,Interrupt enable for I2C1 / I2CRXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x10 28. 0x08 28. " I60_set/clr ,Interrupt enable for I2C1 / I2CTXEVT1" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x10 27. 0x08 27. " I59_set/clr ,Interrupt enable for I2C0 / I2CRXEVT0" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 26. 0x10 26. 0x08 26. " I58_set/clr ,Interrupt enable for I2C0 / I2CTXEVT0" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
setclrfld.long 0x00 25. 0x10 25. 0x08 25. " I57_set/clr ,Interrupt enable for McASP3 / AREVT3" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x10 24. 0x08 24. " I56_set/clr ,Interrupt enable for McASP3 / AXEVT3" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x10 23. 0x08 23. " I55_set/clr ,Interrupt enable for PCIe / PCIE_RX" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x10 22. 0x08 22. " I54_set/clr ,Interrupt enable for PCIe / PCIE_TX" "Disabled,Enabled"
textline " "
endif
setclrfld.long 0x00 21. 0x10 21. 0x08 21. " I53_set/clr ,Interrupt enable for HDMI / HDMIEVT" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x10 20. 0x08 20. " I52_set/clr ,Interrupt enable for GPMC / GPMCEVT" "Disabled,Enabled"
setclrfld.long 0x00 19. 0x10 19. 0x08 19. " I51_set/clr ,Interrupt enable Timer 7 / TINTEVT7" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 18. 0x10 18. 0x08 18. " I50_set/clr ,Interrupt enable for Timer 6 / TINTEVT6" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x10 17. 0x08 17. " I49_set/clr ,Interrupt enable for Timer 5 / TINTEVT5" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x10 16. 0x08 16. " I48_set/clr ,Interrupt enable for Timer 4 / TINTEVT4" "Disabled,Enabled"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
setclrfld.long 0x00 15. 0x10 15. 0x08 15. " I47_set/clr ,Interrupt enable for DCAN0 / CAN_IF3DMA" "Disabled,Enabled"
setclrfld.long 0x00 13. 0x10 13. 0x08 13. " I45_set/clr ,Interrupt enable for SPI1 / SPI1REVT1" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x10 12. 0x08 12. " I44_set/clr ,Interrupt enable for SPI1 / SPI1XEVT1" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 11. 0x10 11. 0x08 11. " I43_set/clr ,Interrupt enable for SPI1 / SPI1REVT0" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x10 10. 0x08 10. " I42_set/clr ,Interrupt enable for SPI1 / SPI1XEVT0" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x10 9. 0x08 9. " I41_set/clr ,Interrupt enable for DCAN0 / CAN_IF2DMA" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 8. 0x10 8. 0x08 8. " I40_set/clr ,Interrupt enable for DCAN0 / CAN_IF1DMA" "Disabled,Enabled"
setclrfld.long 0x00 7. 0x10 7. 0x08 7. " I39_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ4" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x10 6. 0x08 6. " I38_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ3" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 5. 0x10 5. 0x08 5. " I37_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ2" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x10 4. 0x08 4. " I36_set/clr ,Interrupt enable for ISS / ISS_DMA_REQ1" "Disabled,Enabled"
endif
rgroup.long (0x2E00+0x68)++0x07
line.long 0x00 "IPR,Interrupt Pending Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "Not detected,Detected"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "Not detected,Detected"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "Not detected,Detected"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "Not detected,Detected"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "Not detected,Detected"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "Not detected,Detected"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "Not detected,Detected"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "Not detected,Detected"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "Not detected,Detected"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "Not detected,Detected"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "Not detected,Detected"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "Not detected,Detected"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "Not detected,Detected"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "Not detected,Detected"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "Not detected,Detected"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "Not detected,Detected"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "Not detected,Detected"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "Not detected,Detected"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "Not detected,Detected"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "Not detected,Detected"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt enable for SDRXEVT1" "Not detected,Detected"
bitfld.long 0x00 2. " I2 ,Interrupt enable for SDTXEVT1" "Not detected,Detected"
bitfld.long 0x00 1. " I1 ,Interrupt enable for VCPXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt enable for VCPREVT0" "Not detected,Detected"
endif
line.long 0x04 "IPRH,Interrupt Pending Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt enable for AREVT4" "Not detected,Detected"
bitfld.long 0x04 30. " I62 ,Interrupt enable for AXEVT4" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "Not detected,Detected"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "Not detected,Detected"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "Not detected,Detected"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "Not detected,Detected"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt enable for AREVT3" "Not detected,Detected"
bitfld.long 0x04 24. " I56 ,Interrupt enable for AXEVT3" "Not detected,Detected"
bitfld.long 0x04 23. " I55 ,Interrupt enable for PCIE_RX" "Not detected,Detected"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt enable for PCIE_TX" "Not detected,Detected"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "Not detected,Detected"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "Not detected,Detected"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "Not detected,Detected"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "Not detected,Detected"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "Not detected,Detected"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "Not detected,Detected"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt enable for CAN_IF3DMA" "Not detected,Detected"
bitfld.long 0x04 13. " I45 ,Interrupt enable for SPI1REVT1" "Not detected,Detected"
bitfld.long 0x04 12. " I44 ,Interrupt enable for SPI1XEVT1" "Not detected,Detected"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt enable for SPI1REVT0" "Not detected,Detected"
bitfld.long 0x04 10. " I42 ,Interrupt enable for SPI1XEVT0" "Not detected,Detected"
bitfld.long 0x04 9. " I41 ,Interrupt enable for CAN_IF2DMA" "Not detected,Detected"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt enable for CAN_IF1DMA" "Not detected,Detected"
bitfld.long 0x04 7. " I39 ,Interrupt enable for ISS_DMA_REQ4" "Not detected,Detected"
bitfld.long 0x04 6. " I38 ,Interrupt enable for ISS_DMA_REQ3" "Not detected,Detected"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt enable for ISS_DMA_REQ2" "Not detected,Detected"
bitfld.long 0x04 4. " I36 ,Interrupt enable for ISS_DMA_REQ1" "Not detected,Detected"
endif
wgroup.long (0x2E00+0x70)++0x07
line.long 0x00 "ICR,Interrupt Clear Register"
bitfld.long 0x00 31. " I31 ,Interrupt pending URXEVT2" "No effect,Clear"
bitfld.long 0x00 30. " I30 ,Interrupt pending UTXEVT2" "No effect,Clear"
bitfld.long 0x00 29. " I29 ,Interrupt pending URXEVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 28. " I28 ,Interrupt pending UTXEVT1" "No effect,Clear"
bitfld.long 0x00 27. " I27 ,Interrupt pending URXEVT0" "No effect,Clear"
bitfld.long 0x00 26. " I26 ,Interrupt pending UTXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 25. " I25 ,Interrupt pending SDRXEVT" "No effect,Clear"
bitfld.long 0x00 24. " I24 ,Interrupt pending SDTXEVT" "No effect,Clear"
bitfld.long 0x00 23. " I23 ,Interrupt pending SPIREVT4" "No effect,Clear"
textline " "
bitfld.long 0x00 22. " I22 ,Interrupt pending SPIXEVT3" "No effect,Clear"
bitfld.long 0x00 21. " I21 ,Interrupt pending SPIREVT2" "No effect,Clear"
bitfld.long 0x00 20. " I20 ,Interrupt pending SPIXEVT2" "No effect,Clear"
textline " "
bitfld.long 0x00 19. " I19 ,Interrupt pending SPIREVT1" "No effect,Clear"
bitfld.long 0x00 18. " I18 ,Interrupt pending SPIXEVT1" "No effect,Clear"
bitfld.long 0x00 17. " I17 ,Interrupt pending SPIREVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 16. " I16 ,Interrupt pending SPIXEVT0" "No effect,Clear"
bitfld.long 0x00 15. " I15 ,Interrupt pending BREVT" "No effect,Clear"
bitfld.long 0x00 14. " I14 ,Interrupt pending BXEVT" "No effect,Clear"
textline " "
bitfld.long 0x00 13. " I13 ,Interrupt pending AREVT2" "No effect,Clear"
bitfld.long 0x00 12. " I12 ,Interrupt pending AXEVT2" "No effect,Clear"
bitfld.long 0x00 11. " I11 ,Interrupt pending AREVT1" "No effect,Clear"
textline " "
bitfld.long 0x00 10. " I10 ,Interrupt pending AXEVT1" "No effect,Clear"
bitfld.long 0x00 9. " I9 ,Interrupt pending AREVT0" "No effect,Clear"
bitfld.long 0x00 8. " I8 ,Interrupt pending AXEVT0" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x00 3. " I3 ,Interrupt pending SDRXEVT1" "No effect,Clear"
bitfld.long 0x00 2. " I2 ,Interrupt pending SDTXEVT1" "No effect,Clear"
bitfld.long 0x00 1. " I1 ,Interrupt pending VCPXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x00 0. " I0 ,Interrupt pending VCPREVT0" "No effect,Clear"
endif
line.long 0x04 "ICRH,Interrupt Clear Register High"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 31. " I63 ,Interrupt pending AREVT4" "No effect,Clear"
bitfld.long 0x04 30. " I62 ,Interrupt pending AXEVT4" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 29. " I61 ,Interrupt pending I2CRXEVT1" "No effect,Clear"
bitfld.long 0x04 28. " I60 ,Interrupt pending I2CTXEVT1" "No effect,Clear"
bitfld.long 0x04 27. " I59 ,Interrupt pending I2CRXEVT0" "No effect,Clear"
textline " "
bitfld.long 0x04 26. " I58 ,Interrupt pending I2CTXEVT0" "No effect,Clear"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x04 25. " I57 ,Interrupt pending AREVT3" "No effect,Clear"
bitfld.long 0x04 24. " I56 ,Interrupt pending AXEVT3" "No effect,Clear"
bitfld.long 0x04 23. " I55 ,Interrupt pending PCIE_RX" "No effect,Clear"
textline " "
bitfld.long 0x04 22. " I54 ,Interrupt pending PCIE_TX" "No effect,Clear"
textline " "
endif
bitfld.long 0x04 21. " I53 ,Interrupt pending HDMIEVT" "No effect,Clear"
bitfld.long 0x04 20. " I52 ,Interrupt pending GPMCEVT" "No effect,Clear"
bitfld.long 0x04 19. " I51 ,Interrupt pending TINTEVT7" "No effect,Clear"
textline " "
bitfld.long 0x04 18. " I50 ,Interrupt pending TINTEVT6" "No effect,Clear"
bitfld.long 0x04 17. " I49 ,Interrupt pending TINTEVT5" "No effect,Clear"
bitfld.long 0x04 16. " I48 ,Interrupt pending TINTEVT4" "No effect,Clear"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
textline " "
bitfld.long 0x04 15. " I47 ,Interrupt pending CAN_IF3DMA" "No effect,Clear"
bitfld.long 0x04 13. " I45 ,Interrupt pending SPI1REVT1" "No effect,Clear"
bitfld.long 0x04 12. " I44 ,Interrupt pending SPI1XEVT1" "No effect,Clear"
textline " "
bitfld.long 0x04 11. " I43 ,Interrupt pending SPI1REVT0" "No effect,Clear"
bitfld.long 0x04 10. " I42 ,Interrupt pending SPI1XEVT0" "No effect,Clear"
bitfld.long 0x04 9. " I41 ,Interrupt pending CAN_IF2DMA" "No effect,Clear"
textline " "
bitfld.long 0x04 8. " I40 ,Interrupt pending CAN_IF1DMA" "No effect,Clear"
bitfld.long 0x04 7. " I39 ,Interrupt pending ISS_DMA_REQ4" "No effect,Clear"
bitfld.long 0x04 6. " I38 ,Interrupt pending ISS_DMA_REQ3" "No effect,Clear"
textline " "
bitfld.long 0x04 5. " I37 ,Interrupt pending ISS_DMA_REQ2" "No effect,Clear"
bitfld.long 0x04 4. " I36 ,Interrupt pending ISS_DMA_REQ1" "No effect,Clear"
endif
wgroup.long (0x2E00+0x78)++0x03
line.long 0x00 "IEVAL,Interrupt Evaluate Register"
bitfld.long 0x00 0. " EVAL ,Interrupt evaluate" "No effect,Evaluate"
tree.end
tree "QDMA Registers"
rgroup.long (0x2E00+0x80)++0x03
line.long 0x00 "QER,QDMA Event Register"
bitfld.long 0x00 7. " E7 ,QDMA event for channel 7" "No effect,Prioritized"
bitfld.long 0x00 6. " E6 ,QDMA event for channel 6" "No effect,Prioritized"
bitfld.long 0x00 5. " E5 ,QDMA event for channel 5" "No effect,Prioritized"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA event for channel 4" "No effect,Prioritized"
bitfld.long 0x00 3. " E3 ,QDMA event for channel 3" "No effect,Prioritized"
bitfld.long 0x00 2. " E2 ,QDMA event for channel 2" "No effect,Prioritized"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA event for channel 1" "No effect,Prioritized"
bitfld.long 0x00 0. " E0 ,QDMA event for channel 0" "No effect,Prioritized"
group.long (0x2E00+0x84)++0x03
line.long 0x00 "QEER,QDMA Event Enable Register"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " E7_set/clr ,QDMA event enable for channel 7" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " E6_set/clr ,QDMA event enable for channel 6" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " E5_set/clr ,QDMA event enable for channel 5" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " E4_set/clr ,QDMA event enable for channel 4" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " E3_set/clr ,QDMA event enable for channel 3" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " E2_set/clr ,QDMA event enable for channel 2" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " E1_set/clr ,QDMA event enable for channel 1" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " E0_set/clr ,QDMA event enable for channel 0" "Disabled,Enabled"
rgroup.long (0x2E00+0x90)++0x03
line.long 0x00 "QSER,QDMA Secondary Event Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event register for channel 7" "Not stored,Stored"
bitfld.long 0x00 6. " E6 ,QDMA secondary event register for channel 6" "Not stored,Stored"
bitfld.long 0x00 5. " E5 ,QDMA secondary event register for channel 5" "Not stored,Stored"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event register for channel 4" "Not stored,Stored"
bitfld.long 0x00 3. " E3 ,QDMA secondary event register for channel 3" "Not stored,Stored"
bitfld.long 0x00 2. " E2 ,QDMA secondary event register for channel 2" "Not stored,Stored"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event register for channel 1" "Not stored,Stored"
bitfld.long 0x00 0. " E0 ,QDMA secondary event register for channel 0" "Not stored,Stored"
wgroup.long (0x2E00+0x94)++0x03
line.long 0x00 "QSECR,QDMA Secondary Event Clear Register"
bitfld.long 0x00 7. " E7 ,QDMA secondary event clear register for channel7" "No effect,Clear"
bitfld.long 0x00 6. " E6 ,QDMA secondary event clear register for channel6" "No effect,Clear"
bitfld.long 0x00 5. " E5 ,QDMA secondary event clear register for channel5" "No effect,Clear"
textline " "
bitfld.long 0x00 4. " E4 ,QDMA secondary event clear register for channel4" "No effect,Clear"
bitfld.long 0x00 3. " E3 ,QDMA secondary event clear register for channel3" "No effect,Clear"
bitfld.long 0x00 2. " E2 ,QDMA secondary event clear register for channel2" "No effect,Clear"
textline " "
bitfld.long 0x00 1. " E1 ,QDMA secondary event clear register for channel1" "No effect,Clear"
bitfld.long 0x00 0. " E0 ,QDMA secondary event clear register for channel0" "No effect,Clear"
tree.end
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree.end
else
tree.end
endif
tree.end
; width 0xb
tree "PaRAM (EDMA3 Channel Parameter Description)"
base ad:0x49004000
width 9.
tree "Parameter set 0"
group.long 0x0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 1"
group.long 0x20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 2"
group.long 0x40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 3"
group.long 0x60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 4"
group.long 0x80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 5"
group.long 0xA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 6"
group.long 0xC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 7"
group.long 0xE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 8"
group.long 0x100++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x100+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x100+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x100+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 9"
group.long 0x120++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x120+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x120+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x120+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 10"
group.long 0x140++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x140+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x140+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x140+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 11"
group.long 0x160++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x160+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x160+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x160+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 12"
group.long 0x180++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x180+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x180+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x180+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 13"
group.long 0x1A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 14"
group.long 0x1C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 15"
group.long 0x1E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 16"
group.long 0x200++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x200+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x200+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x200+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 17"
group.long 0x220++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x220+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x220+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x220+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 18"
group.long 0x240++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x240+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x240+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x240+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 19"
group.long 0x260++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x260+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x260+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x260+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 20"
group.long 0x280++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x280+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x280+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x280+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 21"
group.long 0x2A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 22"
group.long 0x2C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 23"
group.long 0x2E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 24"
group.long 0x300++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x300+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x300+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x300+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 25"
group.long 0x320++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x320+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x320+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x320+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 26"
group.long 0x340++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x340+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x340+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x340+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 27"
group.long 0x360++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x360+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x360+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x360+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 28"
group.long 0x380++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x380+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x380+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x380+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 29"
group.long 0x3A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 30"
group.long 0x3C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 31"
group.long 0x3E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 32"
group.long 0x400++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x400+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x400+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x400+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 33"
group.long 0x420++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x420+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x420+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x420+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 34"
group.long 0x440++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x440+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x440+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x440+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 35"
group.long 0x460++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x460+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x460+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x460+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 36"
group.long 0x480++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x480+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x480+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x480+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 37"
group.long 0x4A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x4A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x4A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x4A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 38"
group.long 0x4C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x4C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x4C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x4C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 39"
group.long 0x4E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x4E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x4E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x4E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 40"
group.long 0x500++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x500+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x500+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x500+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 41"
group.long 0x520++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x520+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x520+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x520+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 42"
group.long 0x540++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x540+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x540+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x540+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 43"
group.long 0x560++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x560+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x560+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x560+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 44"
group.long 0x580++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x580+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x580+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x580+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 45"
group.long 0x5A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x5A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x5A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x5A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 46"
group.long 0x5C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x5C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x5C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x5C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 47"
group.long 0x5E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x5E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x5E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x5E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 48"
group.long 0x600++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x600+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x600+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x600+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 49"
group.long 0x620++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x620+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x620+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x620+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 50"
group.long 0x640++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x640+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x640+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x640+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 51"
group.long 0x660++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x660+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x660+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x660+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 52"
group.long 0x680++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x680+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x680+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x680+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 53"
group.long 0x6A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x6A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x6A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x6A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 54"
group.long 0x6C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x6C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x6C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x6C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 55"
group.long 0x6E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x6E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x6E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x6E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 56"
group.long 0x700++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x700+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x700+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x700+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 57"
group.long 0x720++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x720+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x720+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x720+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 58"
group.long 0x740++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x740+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x740+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x740+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 59"
group.long 0x760++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x760+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x760+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x760+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 60"
group.long 0x780++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x780+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x780+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x780+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 61"
group.long 0x7A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x7A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x7A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x7A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 62"
group.long 0x7C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x7C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x7C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x7C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 63"
group.long 0x7E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x7E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x7E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x7E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 64"
group.long 0x800++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x800+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x800+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x800+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 65"
group.long 0x820++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x820+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x820+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x820+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 66"
group.long 0x840++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x840+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x840+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x840+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 67"
group.long 0x860++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x860+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x860+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x860+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 68"
group.long 0x880++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x880+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x880+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x880+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 69"
group.long 0x8A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x8A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x8A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x8A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 70"
group.long 0x8C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x8C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x8C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x8C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 71"
group.long 0x8E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x8E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x8E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x8E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 72"
group.long 0x900++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x900+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x900+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x900+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 73"
group.long 0x920++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x920+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x920+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x920+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 74"
group.long 0x940++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x940+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x940+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x940+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 75"
group.long 0x960++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x960+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x960+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x960+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 76"
group.long 0x980++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x980+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x980+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x980+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 77"
group.long 0x9A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x9A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x9A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x9A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 78"
group.long 0x9C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x9C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x9C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x9C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 79"
group.long 0x9E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x9E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x9E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x9E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 80"
group.long 0xA00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 81"
group.long 0xA20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 82"
group.long 0xA40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 83"
group.long 0xA60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 84"
group.long 0xA80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xA80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xA80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xA80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 85"
group.long 0xAA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xAA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xAA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xAA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 86"
group.long 0xAC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xAC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xAC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xAC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 87"
group.long 0xAE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xAE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xAE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xAE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 88"
group.long 0xB00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xB00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xB00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xB00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 89"
group.long 0xB20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xB20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xB20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xB20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 90"
group.long 0xB40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xB40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xB40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xB40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 91"
group.long 0xB60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xB60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xB60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xB60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 92"
group.long 0xB80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xB80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xB80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xB80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 93"
group.long 0xBA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xBA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xBA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xBA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 94"
group.long 0xBC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xBC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xBC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xBC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 95"
group.long 0xBE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xBE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xBE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xBE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 96"
group.long 0xC00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 97"
group.long 0xC20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 98"
group.long 0xC40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 99"
group.long 0xC60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 100"
group.long 0xC80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xC80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xC80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xC80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 101"
group.long 0xCA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xCA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xCA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xCA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 102"
group.long 0xCC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xCC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xCC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xCC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 103"
group.long 0xCE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xCE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xCE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xCE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 104"
group.long 0xD00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xD00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xD00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xD00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 105"
group.long 0xD20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xD20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xD20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xD20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 106"
group.long 0xD40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xD40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xD40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xD40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 107"
group.long 0xD60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xD60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xD60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xD60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 108"
group.long 0xD80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xD80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xD80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xD80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 109"
group.long 0xDA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xDA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xDA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xDA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 110"
group.long 0xDC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xDC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xDC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xDC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 111"
group.long 0xDE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xDE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xDE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xDE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 112"
group.long 0xE00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 113"
group.long 0xE20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 114"
group.long 0xE40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 115"
group.long 0xE60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 116"
group.long 0xE80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xE80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xE80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xE80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 117"
group.long 0xEA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xEA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xEA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xEA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 118"
group.long 0xEC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xEC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xEC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xEC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 119"
group.long 0xEE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xEE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xEE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xEE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 120"
group.long 0xF00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xF00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xF00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xF00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 121"
group.long 0xF20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xF20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xF20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xF20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 122"
group.long 0xF40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xF40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xF40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xF40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 123"
group.long 0xF60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xF60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xF60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xF60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 124"
group.long 0xF80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xF80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xF80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xF80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 125"
group.long 0xFA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xFA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xFA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xFA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 126"
group.long 0xFC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xFC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xFC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xFC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 127"
group.long 0xFE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0xFE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0xFE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0xFE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 128"
group.long 0x1000++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1000+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1000+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1000+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 129"
group.long 0x1020++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1020+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1020+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1020+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 130"
group.long 0x1040++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1040+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1040+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1040+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 131"
group.long 0x1060++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1060+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1060+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1060+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 132"
group.long 0x1080++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1080+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1080+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1080+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 133"
group.long 0x10A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x10A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x10A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x10A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 134"
group.long 0x10C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x10C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x10C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x10C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 135"
group.long 0x10E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x10E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x10E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x10E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 136"
group.long 0x1100++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1100+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1100+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1100+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 137"
group.long 0x1120++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1120+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1120+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1120+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 138"
group.long 0x1140++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1140+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1140+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1140+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 139"
group.long 0x1160++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1160+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1160+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1160+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 140"
group.long 0x1180++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1180+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1180+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1180+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 141"
group.long 0x11A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x11A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x11A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x11A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 142"
group.long 0x11C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x11C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x11C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x11C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 143"
group.long 0x11E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x11E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x11E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x11E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 144"
group.long 0x1200++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1200+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1200+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1200+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 145"
group.long 0x1220++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1220+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1220+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1220+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 146"
group.long 0x1240++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1240+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1240+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1240+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 147"
group.long 0x1260++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1260+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1260+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1260+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 148"
group.long 0x1280++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1280+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1280+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1280+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 149"
group.long 0x12A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x12A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x12A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x12A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 150"
group.long 0x12C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x12C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x12C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x12C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 151"
group.long 0x12E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x12E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x12E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x12E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 152"
group.long 0x1300++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1300+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1300+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1300+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 153"
group.long 0x1320++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1320+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1320+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1320+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 154"
group.long 0x1340++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1340+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1340+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1340+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 155"
group.long 0x1360++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1360+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1360+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1360+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 156"
group.long 0x1380++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1380+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1380+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1380+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 157"
group.long 0x13A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x13A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x13A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x13A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 158"
group.long 0x13C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x13C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x13C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x13C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 159"
group.long 0x13E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x13E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x13E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x13E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 160"
group.long 0x1400++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1400+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1400+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1400+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 161"
group.long 0x1420++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1420+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1420+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1420+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 162"
group.long 0x1440++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1440+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1440+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1440+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 163"
group.long 0x1460++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1460+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1460+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1460+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 164"
group.long 0x1480++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1480+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1480+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1480+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 165"
group.long 0x14A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x14A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x14A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x14A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 166"
group.long 0x14C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x14C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x14C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x14C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 167"
group.long 0x14E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x14E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x14E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x14E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 168"
group.long 0x1500++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1500+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1500+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1500+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 169"
group.long 0x1520++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1520+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1520+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1520+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 170"
group.long 0x1540++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1540+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1540+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1540+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 171"
group.long 0x1560++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1560+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1560+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1560+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 172"
group.long 0x1580++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1580+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1580+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1580+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 173"
group.long 0x15A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x15A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x15A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x15A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 174"
group.long 0x15C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x15C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x15C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x15C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 175"
group.long 0x15E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x15E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x15E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x15E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 176"
group.long 0x1600++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1600+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1600+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1600+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 177"
group.long 0x1620++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1620+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1620+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1620+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 178"
group.long 0x1640++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1640+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1640+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1640+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 179"
group.long 0x1660++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1660+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1660+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1660+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 180"
group.long 0x1680++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1680+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1680+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1680+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 181"
group.long 0x16A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x16A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x16A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x16A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 182"
group.long 0x16C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x16C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x16C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x16C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 183"
group.long 0x16E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x16E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x16E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x16E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 184"
group.long 0x1700++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1700+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1700+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1700+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 185"
group.long 0x1720++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1720+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1720+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1720+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 186"
group.long 0x1740++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1740+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1740+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1740+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 187"
group.long 0x1760++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1760+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1760+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1760+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 188"
group.long 0x1780++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1780+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1780+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1780+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 189"
group.long 0x17A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x17A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x17A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x17A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 190"
group.long 0x17C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x17C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x17C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x17C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 191"
group.long 0x17E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x17E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x17E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x17E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 192"
group.long 0x1800++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1800+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1800+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1800+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 193"
group.long 0x1820++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1820+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1820+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1820+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 194"
group.long 0x1840++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1840+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1840+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1840+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 195"
group.long 0x1860++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1860+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1860+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1860+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 196"
group.long 0x1880++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1880+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1880+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1880+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 197"
group.long 0x18A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x18A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x18A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x18A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 198"
group.long 0x18C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x18C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x18C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x18C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 199"
group.long 0x18E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x18E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x18E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x18E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 200"
group.long 0x1900++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1900+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1900+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1900+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 201"
group.long 0x1920++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1920+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1920+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1920+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 202"
group.long 0x1940++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1940+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1940+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1940+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 203"
group.long 0x1960++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1960+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1960+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1960+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 204"
group.long 0x1980++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1980+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1980+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1980+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 205"
group.long 0x19A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x19A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x19A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x19A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 206"
group.long 0x19C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x19C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x19C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x19C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 207"
group.long 0x19E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x19E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x19E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x19E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 208"
group.long 0x1A00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 209"
group.long 0x1A20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 210"
group.long 0x1A40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 211"
group.long 0x1A60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 212"
group.long 0x1A80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1A80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1A80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1A80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 213"
group.long 0x1AA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1AA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1AA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1AA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 214"
group.long 0x1AC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1AC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1AC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1AC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 215"
group.long 0x1AE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1AE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1AE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1AE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 216"
group.long 0x1B00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1B00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1B00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1B00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 217"
group.long 0x1B20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1B20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1B20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1B20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 218"
group.long 0x1B40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1B40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1B40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1B40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 219"
group.long 0x1B60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1B60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1B60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1B60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 220"
group.long 0x1B80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1B80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1B80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1B80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 221"
group.long 0x1BA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1BA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1BA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1BA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 222"
group.long 0x1BC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1BC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1BC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1BC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 223"
group.long 0x1BE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1BE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1BE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1BE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 224"
group.long 0x1C00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 225"
group.long 0x1C20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 226"
group.long 0x1C40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 227"
group.long 0x1C60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 228"
group.long 0x1C80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1C80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1C80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1C80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 229"
group.long 0x1CA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1CA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1CA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1CA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 230"
group.long 0x1CC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1CC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1CC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1CC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 231"
group.long 0x1CE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1CE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1CE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1CE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 232"
group.long 0x1D00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1D00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1D00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1D00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 233"
group.long 0x1D20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1D20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1D20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1D20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 234"
group.long 0x1D40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1D40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1D40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1D40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 235"
group.long 0x1D60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1D60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1D60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1D60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 236"
group.long 0x1D80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1D80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1D80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1D80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 237"
group.long 0x1DA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1DA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1DA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1DA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 238"
group.long 0x1DC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1DC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1DC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1DC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 239"
group.long 0x1DE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1DE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1DE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1DE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 240"
group.long 0x1E00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 241"
group.long 0x1E20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 242"
group.long 0x1E40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 243"
group.long 0x1E60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 244"
group.long 0x1E80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1E80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1E80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1E80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 245"
group.long 0x1EA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1EA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1EA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1EA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 246"
group.long 0x1EC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1EC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1EC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1EC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 247"
group.long 0x1EE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1EE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1EE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1EE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 248"
group.long 0x1F00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1F00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1F00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1F00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 249"
group.long 0x1F20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1F20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1F20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1F20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 250"
group.long 0x1F40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1F40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1F40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1F40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 251"
group.long 0x1F60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1F60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1F60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1F60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 252"
group.long 0x1F80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1F80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1F80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1F80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 253"
group.long 0x1FA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1FA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1FA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1FA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 254"
group.long 0x1FC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1FC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1FC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1FC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 255"
group.long 0x1FE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x1FE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x1FE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x1FE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 256"
group.long 0x2000++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2000+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2000+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2000+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 257"
group.long 0x2020++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2020+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2020+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2020+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 258"
group.long 0x2040++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2040+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2040+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2040+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 259"
group.long 0x2060++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2060+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2060+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2060+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 260"
group.long 0x2080++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2080+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2080+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2080+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 261"
group.long 0x20A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x20A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x20A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x20A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 262"
group.long 0x20C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x20C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x20C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x20C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 263"
group.long 0x20E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x20E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x20E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x20E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 264"
group.long 0x2100++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2100+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2100+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2100+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 265"
group.long 0x2120++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2120+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2120+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2120+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 266"
group.long 0x2140++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2140+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2140+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2140+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 267"
group.long 0x2160++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2160+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2160+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2160+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 268"
group.long 0x2180++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2180+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2180+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2180+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 269"
group.long 0x21A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x21A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x21A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x21A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 270"
group.long 0x21C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x21C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x21C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x21C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 271"
group.long 0x21E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x21E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x21E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x21E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 272"
group.long 0x2200++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2200+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2200+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2200+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 273"
group.long 0x2220++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2220+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2220+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2220+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 274"
group.long 0x2240++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2240+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2240+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2240+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 275"
group.long 0x2260++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2260+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2260+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2260+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 276"
group.long 0x2280++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2280+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2280+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2280+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 277"
group.long 0x22A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x22A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x22A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x22A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 278"
group.long 0x22C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x22C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x22C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x22C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 279"
group.long 0x22E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x22E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x22E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x22E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 280"
group.long 0x2300++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2300+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2300+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2300+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 281"
group.long 0x2320++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2320+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2320+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2320+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 282"
group.long 0x2340++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2340+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2340+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2340+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 283"
group.long 0x2360++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2360+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2360+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2360+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 284"
group.long 0x2380++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2380+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2380+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2380+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 285"
group.long 0x23A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x23A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x23A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x23A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 286"
group.long 0x23C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x23C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x23C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x23C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 287"
group.long 0x23E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x23E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x23E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x23E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 288"
group.long 0x2400++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2400+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2400+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2400+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 289"
group.long 0x2420++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2420+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2420+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2420+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 290"
group.long 0x2440++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2440+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2440+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2440+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 291"
group.long 0x2460++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2460+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2460+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2460+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 292"
group.long 0x2480++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2480+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2480+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2480+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 293"
group.long 0x24A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x24A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x24A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x24A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 294"
group.long 0x24C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x24C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x24C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x24C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 295"
group.long 0x24E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x24E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x24E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x24E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 296"
group.long 0x2500++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2500+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2500+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2500+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 297"
group.long 0x2520++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2520+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2520+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2520+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 298"
group.long 0x2540++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2540+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2540+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2540+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 299"
group.long 0x2560++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2560+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2560+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2560+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 300"
group.long 0x2580++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2580+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2580+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2580+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 301"
group.long 0x25A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x25A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x25A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x25A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 302"
group.long 0x25C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x25C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x25C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x25C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 303"
group.long 0x25E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x25E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x25E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x25E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 304"
group.long 0x2600++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2600+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2600+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2600+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 305"
group.long 0x2620++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2620+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2620+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2620+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 306"
group.long 0x2640++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2640+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2640+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2640+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 307"
group.long 0x2660++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2660+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2660+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2660+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 308"
group.long 0x2680++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2680+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2680+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2680+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 309"
group.long 0x26A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x26A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x26A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x26A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 310"
group.long 0x26C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x26C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x26C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x26C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 311"
group.long 0x26E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x26E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x26E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x26E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 312"
group.long 0x2700++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2700+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2700+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2700+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 313"
group.long 0x2720++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2720+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2720+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2720+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 314"
group.long 0x2740++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2740+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2740+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2740+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 315"
group.long 0x2760++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2760+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2760+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2760+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 316"
group.long 0x2780++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2780+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2780+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2780+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 317"
group.long 0x27A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x27A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x27A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x27A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 318"
group.long 0x27C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x27C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x27C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x27C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 319"
group.long 0x27E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x27E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x27E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x27E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 320"
group.long 0x2800++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2800+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2800+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2800+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 321"
group.long 0x2820++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2820+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2820+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2820+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 322"
group.long 0x2840++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2840+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2840+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2840+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 323"
group.long 0x2860++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2860+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2860+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2860+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 324"
group.long 0x2880++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2880+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2880+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2880+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 325"
group.long 0x28A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x28A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x28A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x28A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 326"
group.long 0x28C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x28C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x28C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x28C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 327"
group.long 0x28E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x28E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x28E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x28E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 328"
group.long 0x2900++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2900+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2900+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2900+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 329"
group.long 0x2920++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2920+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2920+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2920+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 330"
group.long 0x2940++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2940+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2940+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2940+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 331"
group.long 0x2960++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2960+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2960+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2960+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 332"
group.long 0x2980++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2980+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2980+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2980+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 333"
group.long 0x29A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x29A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x29A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x29A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 334"
group.long 0x29C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x29C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x29C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x29C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 335"
group.long 0x29E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x29E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x29E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x29E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 336"
group.long 0x2A00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 337"
group.long 0x2A20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 338"
group.long 0x2A40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 339"
group.long 0x2A60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 340"
group.long 0x2A80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2A80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2A80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2A80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 341"
group.long 0x2AA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2AA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2AA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2AA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 342"
group.long 0x2AC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2AC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2AC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2AC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 343"
group.long 0x2AE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2AE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2AE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2AE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 344"
group.long 0x2B00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2B00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2B00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2B00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 345"
group.long 0x2B20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2B20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2B20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2B20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 346"
group.long 0x2B40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2B40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2B40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2B40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 347"
group.long 0x2B60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2B60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2B60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2B60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 348"
group.long 0x2B80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2B80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2B80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2B80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 349"
group.long 0x2BA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2BA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2BA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2BA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 350"
group.long 0x2BC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2BC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2BC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2BC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 351"
group.long 0x2BE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2BE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2BE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2BE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 352"
group.long 0x2C00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 353"
group.long 0x2C20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 354"
group.long 0x2C40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 355"
group.long 0x2C60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 356"
group.long 0x2C80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2C80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2C80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2C80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 357"
group.long 0x2CA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2CA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2CA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2CA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 358"
group.long 0x2CC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2CC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2CC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2CC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 359"
group.long 0x2CE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2CE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2CE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2CE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 360"
group.long 0x2D00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2D00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2D00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2D00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 361"
group.long 0x2D20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2D20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2D20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2D20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 362"
group.long 0x2D40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2D40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2D40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2D40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 363"
group.long 0x2D60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2D60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2D60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2D60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 364"
group.long 0x2D80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2D80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2D80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2D80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 365"
group.long 0x2DA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2DA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2DA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2DA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 366"
group.long 0x2DC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2DC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2DC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2DC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 367"
group.long 0x2DE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2DE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2DE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2DE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 368"
group.long 0x2E00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 369"
group.long 0x2E20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 370"
group.long 0x2E40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 371"
group.long 0x2E60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 372"
group.long 0x2E80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2E80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2E80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2E80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 373"
group.long 0x2EA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2EA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2EA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2EA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 374"
group.long 0x2EC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2EC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2EC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2EC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 375"
group.long 0x2EE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2EE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2EE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2EE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 376"
group.long 0x2F00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2F00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2F00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2F00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 377"
group.long 0x2F20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2F20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2F20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2F20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 378"
group.long 0x2F40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2F40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2F40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2F40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 379"
group.long 0x2F60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2F60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2F60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2F60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 380"
group.long 0x2F80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2F80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2F80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2F80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 381"
group.long 0x2FA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2FA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2FA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2FA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 382"
group.long 0x2FC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2FC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2FC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2FC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 383"
group.long 0x2FE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x2FE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x2FE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x2FE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 384"
group.long 0x3000++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3000+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3000+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3000+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 385"
group.long 0x3020++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3020+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3020+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3020+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 386"
group.long 0x3040++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3040+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3040+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3040+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 387"
group.long 0x3060++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3060+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3060+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3060+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 388"
group.long 0x3080++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3080+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3080+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3080+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 389"
group.long 0x30A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x30A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x30A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x30A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 390"
group.long 0x30C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x30C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x30C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x30C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 391"
group.long 0x30E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x30E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x30E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x30E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 392"
group.long 0x3100++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3100+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3100+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3100+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 393"
group.long 0x3120++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3120+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3120+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3120+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 394"
group.long 0x3140++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3140+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3140+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3140+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 395"
group.long 0x3160++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3160+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3160+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3160+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 396"
group.long 0x3180++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3180+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3180+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3180+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 397"
group.long 0x31A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x31A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x31A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x31A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 398"
group.long 0x31C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x31C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x31C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x31C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 399"
group.long 0x31E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x31E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x31E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x31E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 400"
group.long 0x3200++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3200+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3200+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3200+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 401"
group.long 0x3220++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3220+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3220+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3220+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 402"
group.long 0x3240++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3240+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3240+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3240+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 403"
group.long 0x3260++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3260+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3260+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3260+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 404"
group.long 0x3280++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3280+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3280+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3280+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 405"
group.long 0x32A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x32A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x32A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x32A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 406"
group.long 0x32C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x32C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x32C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x32C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 407"
group.long 0x32E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x32E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x32E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x32E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 408"
group.long 0x3300++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3300+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3300+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3300+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 409"
group.long 0x3320++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3320+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3320+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3320+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 410"
group.long 0x3340++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3340+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3340+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3340+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 411"
group.long 0x3360++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3360+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3360+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3360+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 412"
group.long 0x3380++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3380+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3380+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3380+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 413"
group.long 0x33A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x33A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x33A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x33A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 414"
group.long 0x33C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x33C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x33C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x33C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 415"
group.long 0x33E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x33E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x33E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x33E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 416"
group.long 0x3400++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3400+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3400+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3400+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 417"
group.long 0x3420++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3420+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3420+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3420+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 418"
group.long 0x3440++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3440+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3440+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3440+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 419"
group.long 0x3460++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3460+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3460+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3460+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 420"
group.long 0x3480++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3480+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3480+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3480+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 421"
group.long 0x34A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x34A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x34A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x34A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 422"
group.long 0x34C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x34C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x34C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x34C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 423"
group.long 0x34E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x34E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x34E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x34E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 424"
group.long 0x3500++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3500+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3500+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3500+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 425"
group.long 0x3520++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3520+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3520+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3520+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 426"
group.long 0x3540++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3540+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3540+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3540+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 427"
group.long 0x3560++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3560+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3560+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3560+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 428"
group.long 0x3580++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3580+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3580+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3580+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 429"
group.long 0x35A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x35A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x35A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x35A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 430"
group.long 0x35C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x35C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x35C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x35C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 431"
group.long 0x35E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x35E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x35E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x35E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 432"
group.long 0x3600++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3600+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3600+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3600+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 433"
group.long 0x3620++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3620+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3620+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3620+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 434"
group.long 0x3640++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3640+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3640+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3640+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 435"
group.long 0x3660++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3660+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3660+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3660+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 436"
group.long 0x3680++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3680+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3680+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3680+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 437"
group.long 0x36A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x36A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x36A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x36A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 438"
group.long 0x36C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x36C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x36C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x36C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 439"
group.long 0x36E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x36E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x36E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x36E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 440"
group.long 0x3700++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3700+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3700+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3700+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 441"
group.long 0x3720++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3720+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3720+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3720+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 442"
group.long 0x3740++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3740+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3740+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3740+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 443"
group.long 0x3760++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3760+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3760+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3760+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 444"
group.long 0x3780++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3780+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3780+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3780+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 445"
group.long 0x37A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x37A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x37A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x37A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 446"
group.long 0x37C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x37C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x37C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x37C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 447"
group.long 0x37E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x37E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x37E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x37E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 448"
group.long 0x3800++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3800+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3800+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3800+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 449"
group.long 0x3820++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3820+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3820+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3820+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 450"
group.long 0x3840++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3840+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3840+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3840+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 451"
group.long 0x3860++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3860+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3860+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3860+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 452"
group.long 0x3880++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3880+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3880+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3880+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 453"
group.long 0x38A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x38A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x38A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x38A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 454"
group.long 0x38C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x38C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x38C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x38C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 455"
group.long 0x38E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x38E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x38E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x38E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 456"
group.long 0x3900++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3900+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3900+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3900+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 457"
group.long 0x3920++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3920+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3920+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3920+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 458"
group.long 0x3940++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3940+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3940+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3940+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 459"
group.long 0x3960++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3960+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3960+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3960+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 460"
group.long 0x3980++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3980+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3980+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3980+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 461"
group.long 0x39A0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x39A0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x39A0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x39A0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 462"
group.long 0x39C0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x39C0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x39C0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x39C0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 463"
group.long 0x39E0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x39E0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x39E0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x39E0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 464"
group.long 0x3A00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 465"
group.long 0x3A20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 466"
group.long 0x3A40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 467"
group.long 0x3A60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 468"
group.long 0x3A80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3A80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3A80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3A80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 469"
group.long 0x3AA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3AA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3AA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3AA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 470"
group.long 0x3AC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3AC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3AC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3AC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 471"
group.long 0x3AE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3AE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3AE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3AE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 472"
group.long 0x3B00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3B00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3B00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3B00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 473"
group.long 0x3B20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3B20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3B20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3B20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 474"
group.long 0x3B40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3B40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3B40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3B40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 475"
group.long 0x3B60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3B60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3B60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3B60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 476"
group.long 0x3B80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3B80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3B80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3B80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 477"
group.long 0x3BA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3BA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3BA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3BA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 478"
group.long 0x3BC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3BC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3BC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3BC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 479"
group.long 0x3BE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3BE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3BE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3BE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 480"
group.long 0x3C00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 481"
group.long 0x3C20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 482"
group.long 0x3C40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 483"
group.long 0x3C60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 484"
group.long 0x3C80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3C80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3C80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3C80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 485"
group.long 0x3CA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3CA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3CA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3CA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 486"
group.long 0x3CC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3CC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3CC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3CC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 487"
group.long 0x3CE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3CE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3CE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3CE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 488"
group.long 0x3D00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3D00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3D00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3D00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 489"
group.long 0x3D20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3D20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3D20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3D20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 490"
group.long 0x3D40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3D40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3D40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3D40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 491"
group.long 0x3D60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3D60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3D60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3D60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 492"
group.long 0x3D80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3D80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3D80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3D80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 493"
group.long 0x3DA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3DA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3DA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3DA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 494"
group.long 0x3DC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3DC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3DC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3DC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 495"
group.long 0x3DE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3DE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3DE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3DE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 496"
group.long 0x3E00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 497"
group.long 0x3E20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 498"
group.long 0x3E40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 499"
group.long 0x3E60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 500"
group.long 0x3E80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3E80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3E80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3E80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 501"
group.long 0x3EA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3EA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3EA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3EA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 502"
group.long 0x3EC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3EC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3EC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3EC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 503"
group.long 0x3EE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3EE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3EE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3EE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 504"
group.long 0x3F00++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3F00+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3F00+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3F00+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 505"
group.long 0x3F20++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3F20+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3F20+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3F20+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 506"
group.long 0x3F40++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3F40+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3F40+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3F40+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 507"
group.long 0x3F60++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3F60+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3F60+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3F60+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 508"
group.long 0x3F80++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3F80+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3F80+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3F80+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 509"
group.long 0x3FA0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3FA0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3FA0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3FA0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 510"
group.long 0x3FC0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3FC0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3FC0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3FC0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
tree "Parameter set 511"
group.long 0x3FE0++0x07
line.long 0x00 "OPT,Channel Options"
bitfld.long 0x00 31. " PRIV ,Privilege level" "User level,Supervisor level"
bitfld.long 0x00 24.--27. " PRIVID ,Privilege identification for the external host/CPU/DMA that programmed this PaRAM set" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 23. " ITCCHEN ,Intermediate transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 21. " ITCINTEN ,Intermediate transfer completion interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 11. " TCCMODE ,Transfer complete code mode" "Normal completion,Early completion"
bitfld.long 0x00 8.--10. " FWID ,FIFO Width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
textline " "
bitfld.long 0x00 3. " STATIC ,Static set" "Not static,Static"
bitfld.long 0x00 2. " SYNCDIM ,Transfer synchronization dimension" "A-synchronized,AB-synchronized"
textline " "
bitfld.long 0x00 1. " DAM ,Destination address mode" "INCR,CONST"
bitfld.long 0x00 0. " SAM ,Source address mode" "INCR,CONST"
line.long 0x04 "SRC,Channel Source Address"
group.word (0x3FE0+0x08)++0x03
line.word 0x00 "ACNT,Count for 1st Dimension"
line.word 0x02 "BCNT,Count for 2nd Dimension"
group.long (0x3FE0+0x0C)++0x03
line.long 0x00 "DST,Channel Destination Address"
group.word (0x3FE0+0x10)++0x0D
line.word 0x00 "SRCBIDX,Source BCNT Index"
line.word 0x02 "DSTBIDX,Destination BCNT Index"
line.word 0x04 "LINK,Link Address"
line.word 0x06 "BCNTRLD,BCNT Reload"
line.word 0x08 "SRCCIDX,Source CCNT Index"
line.word 0x0A "DSTCIDX,Destination CCNT index"
line.word 0x0C "CCNT,Count for 3rd Dimension"
tree.end
width 0xB
tree.end
tree.end
tree "EDMA3TC (EDMA3 Transfer Controller Control Registers)"
tree "TPTC0"
base ad:0x49800000
width 12.
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral Identification Register"
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
rgroup.long 0x100++0x3
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pended,Pended"
textline " "
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle & available,Busy"
group.long 0x120++0x03
line.long 0x00 "ERRSTAT,Error Register"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR_set/clr ,MMR address error" "No error,Error"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR_set/clr ,Transfer request (TR) error event" "No error,Error"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR_set/clr ,Bus error event" "No error,Error"
rgroup.long 0x12C++0x03
line.long 0x00 "ERRDET,Error Details Register"
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
wgroup.long 0x130++0x03
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Evaluate"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Issued,4 cycles,8 cycles,16 cycles,32 cycles,?..."
group.long 0x240++0x03
line.long 0x00 "SAOPT,Source Active Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
rgroup.long 0x244++0x07
line.long 0x00 "SADDR,Source Active Source Address Register"
line.long 0x04 "SACNT,Source Active Count Register"
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
hgroup.long 0x24C++0x03
hide.long 0x00 "SADST,Source Active Destination Address Register"
rgroup.long 0x250++0x0F
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
bitfld.long 0x04 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
line.long 0x0C "SASRCBREF,Source Active Source Address B-Reference Register"
hgroup.long 0x260++0x03
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
group.long 0x300++0x03
line.long 0x00 "DFOPT0,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x300+0x04)++0x03
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register"
rgroup.long (0x300+0x08)++0x0F
line.long 0x00 "DFCNT0,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX0,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x03
line.long 0x00 "DFOPT1,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x340+0x04)++0x03
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register"
rgroup.long (0x340+0x08)++0x0F
line.long 0x00 "DFCNT1,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX1,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x380++0x03
line.long 0x00 "DFOPT2,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x380+0x04)++0x03
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register"
rgroup.long (0x380+0x08)++0x0F
line.long 0x00 "DFCNT2,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX2,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C0++0x03
line.long 0x00 "DFOPT3,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x3C0+0x04)++0x03
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register"
rgroup.long (0x3C0+0x08)++0x0F
line.long 0x00 "DFCNT3,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX3,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x280++0x03
line.long 0x00 "DFCRNTRLD,Destination FIFO Count Reload Register"
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
hgroup.long 0x284++0x03
hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
rgroup.long 0x288++0x03
line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
else
hgroup.long 0x288++0x03
hide.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
endif
width 0xb
tree.end
tree "TPTC1"
base ad:0x49900000
width 12.
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral Identification Register"
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
rgroup.long 0x100++0x3
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pended,Pended"
textline " "
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle & available,Busy"
group.long 0x120++0x03
line.long 0x00 "ERRSTAT,Error Register"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR_set/clr ,MMR address error" "No error,Error"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR_set/clr ,Transfer request (TR) error event" "No error,Error"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR_set/clr ,Bus error event" "No error,Error"
rgroup.long 0x12C++0x03
line.long 0x00 "ERRDET,Error Details Register"
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
wgroup.long 0x130++0x03
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Evaluate"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Issued,4 cycles,8 cycles,16 cycles,32 cycles,?..."
group.long 0x240++0x03
line.long 0x00 "SAOPT,Source Active Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
rgroup.long 0x244++0x07
line.long 0x00 "SADDR,Source Active Source Address Register"
line.long 0x04 "SACNT,Source Active Count Register"
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
hgroup.long 0x24C++0x03
hide.long 0x00 "SADST,Source Active Destination Address Register"
rgroup.long 0x250++0x0F
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
bitfld.long 0x04 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
line.long 0x0C "SASRCBREF,Source Active Source Address B-Reference Register"
hgroup.long 0x260++0x03
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
group.long 0x300++0x03
line.long 0x00 "DFOPT0,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x300+0x04)++0x03
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register"
rgroup.long (0x300+0x08)++0x0F
line.long 0x00 "DFCNT0,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX0,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x03
line.long 0x00 "DFOPT1,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x340+0x04)++0x03
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register"
rgroup.long (0x340+0x08)++0x0F
line.long 0x00 "DFCNT1,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX1,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x380++0x03
line.long 0x00 "DFOPT2,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x380+0x04)++0x03
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register"
rgroup.long (0x380+0x08)++0x0F
line.long 0x00 "DFCNT2,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX2,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C0++0x03
line.long 0x00 "DFOPT3,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x3C0+0x04)++0x03
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register"
rgroup.long (0x3C0+0x08)++0x0F
line.long 0x00 "DFCNT3,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX3,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x280++0x03
line.long 0x00 "DFCRNTRLD,Destination FIFO Count Reload Register"
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
hgroup.long 0x284++0x03
hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
rgroup.long 0x288++0x03
line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
else
hgroup.long 0x288++0x03
hide.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
endif
width 0xb
tree.end
tree "TPTC2"
base ad:0x49A00000
width 12.
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral Identification Register"
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
rgroup.long 0x100++0x3
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pended,Pended"
textline " "
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle & available,Busy"
group.long 0x120++0x03
line.long 0x00 "ERRSTAT,Error Register"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR_set/clr ,MMR address error" "No error,Error"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR_set/clr ,Transfer request (TR) error event" "No error,Error"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR_set/clr ,Bus error event" "No error,Error"
rgroup.long 0x12C++0x03
line.long 0x00 "ERRDET,Error Details Register"
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
wgroup.long 0x130++0x03
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Evaluate"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Issued,4 cycles,8 cycles,16 cycles,32 cycles,?..."
group.long 0x240++0x03
line.long 0x00 "SAOPT,Source Active Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
rgroup.long 0x244++0x07
line.long 0x00 "SADDR,Source Active Source Address Register"
line.long 0x04 "SACNT,Source Active Count Register"
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
hgroup.long 0x24C++0x03
hide.long 0x00 "SADST,Source Active Destination Address Register"
rgroup.long 0x250++0x0F
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
bitfld.long 0x04 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
line.long 0x0C "SASRCBREF,Source Active Source Address B-Reference Register"
hgroup.long 0x260++0x03
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
group.long 0x300++0x03
line.long 0x00 "DFOPT0,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x300+0x04)++0x03
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register"
rgroup.long (0x300+0x08)++0x0F
line.long 0x00 "DFCNT0,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX0,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x03
line.long 0x00 "DFOPT1,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x340+0x04)++0x03
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register"
rgroup.long (0x340+0x08)++0x0F
line.long 0x00 "DFCNT1,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX1,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x380++0x03
line.long 0x00 "DFOPT2,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x380+0x04)++0x03
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register"
rgroup.long (0x380+0x08)++0x0F
line.long 0x00 "DFCNT2,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX2,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C0++0x03
line.long 0x00 "DFOPT3,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x3C0+0x04)++0x03
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register"
rgroup.long (0x3C0+0x08)++0x0F
line.long 0x00 "DFCNT3,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX3,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x280++0x03
line.long 0x00 "DFCRNTRLD,Destination FIFO Count Reload Register"
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
hgroup.long 0x284++0x03
hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
rgroup.long 0x288++0x03
line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
else
hgroup.long 0x288++0x03
hide.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
endif
width 0xb
tree.end
tree "TPTC3"
base ad:0x49B00000
width 12.
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral Identification Register"
line.long 0x04 "TCCFG,EDMA3TC Configuration Register"
bitfld.long 0x04 8.--9. " DREGDEPTH ,Destination register FIFO depth parameterization" "Reserved,Reserved,4 entry,?..."
bitfld.long 0x04 4.--5. " BUSWIDTH ,Bus width parameterization" "Reserved,Reserved,128-bit,?..."
bitfld.long 0x04 0.--2. " FIFOSIZE ,FIFO size" "Reserved,Reserved,Reserved,Reserved,Reserved,1024 byte,?..."
rgroup.long 0x100++0x3
line.long 0x00 "TCSTAT,EDMA3TC Channel Status Register"
bitfld.long 0x00 12.--13. " DFSTRTPTR ,Destination FIFO start pointer" "0,1,2,3"
bitfld.long 0x00 4.--6. " DSTACTV ,Destination active state" "Empty,1 TR,2 TRs,3 TRs,4 TRs,?..."
bitfld.long 0x00 2. " WSACTV ,Write status active" "Not pended,Pended"
textline " "
bitfld.long 0x00 1. " SRCACTV ,Source active state" "Idle,Busy"
bitfld.long 0x00 0. " PROGBUSY ,Program register set busy" "Idle & available,Busy"
group.long 0x120++0x03
line.long 0x00 "ERRSTAT,Error Register"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " MMRAERR_set/clr ,MMR address error" "No error,Error"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " TRERR_set/clr ,Transfer request (TR) error event" "No error,Error"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " BUSERR_set/clr ,Bus error event" "No error,Error"
rgroup.long 0x12C++0x03
line.long 0x00 "ERRDET,Error Details Register"
bitfld.long 0x00 17. " TCCHEN ,Transfer completion chaining enable" "Disabled,Enabled"
bitfld.long 0x00 16. " TCINTEN ,Transfer completion interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--13. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 0.--3. " STAT ,Transaction status" "No error,Read error,Read error,Read error,Read error,Read error,Read error,Read error,Write error,Write error,Write error,Write error,Write error,Write error,Write error,Write error"
wgroup.long 0x130++0x03
line.long 0x00 "ERRCMD,Error Interrupt Command Register"
bitfld.long 0x00 0. " EVAL ,Error evaluate" "No effect,Evaluate"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. " RDRATE ,Read rate" "Issued,4 cycles,8 cycles,16 cycles,32 cycles,?..."
group.long 0x240++0x03
line.long 0x00 "SAOPT,Source Active Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
rgroup.long 0x244++0x07
line.long 0x00 "SADDR,Source Active Source Address Register"
line.long 0x04 "SACNT,Source Active Count Register"
hexmask.long.word 0x04 16.--31. 1. " BCNT ,B dimension count"
hexmask.long.word 0x04 0.--15. 1. " ACNT ,A dimension count"
hgroup.long 0x24C++0x03
hide.long 0x00 "SADST,Source Active Destination Address Register"
rgroup.long 0x250++0x0F
line.long 0x00 "SABIDX,Source Active Source B-Dimension Index Register"
hexmask.long.word 0x00 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
hexmask.long.word 0x00 0.--15. 1. " SBIDX ,B-Index offset between source arrays"
line.long 0x04 "SAMPPRXY,Source Active Memory Protection Proxy Register"
bitfld.long 0x04 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x04 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "SACNTRLD,Source Active Count Reload Register"
hexmask.long.word 0x08 0.--15. 1. " ACNTRLD ,A-count reload value"
line.long 0x0C "SASRCBREF,Source Active Source Address B-Reference Register"
hgroup.long 0x260++0x03
hide.long 0x00 "SADSTBREF,Source Active Destination Address B-Reference Register"
group.long 0x300++0x03
line.long 0x00 "DFOPT0,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x300+0x04)++0x03
hide.long 0x00 "DFSRC0,Destination FIFO Source Address Register"
rgroup.long (0x300+0x08)++0x0F
line.long 0x00 "DFCNT0,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST0,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX0,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY0,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x340++0x03
line.long 0x00 "DFOPT1,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x340+0x04)++0x03
hide.long 0x00 "DFSRC1,Destination FIFO Source Address Register"
rgroup.long (0x340+0x08)++0x0F
line.long 0x00 "DFCNT1,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST1,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX1,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY1,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x380++0x03
line.long 0x00 "DFOPT2,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x380+0x04)++0x03
hide.long 0x00 "DFSRC2,Destination FIFO Source Address Register"
rgroup.long (0x380+0x08)++0x0F
line.long 0x00 "DFCNT2,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST2,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX2,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY2,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x3C0++0x03
line.long 0x00 "DFOPT3,Destination FIFO Options Register"
bitfld.long 0x00 22. " TCCHEN ,Transfer complete chaining enable" "Disabled,Enabled"
bitfld.long 0x00 20. " TCINTEN ,Transfer complete interrupt enable" "Disabled,Enabled"
hexmask.long.byte 0x00 12.--17. 1. " TCC ,Transfer complete code"
textline " "
bitfld.long 0x00 8.--10. " FWID ,FIFO width" "8-bit,16-bit,32-bit,64-bit,128-bit,256-bit,?..."
bitfld.long 0x00 4.--6. " PRI ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x00 1. " DAM ,Destination address mode within an array" "INCR,CONST"
textline " "
bitfld.long 0x00 0. " SAM ,Source address mode within an array" "INCR,CONST"
hgroup.long (0x3C0+0x04)++0x03
hide.long 0x00 "DFSRC3,Destination FIFO Source Address Register"
rgroup.long (0x3C0+0x08)++0x0F
line.long 0x00 "DFCNT3,Destination FIFO Count Register"
hexmask.long.word 0x00 16.--31. 1. " BCNT ,B-dimension count"
hexmask.long.word 0x00 0.--15. 1. " ACNT ,A-dimension count"
line.long 0x04 "DFDST3,Destination FIFO Destination Address Register"
line.long 0x08 "DFBIDX3,Destination FIFO B-Index Register"
hexmask.long.word 0x08 16.--31. 1. " DBIDX ,B-Index offset between destination arrays"
line.long 0x0C "DFMPPRXY3,Destination FIFO Memory Protection Proxy Register"
bitfld.long 0x0C 8. " PRIV ,Privilege level" "User-level,Supervisor-level"
bitfld.long 0x0C 0.--3. " PRIVID ,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x280++0x03
line.long 0x00 "DFCRNTRLD,Destination FIFO Count Reload Register"
hexmask.long.word 0x00 0.--15. 1. " ACNTRLD ,A-count reload value"
hgroup.long 0x284++0x03
hide.long 0x00 "DFSRCBREF,Destination FIFO Set Destination Address B Reference Register"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
rgroup.long 0x288++0x03
line.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
else
hgroup.long 0x288++0x03
hide.long 0x00 "DFDSTBREF,Destination FIFO Set Destination Address B Reference Register"
endif
width 0xb
tree.end
tree.end
tree.end
tree.open "EMAC (Ethernet Media Access Controller)"
tree "EMAC 0"
tree "EMAC Control Module Registers"
base ad:0x4a100900
width 19.
rgroup.long 0x00++0x03
line.long 0x00 "CMIDVER,EMAC Control Module Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " CPGMACSS_S_IDENT ,CPGMACSS_S Identification Value"
bitfld.long 0x00 11.--15. " CPGMACSS_S_RTL_VER ,CPGMACSS_S RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--10. " CPGMACSS_S_MAJ_VER ,CPGMACSS_S Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. " CPGMACSS_S_MINOR_VER ,CPGMACSS_S Minor Version Value"
group.long 0x04++0x07
line.long 0x00 "SOFTRESET,EMAC Control Module Software Reset Register"
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
line.long 0x04 "CMEMCONTROL,EMAC Control Module Emulation Control Register"
bitfld.long 0x04 1. " SOFT ,Emulation Soft Mode" "Disabled,Enabled"
bitfld.long 0x04 0. " FREE ,Emulation Free Mode" "Disabled,Enabled"
group.long 0x0c++0x03
line.long 0x00 "CMINTCTRL,EMAC Control Module Interrupt Control Register"
bitfld.long 0x00 31. " INTTEST ,Interrupt Test" "Disabled,Enabled"
bitfld.long 0x00 21. " C2_TX ,C2_Tx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " C2_RX ,C2_Rx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 19. " C1_TX ,C1_Tx_Pulse Pacing Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " C1_RX ,C1_Rx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " C0_TX ,C0_Tx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " C0_RX ,C0_Rx_Pulse Pacing Enable" "Disabled,Enabled"
hexmask.long.word 0x00 0.--11. 1. " INTPRESCALE ,Interrupt Counter Prescaler"
group.long 0x10++0x0f
line.long 0x00 "CMRXTHRESHINTEN,EMAC Control Module Receive Threshold Interrupt Enable Register"
bitfld.long 0x00 7. " C0_RX_THRESH_7_EN ,Core 0 Receive Threshold Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " C0_RX_THRESH_6_EN ,Core 0 Receive Threshold Interrupt 6 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " C0_RX_THRESH_5_EN ,Core 0 Receive Threshold Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " C0_RX_THRESH_4_EN ,Core 0 Receive Threshold Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " C0_RX_THRESH_3_EN ,Core 0 Receive Threshold Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " C0_RX_THRESH_2_EN ,Core 0 Receive Threshold Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " C0_RX_THRESH_1_EN ,Core 0 Receive Threshold Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " C0_RX_THRESH_0_EN ,Core 0 Receive Threshold Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x04 "CMRXINTEN,EMAC Control Module Receive Interrupt Enable Register"
bitfld.long 0x04 7. " C_RX_7_EN ,Core 0 Receive Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " C_RX_6_EN ,Core 0 Receive Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " C_RX_5_EN ,Core 0 Receive Interrupt 5 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " C_RX_4_EN ,Core 0 Receive Interrupt 4 Enable" "Disabled,Enabled"
bitfld.long 0x04 3. " C_RX_3_EN ,Core 0 Receive Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " C_RX_2_EN ,Core 0 Receive Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " C_RX_1_EN ,Core 0 Receive Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " C_RX_0_EN ,Core 0 Receive Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x08 "CMTXINTEN,EMAC Control Module Transmit Interrupt Enable Register"
bitfld.long 0x08 7. " C_TX_7_EN ,Core 0 Transmit Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x08 6. " C_TX_6_EN ,Core 0 Transmit Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x08 5. " C_TX_5_EN ,Core 0 Transmit Interrupt 5 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 4. " C_TX_4_EN ,Core 0 Transmit Interrupt 4 Enable" "Disabled,Enabled"
bitfld.long 0x08 3. " C_TX_3_EN ,Core 0 Transmit Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x08 2. " C_TX_2_EN ,Core 0 Transmit Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " C_TX_1_EN ,Core 0 Transmit Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " C_TX_0_EN ,Core 0 Transmit Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x0c "CMMISCINTEN,EMAC Control Module Miscellaneous Interrupt Enable Register"
bitfld.long 0x0C 3. " STAT_PEND_EN ,Core 0 Miscellaneous Interrupt (STAT_PEND) Enable" "Disabled,Enabled"
bitfld.long 0x0C 2. " HOST_PEND_EN ,Core 0 Miscellaneous Interrupt (HOST_PEND) Enable" "Disabled,Enabled"
bitfld.long 0x0C 1. " MDIO_LINKINT_EN ,Core 0 Miscellaneous Interrupt (MDIO_LINKINT) Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 0. " MDIO_USERINT_EN ,ECore 0 Miscellaneous Interrupt (MDIO_USERINT) Enable" "Disabled,Enabled"
rgroup.long 0x40++0x0f
line.long 0x00 "CMRXTHRESHINTSTAT,EMAC Control Module Receive Threshold Interrupt Status Register"
bitfld.long 0x00 7. " C0_RX_THRESH_7_STAT ,Core 0 Receive Threshold Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " C0_RX_THRESH_6_STAT ,Core 0 Receive Threshold Masked Interrupt 6 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " C0_RX_THRESH_5_STAT ,Core 0 Receive Threshold Masked Interrupt 5 Status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " C0_RX_THRESH_4_STAT ,Core 0 Receive Threshold Masked Interrupt 4 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " C0_RX_THRESH_3_STAT ,Core 0 Receive Threshold Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " C0_RX_THRESH_2_STAT ,Core 0 Receive Threshold Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " C0_RX_THRESH_1_STAT ,Core 0 Receive Threshold Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " C0_RX_THRESH_0_STAT ,Core 0 Receive Threshold Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x04 "CMRXINTSTAT,EMAC Control Module Receive Interrupt Status Register"
bitfld.long 0x04 7. " C_RX_7_STAT ,Core 0 Receive Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x04 6. " C_RX_6_STAT ,Core 0 Receive Masked Interrupt 6 Status" "No interrupt,Interrupt"
bitfld.long 0x04 5. " C_RX_5_STAT ,Core 0 Receive Masked Interrupt 5 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 4. " C_RX_4_STAT ,Core 0 Receive Masked Interrupt 4 Status" "No interrupt,Interrupt"
bitfld.long 0x04 3. " C_RX_3_STAT ,Core 0 Receive Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " C_RX_2_STAT ,Core 0 Receive Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " C_RX_1_STAT ,Core 0 Receive Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x04 0. " C_RX_0_STAT ,Core 0 Receive Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x08 "CMTXINTSTAT,EMAC Control Module Transmit Interrupt Status Register"
bitfld.long 0x08 7. " C_TX_7_STAT ,Core 0 Transmit Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x08 6. " C_TX_6_STAT ,Core 0 Transmit Masked Interrupt 6 Status" "No interrupt,Interrupt"
bitfld.long 0x08 5. " C_TX_5_STAT ,Core 0 Transmit Masked Interrupt 5 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 4. " C_TX_4_STAT ,Core 0 Transmit Masked Interrupt 4 Status" "No interrupt,Interrupt"
bitfld.long 0x08 3. " C_TX_3_STAT ,Core 0 Transmit Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x08 2. " C_TX_2_STAT ,Core 0 Transmit Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 1. " C_TX_1_STAT ,Core 0 Transmit Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x08 0. " C_TX_0_STAT ,Core 0 Transmit Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x0c "CMMISCINTSTAT,EMAC Control Module Miscellaneous Interrupt Status Register"
bitfld.long 0x0C 3. " STAT_PEND_STAT ,Core 0 Miscellaneous Masked Interrupt (STAT_PEND) Status" "No interrupt,Interrupt"
bitfld.long 0x0C 2. " HOST_PEND_STAT ,Core 0 Miscellaneous Masked Interrupt (HOST_PEND) Status" "No interrupt,Interrupt"
bitfld.long 0x0C 1. " MDIO_LINKINT_STAT ,Core 0 Miscellaneous Masked Interrupt (MDIO_LINKINT) Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 0. " MDIO_USERINT_STAT ,ECore 0 Miscellaneous Masked Interrupt (MDIO_USERINT) Status" "No interrupt,Interrupt"
group.long 0x70++0x7
line.long 0x00 "CMRXINTMAX,EMAC Control Module Receive Interrupts per Millisecond Register"
bitfld.long 0x00 0.--5. " RXIMAX ,Core 0 Receive Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CMTXINTMAX,EMAC Control Module Transmit Interrupts per Millisecond Register"
bitfld.long 0x04 0.--5. " TXIMAX ,Core 0 Transmit Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 0xb
tree.end
tree "EMAC Port Registers"
base ad:0x4a100000
width 20.
rgroup.long 0x00++0x3
line.long 0x00 "TXIDVER,Transmit Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " TXIDENT ,Transmit identification value"
hexmask.long.byte 0x00 8.--15. 1. " TXMAJORVER ,Transmit major version"
hexmask.long.byte 0x00 0.--7. 1. " TXMINORVER ,Transmit minor version"
group.long 0x04++0x7
line.long 0x00 "TXCONTROL,Transmit Control Register"
bitfld.long 0x00 0. " TXEN ,Transmit enable" "Disabled,Enabled"
line.long 0x04 "TXTEARDOWN,Transmit Teardown Register"
bitfld.long 0x04 0.--2. " TXTDNCH ,Transmit teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
rgroup.long 0x10++0x3
line.long 0x00 "RXIDVER,Receive Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " RXIDENT ,Receive identification value"
hexmask.long.byte 0x00 8.--15. 1. " RXMAJORVER ,Receive major version"
hexmask.long.byte 0x00 0.--7. 1. " RXMINORVER ,Receive minor version"
group.long 0x14++0x7
line.long 0x00 "RXCONTROL,Receive Control Register"
bitfld.long 0x00 0. " RXEN ,Receive DMA enable" "Disabled,Enabled"
line.long 0x04 "RXTEARDOWN,Receive Teardown Register"
bitfld.long 0x04 0.--2. " RXTDNCH ,Receive teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
rgroup.long 0x80++0x7
line.long 0x00 "TXINTSTATRAW,Transmit Interrupt Status (Unmasked) Register"
bitfld.long 0x00 7. " TX7PEND ,TX7PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 6. " TX6PEND ,TX6PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 5. " TX5PEND ,TX5PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 4. " TX4PEND ,TX4PEND raw interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TX3PEND ,TX3PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 2. " TX2PEND ,TX2PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 1. " TX1PEND ,TX1PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 0. " TX0PEND ,TX0PEND raw interrupt read" "No interrupt,Interrupt"
line.long 0x04 "TXINTSTATMASKED,Transmit Interrupt Status (Masked) Register"
bitfld.long 0x04 7. " TX7PEND ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 6. " TX6PEND ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 5. " TX5PEND ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 4. " TX4PEND ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " TX3PEND ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 2. " TX2PEND ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 1. " TX1PEND ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 0. " TX0PEND ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
group.long 0x88++0x7
line.long 0x00 "TXINTMASKSET,Transmit Interrupt Status Mask Set Register"
bitfld.long 0x00 7. " TX7MASK ,Transmit channel 7 interrupt mask set" "No effect,Set"
bitfld.long 0x00 6. " TX6MASK ,Transmit channel 6 interrupt mask set" "No effect,Set"
bitfld.long 0x00 5. " TX5MASK ,Transmit channel 5 interrupt mask set" "No effect,Set"
bitfld.long 0x00 4. " TX4MASK ,Transmit channel 4 interrupt mask set" "No effect,Set"
textline " "
bitfld.long 0x00 3. " TX3MASK ,Transmit channel 3 interrupt mask set" "No effect,Set"
bitfld.long 0x00 2. " TX2MASK ,Transmit channel 2 interrupt mask set" "No effect,Set"
bitfld.long 0x00 1. " TX1MASK ,Transmit channel 1 interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " TX0MASK ,Transmit channel 0 interrupt mask set" "No effect,Set"
line.long 0x04 "TXINTMASKCLEAR,Transmit Interrupt Status Mask Clear Register"
eventfld.long 0x04 7. " TX7MASK ,Transmit channel 7 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 6. " TX6MASK ,Transmit channel 6 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 5. " TX5MASK ,Transmit channel 5 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 4. " TX4MASK ,Transmit channel 4 interrupt mask clear" "No effect,Clear"
textline " "
eventfld.long 0x04 3. " TX3MASK ,Transmit channel 3 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 2. " TX2MASK ,Transmit channel 2 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 1. " TX1MASK ,Transmit channel 1 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 0. " TX0MASK ,Transmit channel 0 interrupt mask clear" "No effect,Clear"
width 20.
rgroup.long 0x90++0x7
line.long 0x00 "MACINVECTOR,MAC Input Vector Register"
bitfld.long 0x00 27. " STATPEND ,EMAC module statistics interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 26. " HOSTPEND ,EMAC module host error interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 25. " LINKINT ,MDIO module link change interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 24. " USERINT ,MDIO module user interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 23. " TXPEND7 ,Transmit channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 22. " TXPEND6 ,Transmit channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 21. " TXPEND5 ,Transmit channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 20. " TXPEND4 ,Transmit channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " TXPEND3 ,Transmit channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 18. " TXPEND2 ,Transmit channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 17. " TXPEND1 ,Transmit channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 16. " TXPEND0 ,Transmit channel 0 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 15. " RXTHRESHPEND7 ,Receive threshold channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 14. " RXTHRESHPEND6 ,Receive threshold channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 13. " RXTHRESHPEND5 ,Receive threshold channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 12. " RXTHRESHPEND4 ,Receive threshold channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 11. " RXTHRESHPEND3 ,Receive threshold channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 10. " RXTHRESHPEND2 ,Receive threshold channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 9. " RXTHRESHPEND1 ,Receive threshold channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 8. " RXTHRESHPEND0 ,Receive threshold channel 0 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 7. " RXPEND7 ,Receive channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 6. " RXPEND6 ,Receive channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 5. " RXPEND5 ,Receive channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 4. " RXPEND4 ,Receive channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 3. " RXPEND3 ,Receive channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 2. " RXPEND2 ,Receive channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 1. " RXPEND1 ,Receive channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 0. " RXPEND0 ,Receive channel 0 interrupt pending status" "Not pending,Pending"
width 20.
line.long 0x04 "MACEOIVECTOR,MAC End Of Interrupt Vector Register"
bitfld.long 0x04 3. " MISCEOI ,End of interrupt processing for Miscellaneous interrupt" "Low,High"
bitfld.long 0x04 2. " TXEOI ,End of interrupt processing for TXPULSE interrupt" "Low,High"
bitfld.long 0x04 1. " RXEOI ,End of interrupt processing for RXPULSE interrupt" "Low,High"
bitfld.long 0x04 0. " RXTHRESHEOI ,End of interrupt processing for RXTHRESH interrupt" "Low,High"
rgroup.long 0xa0++0x7
line.long 0x00 "RXINTSTATRAW,Receive Interrupt Status (Unmasked) Register"
bitfld.long 0x00 7. " RX7PEND ,RX7PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 6. " RX6PEND ,RX6PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 5. " RX5PEND ,RX5PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 4. " RX4PEND ,RX4PEND raw interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " RX3PEND ,RX3PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 2. " RX2PEND ,RX2PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 1. " RX1PEND ,RX1PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 0. " RX0PEND ,RX0PEND raw interrupt read" "No interrupt,Interrupt"
line.long 0x04 "RXINTSTATMASKED,Receive Interrupt Status (Masked) Register"
bitfld.long 0x04 7. " RX7PEND ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 6. " RX6PEND ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 5. " RX5PEND ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 4. " RX4PEND ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " RX3PEND ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 2. " RX2PEND ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 1. " RX1PEND ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 0. " RX0PEND ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
group.long 0xa8++0x7
line.long 0x00 "RXINTMASKSET,Receive Interrupt Status Mask Set Register"
bitfld.long 0x00 7. " RX7MASK ,Receive channel 7 interrupt mask set" "No effect,Set"
bitfld.long 0x00 6. " RX6MASK ,Receive channel 6 interrupt mask set" "No effect,Set"
bitfld.long 0x00 5. " RX5MASK ,Receive channel 5 interrupt mask set" "No effect,Set"
bitfld.long 0x00 4. " RX4MASK ,Receive channel 4 interrupt mask set" "No effect,Set"
textline " "
bitfld.long 0x00 3. " RX3MASK ,Receive channel 3 interrupt mask set" "No effect,Set"
bitfld.long 0x00 2. " RX2MASK ,Receive channel 2 interrupt mask set" "No effect,Set"
bitfld.long 0x00 1. " RX1MASK ,Receive channel 1 interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " RX0MASK ,Receive channel 0 interrupt mask set" "No effect,Set"
line.long 0x04 "RXINTMASKCLEAR,Receive Interrupt Status Mask Clear Register"
eventfld.long 0x04 7. " RX7MASK ,Receive channel 7 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 6. " RX6MASK ,Receive channel 6 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 5. " RX5MASK ,Receive channel 5 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 4. " RX4MASK ,Receive channel 4 interrupt mask clear" "No effect,Clear"
textline " "
eventfld.long 0x04 3. " RX3MASK ,Receive channel 3 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 2. " RX2MASK ,Receive channel 2 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 1. " RX1MASK ,Receive channel 1 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 0. " RX0MASK ,Receive channel 0 interrupt mask clear" "No effect,Clear"
rgroup.long 0xb0++0x7
line.long 0x00 "MACINTSTATRAW,MAC Interrupt Status (Unmasked) Register"
bitfld.long 0x00 1. " HOSTPEND ,Host pending interrupt" "Not pending,Pending"
bitfld.long 0x00 0. " STATPEND ,Statistics pending interrupt" "Not pending,Pending"
line.long 0x04 "MACINTSTATMASKED,MAC Interrupt Status (Masked) Register"
bitfld.long 0x04 1. " HOSTPEND ,Host pending interrupt" "Not pending,Pending"
bitfld.long 0x04 0. " STATPEND ,Statistics pending interrupt" "Not pending,Pending"
group.long 0xb8++0x7
line.long 0x00 "MACINTSTATMASKSET,MAC Interrupt Status Mask Set Register"
bitfld.long 0x00 1. " HOSTMASK ,Host error interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " STATMASK ,Statistics interrupt mask set" "No effect,Set"
line.long 0x04 "MACINTSTATMASKCLEAR,MAC Interrupt Status Mask Clear Register"
bitfld.long 0x04 1. " HOSTMASK ,Host error interrupt mask clear" "No effect,Clear"
bitfld.long 0x04 0. " STATMASK ,Statistics interrupt mask clear" "No effect,Clear"
group.long 0x100++0x17
line.long 0x00 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register"
bitfld.long 0x00 30. " RXPASSCRC ,Pass received CRC enable" "Disabled,Enabled"
bitfld.long 0x00 29. " RXQOSEN ,Receive quality of service (QOS) enable" "Disabled,Enabled"
bitfld.long 0x00 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
bitfld.long 0x00 24. " RXCMFEN ,Receive copy MAC control frames enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " RXCSFEN ,Receive copy short frames enable" "Filtered,Transferred"
bitfld.long 0x00 22. " RXCEFEN ,Receive copy error frames enable" "Filtered,Transferred"
bitfld.long 0x00 21. " RXCAFEN ,Receive copy all frames enable" "Disabled,Enabled"
bitfld.long 0x00 16.--18. " RXPROMCH ,Receive promiscuous channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
textline " "
bitfld.long 0x00 13. " RXBROADEN ,Receive broadcast enable" "Filtered,Transferred"
bitfld.long 0x00 8.--10. " RXBROADCH ,Receive broadcast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
bitfld.long 0x00 5. " RXMULTEN ,Receive multicast enable" "Filtered,Transferred"
bitfld.long 0x00 0.--2. " RXMULTCH ,Receive multicast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
line.long 0x04 "RXUNICASTSET,Receive Unicast Set Register"
bitfld.long 0x04 7. " RXCH7SET ,Receive channel 7 unicast enable set" "No effect,Set"
bitfld.long 0x04 6. " RXCH6SET ,Receive channel 6 unicast enable set" "No effect,Set"
bitfld.long 0x04 5. " RXCH5SET ,Receive channel 5 unicast enable set" "No effect,Set"
bitfld.long 0x04 4. " RXCH4SET ,Receive channel 4 unicast enable set" "No effect,Set"
textline " "
bitfld.long 0x04 3. " RXCH3SET ,Receive channel 3 unicast enable set" "No effect,Set"
bitfld.long 0x04 2. " RXCH2SET ,Receive channel 2 unicast enable set" "No effect,Set"
bitfld.long 0x04 1. " RXCH1SET ,Receive channel 1 unicast enable set" "No effect,Set"
bitfld.long 0x04 0. " RXCH0SET ,Receive channel 0 unicast enable set" "No effect,Set"
line.long 0x08 "RXUNICASTCLEAR,Receive Unicast Clear Register"
eventfld.long 0x08 7. " RXCH7CLEAR ,Receive channel 7 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 6. " RXCH6CLEAR ,Receive channel 6 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 5. " RXCH5CLEAR ,Receive channel 5 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 4. " RXCH4CLEAR ,Receive channel 4 unicast enable clear" "No effect,Clear"
textline " "
eventfld.long 0x08 3. " RXCH3CLEAR ,Receive channel 3 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 2. " RXCH2CLEAR ,Receive channel 2 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 1. " RXCH1CLEAR ,Receive channel 1 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 0. " RXCH0CLEAR ,Receive channel 0 unicast enable clear" "No effect,Clear"
line.long 0x0c "RXMAXLEN,Receive Maximum Length Register"
hexmask.long.word 0x0c 0.--15. 1. " RXMAXLEN ,Received maximum frame length"
line.long 0x10 "RXBUFFEROFFSET,Receive Buffer Offset Register"
hexmask.long.word 0x10 0.--15. 1. " RXBUFFEROFFSET ,Receive buffer offset"
line.long 0x14 "RXFILTERLOWTHRESH,Receive Filter Low Priority Packets Threshold Register"
hexmask.long.byte 0x14 0.--7. 1. " RXFILTERTHRESH ,Receive filter low threshold bits"
width 20.
group.long 0x120++0x1f
line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,Receive flow threshold"
line.long 0x4 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
hexmask.long.byte 0x4 0.--7. 1. " RX1FLOWTHRESH ,Receive flow threshold"
line.long 0x8 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
hexmask.long.byte 0x8 0.--7. 1. " RX2FLOWTHRESH ,Receive flow threshold"
line.long 0xC "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
hexmask.long.byte 0xC 0.--7. 1. " RX3FLOWTHRESH ,Receive flow threshold"
line.long 0x10 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
hexmask.long.byte 0x10 0.--7. 1. " RX4FLOWTHRESH ,Receive flow threshold"
line.long 0x14 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
hexmask.long.byte 0x14 0.--7. 1. " RX5FLOWTHRESH ,Receive flow threshold"
line.long 0x18 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
hexmask.long.byte 0x18 0.--7. 1. " RX6FLOWTHRESH ,Receive flow threshold"
line.long 0x1C "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
hexmask.long.byte 0x1C 0.--7. 1. " RX7FLOWTHRESH ,Receive flow threshold"
wgroup.long 0x140++0x1f
line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,Receive free buffer count"
line.long 0x4 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
hexmask.long.word 0x4 0.--15. 1. " RX1FREEBUF ,Receive free buffer count"
line.long 0x8 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
hexmask.long.word 0x8 0.--15. 1. " RX2FREEBUF ,Receive free buffer count"
line.long 0xC "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
hexmask.long.word 0xC 0.--15. 1. " RX3FREEBUF ,Receive free buffer count"
line.long 0x10 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
hexmask.long.word 0x10 0.--15. 1. " RX4FREEBUF ,Receive free buffer count"
line.long 0x14 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
hexmask.long.word 0x14 0.--15. 1. " RX5FREEBUF ,Receive free buffer count"
line.long 0x18 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
hexmask.long.word 0x18 0.--15. 1. " RX6FREEBUF ,Receive free buffer count"
line.long 0x1C "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
hexmask.long.word 0x1C 0.--15. 1. " RX7FREEBUF ,Receive free buffer count"
group.long 0x160++0x3
line.long 0x00 "MACCONTROL,MAC Control Register"
bitfld.long 0x00 17. " GIGFORCE ,Gigabit Mode Force" "Disabled,Enabled"
bitfld.long 0x00 14. " RXOFFLENBLOCK ,Receive offset / length word write block" "Not blocked,Blocked"
bitfld.long 0x00 13. " RXOWNERSHIP ,Receive ownership write bit value" "Zero,One"
textline " "
bitfld.long 0x00 12. " RXFIFOFLOWEN ,Receive FIFO flow control enable" "Disabled,Enabled"
bitfld.long 0x00 11. " CMDIDLE ,Command Idle" "Not commanded,Commanded"
bitfld.long 0x00 9. " TXPTYPE ,Transmit queue priority type" "Round-robin,Fixed-priority"
textline " "
bitfld.long 0x00 7. " GIG ,Gigabit mode" "Disabled,Enabled"
bitfld.long 0x00 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
bitfld.long 0x00 5. " GMMIIEN ,GMII enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
bitfld.long 0x00 3. " RXBUFFERFLOWEN ,Receive flow control enable" "Disabled,Enabled"
bitfld.long 0x00 1. " LOOPBACK ,Loopback mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " FULLDUPLEX ,Full-duplex mode enable" "Disabled,Enabled"
rgroup.long 0x164++0x3
line.long 0x00 "MACSTATUS,MAC Status Register"
bitfld.long 0x00 31. " IDLE ,EMAC idle" "Busy,Idle"
bitfld.long 0x00 20.--23. " TXERRCODE ,Transmit host error code" "NOERROR,SOPERROR,OWNERSHIP,NOEOP,NULLPTR,NULLEN,LENERROR,..."
bitfld.long 0x00 16.--18. " TXERRCH ,Transmit host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
textline " "
bitfld.long 0x00 12.--15. " RXERRCODE ,Receive host error code" "NOERROR,,OWNERSHIP,,NULLPTR,..."
bitfld.long 0x00 8.--10. " RXERRCH ,Receive host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
bitfld.long 0x00 4. " RGMIIGIG ,RGMII gigabit" "Low,High"
textline " "
bitfld.long 0x00 3. " RGMIIFULLDUPLEX ,RGMII full-duplex" "Low,High"
bitfld.long 0x00 2. " RXQOSACT ,Receive quality of service (QOS)" "Disabled,Enabled"
bitfld.long 0x00 1. " RXFLOWACT ,Receive flow control" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " TXFLOWACT ,Transmit flow control" "Disabled,Enabled"
group.long 0x168++0x7
line.long 0x00 "EMCONTROL,Emulation Control Register"
bitfld.long 0x00 1. " SOFT ,Emulation soft bit" "0,1"
bitfld.long 0x00 0. " FREE ,Emulation free bit" "0,1"
line.long 0x04 "FIFOCONTROL,FIFO Control Register"
hexmask.long.byte 0x04 16.--22. 1. " RXFIFOFLOWTHRESH ,Receive FIFO flow control threshold"
bitfld.long 0x04 0.--4. " TXCELLTHRESH ,Transmit FIFO cell threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x170++0x3
line.long 0x00 "MACCONFIG,MAC Configuration Register"
hexmask.long.byte 0x00 24.--31. 1. " TXCELLDEPTH ,Transmit cell depth"
hexmask.long.byte 0x00 16.--23. 1. " RXCELLDEPTH ,Receive cell depth"
hexmask.long.byte 0x00 8.--15. 1. " ADDRTYPE ,Address type"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " MACCFIG ,MAC configuration value"
group.long 0x174++0x3
line.long 0x00 "SOFTRESET,Soft Reset Register"
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x1d0++0xf
line.long 0x00 "MACSRCADDRLO,MAC Source Address Low Bytes Register"
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits (byte 0)"
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15-8 (byte 1)"
line.long 0x04 "MACSRCADDRHI,MAC Source Address High Bytes Register"
hexmask.long.byte 0x04 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23-16 (byte 2)"
hexmask.long.byte 0x04 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31-24 (byte 3)"
hexmask.long.byte 0x04 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39-32 (byte 4)"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47-40 (byte 5)"
line.long 0x08 "MACHASH1,MAC Address Hash 1 Register"
line.long 0x0c "MACHASH2,MAC Address Hash 2 Register"
rgroup.long 0x1e0++0xf
line.long 0x00 "BOFFTEST,Backoff Test Register"
hexmask.long.word 0x00 16.--25. 1. " RNDNUM ,Backoff random number generator"
hexmask.long.byte 0x00 12.--15. 1. " COLLCOUNT ,Collision count"
hexmask.long.word 0x00 0.--9. 1. " TXBACKOFF ,Backoff count"
line.long 0x04 "TPACETEST,Transmit Pacing Test Register"
hexmask.long.byte 0x04 0.--4. 1. " PACEVAL ,Pacing register current value"
line.long 0x08 "RXPAUSE,Receive Pause Timer Register"
hexmask.long.word 0x08 0.--15. 1. " PAUSETIMER ,Pause timer value bits"
line.long 0x0c "TXPAUSE,Transmit Pause Timer Register"
hexmask.long.word 0x0c 0.--15. 1. " PAUSETIMER ,Pause timer value bits"
group.long 0x500++0xb
line.long 0x00 "MACADDRLO,MAC Address Low Bytes Register"
bitfld.long 0x00 20. " VALID ,Address valid" "Invalid,Valid"
bitfld.long 0x00 19. " MATCHFILT ,Match or filter" "Filtered,Matched"
bitfld.long 0x00 16.--18. " CHANNEL ,Channel" "0,1,2,3,4,5,6,7"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " MACADDR0 ,MAC address lower 8 bits (byte 0)"
hexmask.long.byte 0x00 0.--7. 1. " MACADDR1 ,MAC address bits 15-8 (byte 1)"
line.long 0x04 "MACADDRHI,MAC Address High Bytes Register"
hexmask.long.byte 0x04 24.--31. 1. " MACADDR2 ,MAC source address bits 23-16 (byte 2)"
hexmask.long.byte 0x04 16.--23. 1. " MACADDR3 ,MAC source address bits 31-24 (byte 3)"
hexmask.long.byte 0x04 8.--15. 1. " MACADDR4 ,MAC source address bits 39-32 (byte 4)"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " MACADDR5 ,MAC source address bits 47-40 (byte 5)"
line.long 0x08 "MACINDEX,MAC Index Register"
hexmask.long.byte 0x08 0.--4. 1. " MACINDEX ,MAC address index"
group.long 0x600++0x1f
line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
line.long 0x4 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
line.long 0x8 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
line.long 0xC "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
line.long 0x10 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
line.long 0x14 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
line.long 0x18 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
line.long 0x1C "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x620++0x1f
line.long 0x0 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
line.long 0x4 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
line.long 0x8 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
line.long 0xC "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
line.long 0x10 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
line.long 0x14 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
line.long 0x18 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
line.long 0x1C "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x640++0x1f
line.long 0x0 "TX0CP,Transmit Channel 0 Completion Pointer Register"
line.long 0x4 "TX1CP,Transmit Channel 1 Completion Pointer Register"
line.long 0x8 "TX2CP,Transmit Channel 2 Completion Pointer Register"
line.long 0xC "TX3CP,Transmit Channel 3 Completion Pointer Register"
line.long 0x10 "TX4CP,Transmit Channel 4 Completion Pointer Register"
line.long 0x14 "TX5CP,Transmit Channel 5 Completion Pointer Register"
line.long 0x18 "TX6CP,Transmit Channel 6 Completion Pointer Register"
line.long 0x1C "TX7CP,Transmit Channel 7 Completion Pointer Register"
group.long 0x660++0x1f
line.long 0x0 "RX0CP,Receive Channel 0 Completion Pointer Register"
line.long 0x4 "RX1CP,Receive Channel 1 Completion Pointer Register"
line.long 0x8 "RX2CP,Receive Channel 2 Completion Pointer Register"
line.long 0xC "RX3CP,Receive Channel 3 Completion Pointer Register"
line.long 0x10 "RX4CP,Receive Channel 4 Completion Pointer Register"
line.long 0x14 "RX5CP,Receive Channel 5 Completion Pointer Register"
line.long 0x18 "RX6CP,Receive Channel 6 Completion Pointer Register"
line.long 0x1C "RX7CP,Receive Channel 7 Completion Pointer Register"
group.long 0x200++0x8f "Network Statistics Registers"
line.long 0x00 "RXGOODFRAMES,Good Receive Frames Register"
line.long 0x04 "RXBCASTFRAMES,Broadcast Receive Frames Register"
line.long 0x08 "RXMCASTFRAMES,Multicast Receive Frames Register"
line.long 0x0c "RXPAUSEFRAMES,Pause Receive Frames Register"
line.long 0x10 "RXCRCERRORS,Receive CRC Errors Register"
line.long 0x14 "RXALIGNCODEERRORS,Receive Alignment/Code Errors Register"
line.long 0x18 "RXOVERSIZED,Receive Oversized Frames Register"
line.long 0x1c "RXJABBER,Receive Jabber Frames Register"
line.long 0x20 "RXUNDERSIZED,Receive Undersized Frames Register"
line.long 0x24 "RXFRAGMENTS,Receive Frame Fragments Register"
line.long 0x28 "RXFILTERED,Filtered Receive Frames Register"
line.long 0x2c "RXQOSFILTERED,Receive QOS Filtered Frames Register"
line.long 0x30 "RXOCTETS,Receive Octet Frames Register"
line.long 0x34 "TXGOODFRAMES,Good Transmit Frames Register"
line.long 0x38 "TXBCASTFRAMES,Broadcast Transmit Frames Register"
line.long 0x3c "TXMCASTFRAMES,Multicast Transmit Frames Register"
line.long 0x40 "TXPAUSEFRAMES,Pause Transmit Frames Register"
line.long 0x44 "TXDEFERRED,Deferred Transmit Frames Register"
line.long 0x48 "TXCOLLISION,Collision Register"
line.long 0x4c "TXSINGLECOLL,Single Collision Transmit Frames Register"
line.long 0x50 "TXMULTICOLL,Multiple Collision Transmit Frames Register"
line.long 0x54 "TXEXCESSIVECOLL,Excessive Collisions Register"
line.long 0x58 "TXLATECOLL,Late Collisions Register"
line.long 0x5c "TXUNDERRUN,Transmit Underrun Register"
line.long 0x60 "TXCARRIERSENSE,Transmit Carrier Sense Errors Register"
line.long 0x64 "TXOCTETS,Transmit Octet Frames Register"
line.long 0x68 "FRAME64,Transmit and Receive 64 Octet Frames Register"
line.long 0x6c "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register"
line.long 0x70 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register"
line.long 0x74 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register"
line.long 0x78 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register"
line.long 0x7c "FRAME1024TUP,Transmit and Receive 1024 or Above Octet Frames Register"
line.long 0x80 "NETOCTETS,Network Octet Frames Register"
line.long 0x84 "RXSOFOVERRUNS,Receive Start of Frame Overruns Register"
line.long 0x88 "RXMOFOVERRUNS,Receive Middle of Frame Overruns Register"
line.long 0x8c "RXDMAOVERRUNS,Receive DMA Overruns Register"
width 0xb
tree.end
tree "MDIO (Management Data Input/Output)"
base ad:0x4a100800
width 9.
rgroup.long 0x00++0x03
line.long 0x00 "REVID,MDIO Revision ID Register"
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168"||cpu()=="DM8165DSP"||cpu()=="DM8166DSP"||cpu()=="DM8167DSP"||cpu()=="DM8168DSP"||cpuis("AM335*"))
hexmask.long.word 0x00 16.--31. 1. " MODID ,Type of peripheral"
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Major revision of peripheral"
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision of peripheral"
endif
group.long 0x04++0x7
line.long 0x00 "CONTROL,MDIO Control Register"
bitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE status" "Busy,Idle"
bitfld.long 0x00 30. " ENABLE ,MDIO state machine enable control" "Disabled,Enabled"
hexmask.long.byte 0x00 24.--28. 1. " HUC ,Highest User-access Channel"
textline " "
bitfld.long 0x00 20. " PREAMBLE ,MDIO frame preamble disable" "No,Yes"
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Failure"
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
textline " "
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505"||cpuis("AM335*"))
bitfld.long 0x00 17. " INT_TEST_ENABLE ,Interrupt test enable" "Disabled,Enabled"
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
else
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
endif
line.long 0x04 "ALIVE,MDIO PHY Alive Indication Register"
eventfld.long 0x04 31. " ALIVE[31] ,MDIO ALIVE bit 31" "Not acknowledged,Acknowledged"
eventfld.long 0x04 30. " ALIVE[30] ,MDIO ALIVE bit 30" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 29. " ALIVE[29] ,MDIO ALIVE bit 29" "Not acknowledged,Acknowledged"
eventfld.long 0x04 28. " ALIVE[28] ,MDIO ALIVE bit 28" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 27. " ALIVE[27] ,MDIO ALIVE bit 27" "Not acknowledged,Acknowledged"
eventfld.long 0x04 26. " ALIVE[26] ,MDIO ALIVE bit 26" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 25. " ALIVE[25] ,MDIO ALIVE bit 25" "Not acknowledged,Acknowledged"
eventfld.long 0x04 24. " ALIVE[24] ,MDIO ALIVE bit 24" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 23. " ALIVE[23] ,MDIO ALIVE bit 23" "Not acknowledged,Acknowledged"
eventfld.long 0x04 22. " ALIVE[22] ,MDIO ALIVE bit 22" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 21. " ALIVE[21] ,MDIO ALIVE bit 21" "Not acknowledged,Acknowledged"
eventfld.long 0x04 20. " ALIVE[20] ,MDIO ALIVE bit 20" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 19. " ALIVE[19] ,MDIO ALIVE bit 19" "Not acknowledged,Acknowledged"
eventfld.long 0x04 18. " ALIVE[18] ,MDIO ALIVE bit 18" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 17. " ALIVE[17] ,MDIO ALIVE bit 17" "Not acknowledged,Acknowledged"
eventfld.long 0x04 16. " ALIVE[16] ,MDIO ALIVE bit 16" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 15. " ALIVE[15] ,MDIO ALIVE bit 15" "Not acknowledged,Acknowledged"
eventfld.long 0x04 14. " ALIVE[14] ,MDIO ALIVE bit 14" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 13. " ALIVE[13] ,MDIO ALIVE bit 13" "Not acknowledged,Acknowledged"
eventfld.long 0x04 12. " ALIVE[12] ,MDIO ALIVE bit 12" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 11. " ALIVE[11] ,MDIO ALIVE bit 11" "Not acknowledged,Acknowledged"
eventfld.long 0x04 10. " ALIVE[10] ,MDIO ALIVE bit 10" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 9. " ALIVE[9] ,MDIO ALIVE bit 9" "Not acknowledged,Acknowledged"
eventfld.long 0x04 8. " ALIVE[8] ,MDIO ALIVE bit 8" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 7. " ALIVE[7] ,MDIO ALIVE bit 7" "Not acknowledged,Acknowledged"
eventfld.long 0x04 6. " ALIVE[6] ,MDIO ALIVE bit 6" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 5. " ALIVE[5] ,MDIO ALIVE bit 5" "Not acknowledged,Acknowledged"
eventfld.long 0x04 4. " ALIVE[4] ,MDIO ALIVE bit 4" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 3. " ALIVE[3] ,MDIO ALIVE bit 3" "Not acknowledged,Acknowledged"
eventfld.long 0x04 2. " ALIVE[2] ,MDIO ALIVE bit 2" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 1. " ALIVE[1] ,MDIO ALIVE bit 1" "Not acknowledged,Acknowledged"
eventfld.long 0x04 0. " ALIVE[0] ,MDIO ALIVE bit 0" "Not acknowledged,Acknowledged"
rgroup.long 0x0c++0x3
line.long 0x00 "LINK,MDIO PHY Link Status Register"
bitfld.long 0x00 31. " LINK[31] ,MDIO link state bit 31" "No link,Link"
bitfld.long 0x00 30. " LINK[30] ,MDIO link state bit 30" "No link,Link"
bitfld.long 0x00 29. " LINK[29] ,MDIO link state bit 29" "No link,Link"
bitfld.long 0x00 28. " LINK[28] ,MDIO link state bit 28" "No link,Link"
textline " "
bitfld.long 0x00 27. " LINK[27] ,MDIO link state bit 27" "No link,Link"
bitfld.long 0x00 26. " LINK[26] ,MDIO link state bit 26" "No link,Link"
bitfld.long 0x00 25. " LINK[25] ,MDIO link state bit 25" "No link,Link"
bitfld.long 0x00 24. " LINK[24] ,MDIO link state bit 24" "No link,Link"
textline " "
bitfld.long 0x00 23. " LINK[23] ,MDIO link state bit 23" "No link,Link"
bitfld.long 0x00 22. " LINK[22] ,MDIO link state bit 22" "No link,Link"
bitfld.long 0x00 21. " LINK[21] ,MDIO link state bit 21" "No link,Link"
bitfld.long 0x00 20. " LINK[20] ,MDIO link state bit 20" "No link,Link"
textline " "
bitfld.long 0x00 19. " LINK[19] ,MDIO link state bit 19" "No link,Link"
bitfld.long 0x00 18. " LINK[18] ,MDIO link state bit 18" "No link,Link"
bitfld.long 0x00 17. " LINK[17] ,MDIO link state bit 17" "No link,Link"
bitfld.long 0x00 16. " LINK[16] ,MDIO link state bit 16" "No link,Link"
textline " "
bitfld.long 0x00 15. " LINK[15] ,MDIO link state bit 15" "No link,Link"
bitfld.long 0x00 14. " LINK[14] ,MDIO link state bit 14" "No link,Link"
bitfld.long 0x00 13. " LINK[13] ,MDIO link state bit 13" "No link,Link"
bitfld.long 0x00 12. " LINK[12] ,MDIO link state bit 12" "No link,Link"
textline " "
bitfld.long 0x00 11. " LINK[11] ,MDIO link state bit 11" "No link,Link"
bitfld.long 0x00 10. " LINK[10] ,MDIO link state bit 10" "No link,Link"
bitfld.long 0x00 9. " LINK[9] ,MDIO link state bit 9" "No link,Link"
bitfld.long 0x00 8. " LINK[8] ,MDIO link state bit 8" "No link,Link"
textline " "
bitfld.long 0x00 7. " LINK[7] ,MDIO link state bit 7" "No link,Link"
bitfld.long 0x00 6. " LINK[6] ,MDIO link state bit 6" "No link,Link"
bitfld.long 0x00 5. " LINK[5] ,MDIO link state bit 5" "No link,Link"
bitfld.long 0x00 4. " LINK[4] ,MDIO link state bit 4" "No link,Link"
textline " "
bitfld.long 0x00 3. " LINK[3] ,MDIO link state bit 3" "No link,Link"
bitfld.long 0x00 2. " LINK[2] ,MDIO link state bit 2" "No link,Link"
bitfld.long 0x00 1. " LINK[1] ,MDIO link state bit 1" "No link,Link"
bitfld.long 0x00 0. " LINK[0] ,MDIO link state bit 0" "No link,Link"
width 18.
group.long 0x10++0x7
line.long 0x00 "LINKINTRAW,MDIO Link Status Change Interrupt Register"
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change event" "Not changed,Changed"
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change event" "Not changed,Changed"
line.long 0x04 "LINKINTMASKED,MDIO Link Status Change Interrupt (Masked) Register"
eventfld.long 0x04 1. " USERPHY1 ,MDIO link change interrupt" "Not changed,Changed"
eventfld.long 0x04 0. " USERPHY0 ,MDIO link change interrupt" "Not changed,Changed"
group.long 0x20++0x3
line.long 0x00 "USERINTRAW,MDIO User Command Complete Interrupt Register"
eventfld.long 0x00 1. " USERACCESS1 ,MDIO user command complete event" "Not completed,Completed"
eventfld.long 0x00 0. " USERACCESS0 ,MDIO user command complete event" "Not completed,Completed"
group.long 0x24++0x03
line.long 0x00 "USERINTMASKED,MDIO User Command Complete Interrupt (Masked) Register"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
group.long 0x80++0x0f
line.long 0x00 "USERACCESS0,MDIO User Access Register 0"
bitfld.long 0x00 31. " GO ,GO bit" "No effect,MDIO accessed"
bitfld.long 0x00 30. " WRITE ,Write enable" "Read,Write"
textline " "
bitfld.long 0x00 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
hexmask.long.word 0x00 21.--25. 0x20 " REGADR ,Register address"
textline " "
hexmask.long.byte 0x00 16.--20. 1. " PHYADR ,PHY address"
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data"
line.long 0x04 "USERPHYSEL0,MDIO User PHY Select Register 0"
bitfld.long 0x04 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
bitfld.long 0x04 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x04 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
line.long 0x08 "USERACCESS1,MDIO User Access Register 1"
bitfld.long 0x08 31. " GO ,GO bit" "No effect,MDIO accessed"
bitfld.long 0x08 30. " WRITE ,Write enable" "Read,Write"
textline " "
bitfld.long 0x08 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
hexmask.long.word 0x08 21.--25. 0x20 " REGADR ,Register address"
textline " "
hexmask.long.byte 0x08 16.--20. 1. " PHYADR ,PHY address"
hexmask.long.word 0x08 0.--15. 1. " DATA ,User data"
line.long 0x0c "USERPHYSEL1,MDIO User PHY Select Register 1"
bitfld.long 0x0c 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
bitfld.long 0x0c 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0c 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
width 0xb
tree.end
tree.end
tree "EMAC 1"
tree "EMAC Control Module Registers"
base ad:0x4a120900
width 19.
rgroup.long 0x00++0x03
line.long 0x00 "CMIDVER,EMAC Control Module Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " CPGMACSS_S_IDENT ,CPGMACSS_S Identification Value"
bitfld.long 0x00 11.--15. " CPGMACSS_S_RTL_VER ,CPGMACSS_S RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--10. " CPGMACSS_S_MAJ_VER ,CPGMACSS_S Major Version Value" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. " CPGMACSS_S_MINOR_VER ,CPGMACSS_S Minor Version Value"
group.long 0x04++0x07
line.long 0x00 "SOFTRESET,EMAC Control Module Software Reset Register"
bitfld.long 0x00 0. " SOFT_RESET ,Software reset" "No reset,Reset"
line.long 0x04 "CMEMCONTROL,EMAC Control Module Emulation Control Register"
bitfld.long 0x04 1. " SOFT ,Emulation Soft Mode" "Disabled,Enabled"
bitfld.long 0x04 0. " FREE ,Emulation Free Mode" "Disabled,Enabled"
group.long 0x0c++0x03
line.long 0x00 "CMINTCTRL,EMAC Control Module Interrupt Control Register"
bitfld.long 0x00 31. " INTTEST ,Interrupt Test" "Disabled,Enabled"
bitfld.long 0x00 21. " C2_TX ,C2_Tx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " C2_RX ,C2_Rx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 19. " C1_TX ,C1_Tx_Pulse Pacing Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 18. " C1_RX ,C1_Rx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " C0_TX ,C0_Tx_Pulse Pacing Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " C0_RX ,C0_Rx_Pulse Pacing Enable" "Disabled,Enabled"
hexmask.long.word 0x00 0.--11. 1. " INTPRESCALE ,Interrupt Counter Prescaler"
group.long 0x10++0x0f
line.long 0x00 "CMRXTHRESHINTEN,EMAC Control Module Receive Threshold Interrupt Enable Register"
bitfld.long 0x00 7. " C0_RX_THRESH_7_EN ,Core 0 Receive Threshold Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " C0_RX_THRESH_6_EN ,Core 0 Receive Threshold Interrupt 6 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " C0_RX_THRESH_5_EN ,Core 0 Receive Threshold Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " C0_RX_THRESH_4_EN ,Core 0 Receive Threshold Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " C0_RX_THRESH_3_EN ,Core 0 Receive Threshold Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " C0_RX_THRESH_2_EN ,Core 0 Receive Threshold Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " C0_RX_THRESH_1_EN ,Core 0 Receive Threshold Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " C0_RX_THRESH_0_EN ,Core 0 Receive Threshold Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x04 "CMRXINTEN,EMAC Control Module Receive Interrupt Enable Register"
bitfld.long 0x04 7. " C_RX_7_EN ,Core 0 Receive Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " C_RX_6_EN ,Core 0 Receive Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " C_RX_5_EN ,Core 0 Receive Interrupt 5 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " C_RX_4_EN ,Core 0 Receive Interrupt 4 Enable" "Disabled,Enabled"
bitfld.long 0x04 3. " C_RX_3_EN ,Core 0 Receive Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " C_RX_2_EN ,Core 0 Receive Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " C_RX_1_EN ,Core 0 Receive Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " C_RX_0_EN ,Core 0 Receive Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x08 "CMTXINTEN,EMAC Control Module Transmit Interrupt Enable Register"
bitfld.long 0x08 7. " C_TX_7_EN ,Core 0 Transmit Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x08 6. " C_TX_6_EN ,Core 0 Transmit Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x08 5. " C_TX_5_EN ,Core 0 Transmit Interrupt 5 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 4. " C_TX_4_EN ,Core 0 Transmit Interrupt 4 Enable" "Disabled,Enabled"
bitfld.long 0x08 3. " C_TX_3_EN ,Core 0 Transmit Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x08 2. " C_TX_2_EN ,Core 0 Transmit Interrupt 2 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " C_TX_1_EN ,Core 0 Transmit Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " C_TX_0_EN ,Core 0 Transmit Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x0c "CMMISCINTEN,EMAC Control Module Miscellaneous Interrupt Enable Register"
bitfld.long 0x0C 3. " STAT_PEND_EN ,Core 0 Miscellaneous Interrupt (STAT_PEND) Enable" "Disabled,Enabled"
bitfld.long 0x0C 2. " HOST_PEND_EN ,Core 0 Miscellaneous Interrupt (HOST_PEND) Enable" "Disabled,Enabled"
bitfld.long 0x0C 1. " MDIO_LINKINT_EN ,Core 0 Miscellaneous Interrupt (MDIO_LINKINT) Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 0. " MDIO_USERINT_EN ,ECore 0 Miscellaneous Interrupt (MDIO_USERINT) Enable" "Disabled,Enabled"
rgroup.long 0x40++0x0f
line.long 0x00 "CMRXTHRESHINTSTAT,EMAC Control Module Receive Threshold Interrupt Status Register"
bitfld.long 0x00 7. " C0_RX_THRESH_7_STAT ,Core 0 Receive Threshold Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " C0_RX_THRESH_6_STAT ,Core 0 Receive Threshold Masked Interrupt 6 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " C0_RX_THRESH_5_STAT ,Core 0 Receive Threshold Masked Interrupt 5 Status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " C0_RX_THRESH_4_STAT ,Core 0 Receive Threshold Masked Interrupt 4 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " C0_RX_THRESH_3_STAT ,Core 0 Receive Threshold Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " C0_RX_THRESH_2_STAT ,Core 0 Receive Threshold Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " C0_RX_THRESH_1_STAT ,Core 0 Receive Threshold Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " C0_RX_THRESH_0_STAT ,Core 0 Receive Threshold Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x04 "CMRXINTSTAT,EMAC Control Module Receive Interrupt Status Register"
bitfld.long 0x04 7. " C_RX_7_STAT ,Core 0 Receive Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x04 6. " C_RX_6_STAT ,Core 0 Receive Masked Interrupt 6 Status" "No interrupt,Interrupt"
bitfld.long 0x04 5. " C_RX_5_STAT ,Core 0 Receive Masked Interrupt 5 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 4. " C_RX_4_STAT ,Core 0 Receive Masked Interrupt 4 Status" "No interrupt,Interrupt"
bitfld.long 0x04 3. " C_RX_3_STAT ,Core 0 Receive Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " C_RX_2_STAT ,Core 0 Receive Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " C_RX_1_STAT ,Core 0 Receive Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x04 0. " C_RX_0_STAT ,Core 0 Receive Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x08 "CMTXINTSTAT,EMAC Control Module Transmit Interrupt Status Register"
bitfld.long 0x08 7. " C_TX_7_STAT ,Core 0 Transmit Masked Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x08 6. " C_TX_6_STAT ,Core 0 Transmit Masked Interrupt 6 Status" "No interrupt,Interrupt"
bitfld.long 0x08 5. " C_TX_5_STAT ,Core 0 Transmit Masked Interrupt 5 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 4. " C_TX_4_STAT ,Core 0 Transmit Masked Interrupt 4 Status" "No interrupt,Interrupt"
bitfld.long 0x08 3. " C_TX_3_STAT ,Core 0 Transmit Masked Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x08 2. " C_TX_2_STAT ,Core 0 Transmit Masked Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 1. " C_TX_1_STAT ,Core 0 Transmit Masked Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x08 0. " C_TX_0_STAT ,Core 0 Transmit Masked Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x0c "CMMISCINTSTAT,EMAC Control Module Miscellaneous Interrupt Status Register"
bitfld.long 0x0C 3. " STAT_PEND_STAT ,Core 0 Miscellaneous Masked Interrupt (STAT_PEND) Status" "No interrupt,Interrupt"
bitfld.long 0x0C 2. " HOST_PEND_STAT ,Core 0 Miscellaneous Masked Interrupt (HOST_PEND) Status" "No interrupt,Interrupt"
bitfld.long 0x0C 1. " MDIO_LINKINT_STAT ,Core 0 Miscellaneous Masked Interrupt (MDIO_LINKINT) Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x0C 0. " MDIO_USERINT_STAT ,ECore 0 Miscellaneous Masked Interrupt (MDIO_USERINT) Status" "No interrupt,Interrupt"
group.long 0x70++0x7
line.long 0x00 "CMRXINTMAX,EMAC Control Module Receive Interrupts per Millisecond Register"
bitfld.long 0x00 0.--5. " RXIMAX ,Core 0 Receive Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CMTXINTMAX,EMAC Control Module Transmit Interrupts per Millisecond Register"
bitfld.long 0x04 0.--5. " TXIMAX ,Core 0 Transmit Interrupts per Millisecond" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
width 0xb
tree.end
tree "EMAC Port Registers"
base ad:0x4a120000
width 20.
rgroup.long 0x00++0x3
line.long 0x00 "TXIDVER,Transmit Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " TXIDENT ,Transmit identification value"
hexmask.long.byte 0x00 8.--15. 1. " TXMAJORVER ,Transmit major version"
hexmask.long.byte 0x00 0.--7. 1. " TXMINORVER ,Transmit minor version"
group.long 0x04++0x7
line.long 0x00 "TXCONTROL,Transmit Control Register"
bitfld.long 0x00 0. " TXEN ,Transmit enable" "Disabled,Enabled"
line.long 0x04 "TXTEARDOWN,Transmit Teardown Register"
bitfld.long 0x04 0.--2. " TXTDNCH ,Transmit teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
rgroup.long 0x10++0x3
line.long 0x00 "RXIDVER,Receive Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. " RXIDENT ,Receive identification value"
hexmask.long.byte 0x00 8.--15. 1. " RXMAJORVER ,Receive major version"
hexmask.long.byte 0x00 0.--7. 1. " RXMINORVER ,Receive minor version"
group.long 0x14++0x7
line.long 0x00 "RXCONTROL,Receive Control Register"
bitfld.long 0x00 0. " RXEN ,Receive DMA enable" "Disabled,Enabled"
line.long 0x04 "RXTEARDOWN,Receive Teardown Register"
bitfld.long 0x04 0.--2. " RXTDNCH ,Receive teardown channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
rgroup.long 0x80++0x7
line.long 0x00 "TXINTSTATRAW,Transmit Interrupt Status (Unmasked) Register"
bitfld.long 0x00 7. " TX7PEND ,TX7PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 6. " TX6PEND ,TX6PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 5. " TX5PEND ,TX5PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 4. " TX4PEND ,TX4PEND raw interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TX3PEND ,TX3PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 2. " TX2PEND ,TX2PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 1. " TX1PEND ,TX1PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 0. " TX0PEND ,TX0PEND raw interrupt read" "No interrupt,Interrupt"
line.long 0x04 "TXINTSTATMASKED,Transmit Interrupt Status (Masked) Register"
bitfld.long 0x04 7. " TX7PEND ,TX7PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 6. " TX6PEND ,TX6PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 5. " TX5PEND ,TX5PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 4. " TX4PEND ,TX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " TX3PEND ,TX3PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 2. " TX2PEND ,TX2PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 1. " TX1PEND ,TX1PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 0. " TX0PEND ,TX0PEND masked interrupt read" "No interrupt,Interrupt"
group.long 0x88++0x7
line.long 0x00 "TXINTMASKSET,Transmit Interrupt Status Mask Set Register"
bitfld.long 0x00 7. " TX7MASK ,Transmit channel 7 interrupt mask set" "No effect,Set"
bitfld.long 0x00 6. " TX6MASK ,Transmit channel 6 interrupt mask set" "No effect,Set"
bitfld.long 0x00 5. " TX5MASK ,Transmit channel 5 interrupt mask set" "No effect,Set"
bitfld.long 0x00 4. " TX4MASK ,Transmit channel 4 interrupt mask set" "No effect,Set"
textline " "
bitfld.long 0x00 3. " TX3MASK ,Transmit channel 3 interrupt mask set" "No effect,Set"
bitfld.long 0x00 2. " TX2MASK ,Transmit channel 2 interrupt mask set" "No effect,Set"
bitfld.long 0x00 1. " TX1MASK ,Transmit channel 1 interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " TX0MASK ,Transmit channel 0 interrupt mask set" "No effect,Set"
line.long 0x04 "TXINTMASKCLEAR,Transmit Interrupt Status Mask Clear Register"
eventfld.long 0x04 7. " TX7MASK ,Transmit channel 7 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 6. " TX6MASK ,Transmit channel 6 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 5. " TX5MASK ,Transmit channel 5 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 4. " TX4MASK ,Transmit channel 4 interrupt mask clear" "No effect,Clear"
textline " "
eventfld.long 0x04 3. " TX3MASK ,Transmit channel 3 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 2. " TX2MASK ,Transmit channel 2 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 1. " TX1MASK ,Transmit channel 1 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 0. " TX0MASK ,Transmit channel 0 interrupt mask clear" "No effect,Clear"
width 20.
rgroup.long 0x90++0x7
line.long 0x00 "MACINVECTOR,MAC Input Vector Register"
bitfld.long 0x00 27. " STATPEND ,EMAC module statistics interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 26. " HOSTPEND ,EMAC module host error interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 25. " LINKINT ,MDIO module link change interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 24. " USERINT ,MDIO module user interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 23. " TXPEND7 ,Transmit channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 22. " TXPEND6 ,Transmit channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 21. " TXPEND5 ,Transmit channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 20. " TXPEND4 ,Transmit channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " TXPEND3 ,Transmit channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 18. " TXPEND2 ,Transmit channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 17. " TXPEND1 ,Transmit channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 16. " TXPEND0 ,Transmit channel 0 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 15. " RXTHRESHPEND7 ,Receive threshold channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 14. " RXTHRESHPEND6 ,Receive threshold channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 13. " RXTHRESHPEND5 ,Receive threshold channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 12. " RXTHRESHPEND4 ,Receive threshold channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 11. " RXTHRESHPEND3 ,Receive threshold channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 10. " RXTHRESHPEND2 ,Receive threshold channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 9. " RXTHRESHPEND1 ,Receive threshold channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 8. " RXTHRESHPEND0 ,Receive threshold channel 0 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 7. " RXPEND7 ,Receive channel 7 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 6. " RXPEND6 ,Receive channel 6 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 5. " RXPEND5 ,Receive channel 5 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 4. " RXPEND4 ,Receive channel 4 interrupt pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 3. " RXPEND3 ,Receive channel 3 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 2. " RXPEND2 ,Receive channel 2 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 1. " RXPEND1 ,Receive channel 1 interrupt pending status" "Not pending,Pending"
bitfld.long 0x00 0. " RXPEND0 ,Receive channel 0 interrupt pending status" "Not pending,Pending"
width 20.
line.long 0x04 "MACEOIVECTOR,MAC End Of Interrupt Vector Register"
bitfld.long 0x04 3. " MISCEOI ,End of interrupt processing for Miscellaneous interrupt" "Low,High"
bitfld.long 0x04 2. " TXEOI ,End of interrupt processing for TXPULSE interrupt" "Low,High"
bitfld.long 0x04 1. " RXEOI ,End of interrupt processing for RXPULSE interrupt" "Low,High"
bitfld.long 0x04 0. " RXTHRESHEOI ,End of interrupt processing for RXTHRESH interrupt" "Low,High"
rgroup.long 0xa0++0x7
line.long 0x00 "RXINTSTATRAW,Receive Interrupt Status (Unmasked) Register"
bitfld.long 0x00 7. " RX7PEND ,RX7PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 6. " RX6PEND ,RX6PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 5. " RX5PEND ,RX5PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 4. " RX4PEND ,RX4PEND raw interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " RX3PEND ,RX3PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 2. " RX2PEND ,RX2PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 1. " RX1PEND ,RX1PEND raw interrupt read" "No interrupt,Interrupt"
bitfld.long 0x00 0. " RX0PEND ,RX0PEND raw interrupt read" "No interrupt,Interrupt"
line.long 0x04 "RXINTSTATMASKED,Receive Interrupt Status (Masked) Register"
bitfld.long 0x04 7. " RX7PEND ,RX7PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 6. " RX6PEND ,RX6PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 5. " RX5PEND ,RX5PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 4. " RX4PEND ,RX4PEND masked interrupt read" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " RX3PEND ,RX3PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 2. " RX2PEND ,RX2PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 1. " RX1PEND ,RX1PEND masked interrupt read" "No interrupt,Interrupt"
bitfld.long 0x04 0. " RX0PEND ,RX0PEND masked interrupt read" "No interrupt,Interrupt"
group.long 0xa8++0x7
line.long 0x00 "RXINTMASKSET,Receive Interrupt Status Mask Set Register"
bitfld.long 0x00 7. " RX7MASK ,Receive channel 7 interrupt mask set" "No effect,Set"
bitfld.long 0x00 6. " RX6MASK ,Receive channel 6 interrupt mask set" "No effect,Set"
bitfld.long 0x00 5. " RX5MASK ,Receive channel 5 interrupt mask set" "No effect,Set"
bitfld.long 0x00 4. " RX4MASK ,Receive channel 4 interrupt mask set" "No effect,Set"
textline " "
bitfld.long 0x00 3. " RX3MASK ,Receive channel 3 interrupt mask set" "No effect,Set"
bitfld.long 0x00 2. " RX2MASK ,Receive channel 2 interrupt mask set" "No effect,Set"
bitfld.long 0x00 1. " RX1MASK ,Receive channel 1 interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " RX0MASK ,Receive channel 0 interrupt mask set" "No effect,Set"
line.long 0x04 "RXINTMASKCLEAR,Receive Interrupt Status Mask Clear Register"
eventfld.long 0x04 7. " RX7MASK ,Receive channel 7 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 6. " RX6MASK ,Receive channel 6 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 5. " RX5MASK ,Receive channel 5 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 4. " RX4MASK ,Receive channel 4 interrupt mask clear" "No effect,Clear"
textline " "
eventfld.long 0x04 3. " RX3MASK ,Receive channel 3 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 2. " RX2MASK ,Receive channel 2 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 1. " RX1MASK ,Receive channel 1 interrupt mask clear" "No effect,Clear"
eventfld.long 0x04 0. " RX0MASK ,Receive channel 0 interrupt mask clear" "No effect,Clear"
rgroup.long 0xb0++0x7
line.long 0x00 "MACINTSTATRAW,MAC Interrupt Status (Unmasked) Register"
bitfld.long 0x00 1. " HOSTPEND ,Host pending interrupt" "Not pending,Pending"
bitfld.long 0x00 0. " STATPEND ,Statistics pending interrupt" "Not pending,Pending"
line.long 0x04 "MACINTSTATMASKED,MAC Interrupt Status (Masked) Register"
bitfld.long 0x04 1. " HOSTPEND ,Host pending interrupt" "Not pending,Pending"
bitfld.long 0x04 0. " STATPEND ,Statistics pending interrupt" "Not pending,Pending"
group.long 0xb8++0x7
line.long 0x00 "MACINTSTATMASKSET,MAC Interrupt Status Mask Set Register"
bitfld.long 0x00 1. " HOSTMASK ,Host error interrupt mask set" "No effect,Set"
bitfld.long 0x00 0. " STATMASK ,Statistics interrupt mask set" "No effect,Set"
line.long 0x04 "MACINTSTATMASKCLEAR,MAC Interrupt Status Mask Clear Register"
bitfld.long 0x04 1. " HOSTMASK ,Host error interrupt mask clear" "No effect,Clear"
bitfld.long 0x04 0. " STATMASK ,Statistics interrupt mask clear" "No effect,Clear"
group.long 0x100++0x17
line.long 0x00 "RXMBPENABLE,Receive Multicast/Broadcast/Promiscuous Channel Enable Register"
bitfld.long 0x00 30. " RXPASSCRC ,Pass received CRC enable" "Disabled,Enabled"
bitfld.long 0x00 29. " RXQOSEN ,Receive quality of service (QOS) enable" "Disabled,Enabled"
bitfld.long 0x00 28. " RXNOCHAIN ,Receive no buffer chaining" "Multiple,Single"
bitfld.long 0x00 24. " RXCMFEN ,Receive copy MAC control frames enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " RXCSFEN ,Receive copy short frames enable" "Filtered,Transferred"
bitfld.long 0x00 22. " RXCEFEN ,Receive copy error frames enable" "Filtered,Transferred"
bitfld.long 0x00 21. " RXCAFEN ,Receive copy all frames enable" "Disabled,Enabled"
bitfld.long 0x00 16.--18. " RXPROMCH ,Receive promiscuous channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
textline " "
bitfld.long 0x00 13. " RXBROADEN ,Receive broadcast enable" "Filtered,Transferred"
bitfld.long 0x00 8.--10. " RXBROADCH ,Receive broadcast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
bitfld.long 0x00 5. " RXMULTEN ,Receive multicast enable" "Filtered,Transferred"
bitfld.long 0x00 0.--2. " RXMULTCH ,Receive multicast channel select" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
line.long 0x04 "RXUNICASTSET,Receive Unicast Set Register"
bitfld.long 0x04 7. " RXCH7SET ,Receive channel 7 unicast enable set" "No effect,Set"
bitfld.long 0x04 6. " RXCH6SET ,Receive channel 6 unicast enable set" "No effect,Set"
bitfld.long 0x04 5. " RXCH5SET ,Receive channel 5 unicast enable set" "No effect,Set"
bitfld.long 0x04 4. " RXCH4SET ,Receive channel 4 unicast enable set" "No effect,Set"
textline " "
bitfld.long 0x04 3. " RXCH3SET ,Receive channel 3 unicast enable set" "No effect,Set"
bitfld.long 0x04 2. " RXCH2SET ,Receive channel 2 unicast enable set" "No effect,Set"
bitfld.long 0x04 1. " RXCH1SET ,Receive channel 1 unicast enable set" "No effect,Set"
bitfld.long 0x04 0. " RXCH0SET ,Receive channel 0 unicast enable set" "No effect,Set"
line.long 0x08 "RXUNICASTCLEAR,Receive Unicast Clear Register"
eventfld.long 0x08 7. " RXCH7CLEAR ,Receive channel 7 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 6. " RXCH6CLEAR ,Receive channel 6 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 5. " RXCH5CLEAR ,Receive channel 5 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 4. " RXCH4CLEAR ,Receive channel 4 unicast enable clear" "No effect,Clear"
textline " "
eventfld.long 0x08 3. " RXCH3CLEAR ,Receive channel 3 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 2. " RXCH2CLEAR ,Receive channel 2 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 1. " RXCH1CLEAR ,Receive channel 1 unicast enable clear" "No effect,Clear"
eventfld.long 0x08 0. " RXCH0CLEAR ,Receive channel 0 unicast enable clear" "No effect,Clear"
line.long 0x0c "RXMAXLEN,Receive Maximum Length Register"
hexmask.long.word 0x0c 0.--15. 1. " RXMAXLEN ,Received maximum frame length"
line.long 0x10 "RXBUFFEROFFSET,Receive Buffer Offset Register"
hexmask.long.word 0x10 0.--15. 1. " RXBUFFEROFFSET ,Receive buffer offset"
line.long 0x14 "RXFILTERLOWTHRESH,Receive Filter Low Priority Packets Threshold Register"
hexmask.long.byte 0x14 0.--7. 1. " RXFILTERTHRESH ,Receive filter low threshold bits"
width 20.
group.long 0x120++0x1f
line.long 0x0 "RX0FLOWTHRESH,Receive Channel 0 Flow Control Threshold Register"
hexmask.long.byte 0x0 0.--7. 1. " RX0FLOWTHRESH ,Receive flow threshold"
line.long 0x4 "RX1FLOWTHRESH,Receive Channel 1 Flow Control Threshold Register"
hexmask.long.byte 0x4 0.--7. 1. " RX1FLOWTHRESH ,Receive flow threshold"
line.long 0x8 "RX2FLOWTHRESH,Receive Channel 2 Flow Control Threshold Register"
hexmask.long.byte 0x8 0.--7. 1. " RX2FLOWTHRESH ,Receive flow threshold"
line.long 0xC "RX3FLOWTHRESH,Receive Channel 3 Flow Control Threshold Register"
hexmask.long.byte 0xC 0.--7. 1. " RX3FLOWTHRESH ,Receive flow threshold"
line.long 0x10 "RX4FLOWTHRESH,Receive Channel 4 Flow Control Threshold Register"
hexmask.long.byte 0x10 0.--7. 1. " RX4FLOWTHRESH ,Receive flow threshold"
line.long 0x14 "RX5FLOWTHRESH,Receive Channel 5 Flow Control Threshold Register"
hexmask.long.byte 0x14 0.--7. 1. " RX5FLOWTHRESH ,Receive flow threshold"
line.long 0x18 "RX6FLOWTHRESH,Receive Channel 6 Flow Control Threshold Register"
hexmask.long.byte 0x18 0.--7. 1. " RX6FLOWTHRESH ,Receive flow threshold"
line.long 0x1C "RX7FLOWTHRESH,Receive Channel 7 Flow Control Threshold Register"
hexmask.long.byte 0x1C 0.--7. 1. " RX7FLOWTHRESH ,Receive flow threshold"
wgroup.long 0x140++0x1f
line.long 0x0 "RX0FREEBUFFER,Receive Channel 0 Free Buffer Count Register"
hexmask.long.word 0x0 0.--15. 1. " RX0FREEBUF ,Receive free buffer count"
line.long 0x4 "RX1FREEBUFFER,Receive Channel 1 Free Buffer Count Register"
hexmask.long.word 0x4 0.--15. 1. " RX1FREEBUF ,Receive free buffer count"
line.long 0x8 "RX2FREEBUFFER,Receive Channel 2 Free Buffer Count Register"
hexmask.long.word 0x8 0.--15. 1. " RX2FREEBUF ,Receive free buffer count"
line.long 0xC "RX3FREEBUFFER,Receive Channel 3 Free Buffer Count Register"
hexmask.long.word 0xC 0.--15. 1. " RX3FREEBUF ,Receive free buffer count"
line.long 0x10 "RX4FREEBUFFER,Receive Channel 4 Free Buffer Count Register"
hexmask.long.word 0x10 0.--15. 1. " RX4FREEBUF ,Receive free buffer count"
line.long 0x14 "RX5FREEBUFFER,Receive Channel 5 Free Buffer Count Register"
hexmask.long.word 0x14 0.--15. 1. " RX5FREEBUF ,Receive free buffer count"
line.long 0x18 "RX6FREEBUFFER,Receive Channel 6 Free Buffer Count Register"
hexmask.long.word 0x18 0.--15. 1. " RX6FREEBUF ,Receive free buffer count"
line.long 0x1C "RX7FREEBUFFER,Receive Channel 7 Free Buffer Count Register"
hexmask.long.word 0x1C 0.--15. 1. " RX7FREEBUF ,Receive free buffer count"
group.long 0x160++0x3
line.long 0x00 "MACCONTROL,MAC Control Register"
bitfld.long 0x00 17. " GIGFORCE ,Gigabit Mode Force" "Disabled,Enabled"
bitfld.long 0x00 14. " RXOFFLENBLOCK ,Receive offset / length word write block" "Not blocked,Blocked"
bitfld.long 0x00 13. " RXOWNERSHIP ,Receive ownership write bit value" "Zero,One"
textline " "
bitfld.long 0x00 12. " RXFIFOFLOWEN ,Receive FIFO flow control enable" "Disabled,Enabled"
bitfld.long 0x00 11. " CMDIDLE ,Command Idle" "Not commanded,Commanded"
bitfld.long 0x00 9. " TXPTYPE ,Transmit queue priority type" "Round-robin,Fixed-priority"
textline " "
bitfld.long 0x00 7. " GIG ,Gigabit mode" "Disabled,Enabled"
bitfld.long 0x00 6. " TXPACE ,Transmit pacing enable" "Disabled,Enabled"
bitfld.long 0x00 5. " GMMIIEN ,GMII enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " TXFLOWEN ,Transmit flow control enable" "Disabled,Enabled"
bitfld.long 0x00 3. " RXBUFFERFLOWEN ,Receive flow control enable" "Disabled,Enabled"
bitfld.long 0x00 1. " LOOPBACK ,Loopback mode enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " FULLDUPLEX ,Full-duplex mode enable" "Disabled,Enabled"
rgroup.long 0x164++0x3
line.long 0x00 "MACSTATUS,MAC Status Register"
bitfld.long 0x00 31. " IDLE ,EMAC idle" "Busy,Idle"
bitfld.long 0x00 20.--23. " TXERRCODE ,Transmit host error code" "NOERROR,SOPERROR,OWNERSHIP,NOEOP,NULLPTR,NULLEN,LENERROR,..."
bitfld.long 0x00 16.--18. " TXERRCH ,Transmit host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
textline " "
bitfld.long 0x00 12.--15. " RXERRCODE ,Receive host error code" "NOERROR,,OWNERSHIP,,NULLPTR,..."
bitfld.long 0x00 8.--10. " RXERRCH ,Receive host error channel" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7"
bitfld.long 0x00 4. " RGMIIGIG ,RGMII gigabit" "Low,High"
textline " "
bitfld.long 0x00 3. " RGMIIFULLDUPLEX ,RGMII full-duplex" "Low,High"
bitfld.long 0x00 2. " RXQOSACT ,Receive quality of service (QOS)" "Disabled,Enabled"
bitfld.long 0x00 1. " RXFLOWACT ,Receive flow control" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " TXFLOWACT ,Transmit flow control" "Disabled,Enabled"
group.long 0x168++0x7
line.long 0x00 "EMCONTROL,Emulation Control Register"
bitfld.long 0x00 1. " SOFT ,Emulation soft bit" "0,1"
bitfld.long 0x00 0. " FREE ,Emulation free bit" "0,1"
line.long 0x04 "FIFOCONTROL,FIFO Control Register"
hexmask.long.byte 0x04 16.--22. 1. " RXFIFOFLOWTHRESH ,Receive FIFO flow control threshold"
bitfld.long 0x04 0.--4. " TXCELLTHRESH ,Transmit FIFO cell threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x170++0x3
line.long 0x00 "MACCONFIG,MAC Configuration Register"
hexmask.long.byte 0x00 24.--31. 1. " TXCELLDEPTH ,Transmit cell depth"
hexmask.long.byte 0x00 16.--23. 1. " RXCELLDEPTH ,Receive cell depth"
hexmask.long.byte 0x00 8.--15. 1. " ADDRTYPE ,Address type"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " MACCFIG ,MAC configuration value"
group.long 0x174++0x3
line.long 0x00 "SOFTRESET,Soft Reset Register"
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x1d0++0xf
line.long 0x00 "MACSRCADDRLO,MAC Source Address Low Bytes Register"
hexmask.long.byte 0x00 8.--15. 1. " MACSRCADDR0 ,MAC source address lower 8 bits (byte 0)"
hexmask.long.byte 0x00 0.--7. 1. " MACSRCADDR1 ,MAC source address bits 15-8 (byte 1)"
line.long 0x04 "MACSRCADDRHI,MAC Source Address High Bytes Register"
hexmask.long.byte 0x04 24.--31. 1. " MACSRCADDR2 ,MAC source address bits 23-16 (byte 2)"
hexmask.long.byte 0x04 16.--23. 1. " MACSRCADDR3 ,MAC source address bits 31-24 (byte 3)"
hexmask.long.byte 0x04 8.--15. 1. " MACSRCADDR4 ,MAC source address bits 39-32 (byte 4)"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " MACSRCADDR5 ,MAC source address bits 47-40 (byte 5)"
line.long 0x08 "MACHASH1,MAC Address Hash 1 Register"
line.long 0x0c "MACHASH2,MAC Address Hash 2 Register"
rgroup.long 0x1e0++0xf
line.long 0x00 "BOFFTEST,Backoff Test Register"
hexmask.long.word 0x00 16.--25. 1. " RNDNUM ,Backoff random number generator"
hexmask.long.byte 0x00 12.--15. 1. " COLLCOUNT ,Collision count"
hexmask.long.word 0x00 0.--9. 1. " TXBACKOFF ,Backoff count"
line.long 0x04 "TPACETEST,Transmit Pacing Test Register"
hexmask.long.byte 0x04 0.--4. 1. " PACEVAL ,Pacing register current value"
line.long 0x08 "RXPAUSE,Receive Pause Timer Register"
hexmask.long.word 0x08 0.--15. 1. " PAUSETIMER ,Pause timer value bits"
line.long 0x0c "TXPAUSE,Transmit Pause Timer Register"
hexmask.long.word 0x0c 0.--15. 1. " PAUSETIMER ,Pause timer value bits"
group.long 0x500++0xb
line.long 0x00 "MACADDRLO,MAC Address Low Bytes Register"
bitfld.long 0x00 20. " VALID ,Address valid" "Invalid,Valid"
bitfld.long 0x00 19. " MATCHFILT ,Match or filter" "Filtered,Matched"
bitfld.long 0x00 16.--18. " CHANNEL ,Channel" "0,1,2,3,4,5,6,7"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " MACADDR0 ,MAC address lower 8 bits (byte 0)"
hexmask.long.byte 0x00 0.--7. 1. " MACADDR1 ,MAC address bits 15-8 (byte 1)"
line.long 0x04 "MACADDRHI,MAC Address High Bytes Register"
hexmask.long.byte 0x04 24.--31. 1. " MACADDR2 ,MAC source address bits 23-16 (byte 2)"
hexmask.long.byte 0x04 16.--23. 1. " MACADDR3 ,MAC source address bits 31-24 (byte 3)"
hexmask.long.byte 0x04 8.--15. 1. " MACADDR4 ,MAC source address bits 39-32 (byte 4)"
textline " "
hexmask.long.byte 0x04 0.--7. 1. " MACADDR5 ,MAC source address bits 47-40 (byte 5)"
line.long 0x08 "MACINDEX,MAC Index Register"
hexmask.long.byte 0x08 0.--4. 1. " MACINDEX ,MAC address index"
group.long 0x600++0x1f
line.long 0x0 "TX0HDP,Transmit Channel 0 DMA Head Descriptor Pointer Register"
line.long 0x4 "TX1HDP,Transmit Channel 1 DMA Head Descriptor Pointer Register"
line.long 0x8 "TX2HDP,Transmit Channel 2 DMA Head Descriptor Pointer Register"
line.long 0xC "TX3HDP,Transmit Channel 3 DMA Head Descriptor Pointer Register"
line.long 0x10 "TX4HDP,Transmit Channel 4 DMA Head Descriptor Pointer Register"
line.long 0x14 "TX5HDP,Transmit Channel 5 DMA Head Descriptor Pointer Register"
line.long 0x18 "TX6HDP,Transmit Channel 6 DMA Head Descriptor Pointer Register"
line.long 0x1C "TX7HDP,Transmit Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x620++0x1f
line.long 0x0 "RX0HDP,Receive Channel 0 DMA Head Descriptor Pointer Register"
line.long 0x4 "RX1HDP,Receive Channel 1 DMA Head Descriptor Pointer Register"
line.long 0x8 "RX2HDP,Receive Channel 2 DMA Head Descriptor Pointer Register"
line.long 0xC "RX3HDP,Receive Channel 3 DMA Head Descriptor Pointer Register"
line.long 0x10 "RX4HDP,Receive Channel 4 DMA Head Descriptor Pointer Register"
line.long 0x14 "RX5HDP,Receive Channel 5 DMA Head Descriptor Pointer Register"
line.long 0x18 "RX6HDP,Receive Channel 6 DMA Head Descriptor Pointer Register"
line.long 0x1C "RX7HDP,Receive Channel 7 DMA Head Descriptor Pointer Register"
group.long 0x640++0x1f
line.long 0x0 "TX0CP,Transmit Channel 0 Completion Pointer Register"
line.long 0x4 "TX1CP,Transmit Channel 1 Completion Pointer Register"
line.long 0x8 "TX2CP,Transmit Channel 2 Completion Pointer Register"
line.long 0xC "TX3CP,Transmit Channel 3 Completion Pointer Register"
line.long 0x10 "TX4CP,Transmit Channel 4 Completion Pointer Register"
line.long 0x14 "TX5CP,Transmit Channel 5 Completion Pointer Register"
line.long 0x18 "TX6CP,Transmit Channel 6 Completion Pointer Register"
line.long 0x1C "TX7CP,Transmit Channel 7 Completion Pointer Register"
group.long 0x660++0x1f
line.long 0x0 "RX0CP,Receive Channel 0 Completion Pointer Register"
line.long 0x4 "RX1CP,Receive Channel 1 Completion Pointer Register"
line.long 0x8 "RX2CP,Receive Channel 2 Completion Pointer Register"
line.long 0xC "RX3CP,Receive Channel 3 Completion Pointer Register"
line.long 0x10 "RX4CP,Receive Channel 4 Completion Pointer Register"
line.long 0x14 "RX5CP,Receive Channel 5 Completion Pointer Register"
line.long 0x18 "RX6CP,Receive Channel 6 Completion Pointer Register"
line.long 0x1C "RX7CP,Receive Channel 7 Completion Pointer Register"
group.long 0x200++0x8f "Network Statistics Registers"
line.long 0x00 "RXGOODFRAMES,Good Receive Frames Register"
line.long 0x04 "RXBCASTFRAMES,Broadcast Receive Frames Register"
line.long 0x08 "RXMCASTFRAMES,Multicast Receive Frames Register"
line.long 0x0c "RXPAUSEFRAMES,Pause Receive Frames Register"
line.long 0x10 "RXCRCERRORS,Receive CRC Errors Register"
line.long 0x14 "RXALIGNCODEERRORS,Receive Alignment/Code Errors Register"
line.long 0x18 "RXOVERSIZED,Receive Oversized Frames Register"
line.long 0x1c "RXJABBER,Receive Jabber Frames Register"
line.long 0x20 "RXUNDERSIZED,Receive Undersized Frames Register"
line.long 0x24 "RXFRAGMENTS,Receive Frame Fragments Register"
line.long 0x28 "RXFILTERED,Filtered Receive Frames Register"
line.long 0x2c "RXQOSFILTERED,Receive QOS Filtered Frames Register"
line.long 0x30 "RXOCTETS,Receive Octet Frames Register"
line.long 0x34 "TXGOODFRAMES,Good Transmit Frames Register"
line.long 0x38 "TXBCASTFRAMES,Broadcast Transmit Frames Register"
line.long 0x3c "TXMCASTFRAMES,Multicast Transmit Frames Register"
line.long 0x40 "TXPAUSEFRAMES,Pause Transmit Frames Register"
line.long 0x44 "TXDEFERRED,Deferred Transmit Frames Register"
line.long 0x48 "TXCOLLISION,Collision Register"
line.long 0x4c "TXSINGLECOLL,Single Collision Transmit Frames Register"
line.long 0x50 "TXMULTICOLL,Multiple Collision Transmit Frames Register"
line.long 0x54 "TXEXCESSIVECOLL,Excessive Collisions Register"
line.long 0x58 "TXLATECOLL,Late Collisions Register"
line.long 0x5c "TXUNDERRUN,Transmit Underrun Register"
line.long 0x60 "TXCARRIERSENSE,Transmit Carrier Sense Errors Register"
line.long 0x64 "TXOCTETS,Transmit Octet Frames Register"
line.long 0x68 "FRAME64,Transmit and Receive 64 Octet Frames Register"
line.long 0x6c "FRAME65T127,Transmit and Receive 65 to 127 Octet Frames Register"
line.long 0x70 "FRAME128T255,Transmit and Receive 128 to 255 Octet Frames Register"
line.long 0x74 "FRAME256T511,Transmit and Receive 256 to 511 Octet Frames Register"
line.long 0x78 "FRAME512T1023,Transmit and Receive 512 to 1023 Octet Frames Register"
line.long 0x7c "FRAME1024TUP,Transmit and Receive 1024 or Above Octet Frames Register"
line.long 0x80 "NETOCTETS,Network Octet Frames Register"
line.long 0x84 "RXSOFOVERRUNS,Receive Start of Frame Overruns Register"
line.long 0x88 "RXMOFOVERRUNS,Receive Middle of Frame Overruns Register"
line.long 0x8c "RXDMAOVERRUNS,Receive DMA Overruns Register"
width 0xb
tree.end
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
tree "MDIO (Management Data Input/Output)"
base ad:0x4a120800
width 9.
rgroup.long 0x00++0x03
line.long 0x00 "REVID,MDIO Revision ID Register"
sif (cpuis("AM389*")||cpuis("C6A816*")||cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168"||cpu()=="DM8165DSP"||cpu()=="DM8166DSP"||cpu()=="DM8167DSP"||cpu()=="DM8168DSP"||cpuis("AM335*"))
hexmask.long.word 0x00 16.--31. 1. " MODID ,Type of peripheral"
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Major revision of peripheral"
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision of peripheral"
endif
group.long 0x04++0x7
line.long 0x00 "CONTROL,MDIO Control Register"
bitfld.long 0x00 31. " IDLE ,MDIO state machine IDLE status" "Busy,Idle"
bitfld.long 0x00 30. " ENABLE ,MDIO state machine enable control" "Disabled,Enabled"
hexmask.long.byte 0x00 24.--28. 1. " HUC ,Highest User-access Channel"
textline " "
bitfld.long 0x00 20. " PREAMBLE ,MDIO frame preamble disable" "No,Yes"
eventfld.long 0x00 19. " FAULT ,Fault indicator" "No failure,Failure"
bitfld.long 0x00 18. " FAULTENB ,Fault detect enable" "Disabled,Enabled"
textline " "
sif (cpu()=="OMAP3517"||cpu()=="OMAP3505"||cpuis("AM335*"))
bitfld.long 0x00 17. " INT_TEST_ENABLE ,Interrupt test enable" "Disabled,Enabled"
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
else
hexmask.long.word 0x00 0.--15. 1. " CLKDIV ,Clock divider"
endif
line.long 0x04 "ALIVE,MDIO PHY Alive Indication Register"
eventfld.long 0x04 31. " ALIVE[31] ,MDIO ALIVE bit 31" "Not acknowledged,Acknowledged"
eventfld.long 0x04 30. " ALIVE[30] ,MDIO ALIVE bit 30" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 29. " ALIVE[29] ,MDIO ALIVE bit 29" "Not acknowledged,Acknowledged"
eventfld.long 0x04 28. " ALIVE[28] ,MDIO ALIVE bit 28" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 27. " ALIVE[27] ,MDIO ALIVE bit 27" "Not acknowledged,Acknowledged"
eventfld.long 0x04 26. " ALIVE[26] ,MDIO ALIVE bit 26" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 25. " ALIVE[25] ,MDIO ALIVE bit 25" "Not acknowledged,Acknowledged"
eventfld.long 0x04 24. " ALIVE[24] ,MDIO ALIVE bit 24" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 23. " ALIVE[23] ,MDIO ALIVE bit 23" "Not acknowledged,Acknowledged"
eventfld.long 0x04 22. " ALIVE[22] ,MDIO ALIVE bit 22" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 21. " ALIVE[21] ,MDIO ALIVE bit 21" "Not acknowledged,Acknowledged"
eventfld.long 0x04 20. " ALIVE[20] ,MDIO ALIVE bit 20" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 19. " ALIVE[19] ,MDIO ALIVE bit 19" "Not acknowledged,Acknowledged"
eventfld.long 0x04 18. " ALIVE[18] ,MDIO ALIVE bit 18" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 17. " ALIVE[17] ,MDIO ALIVE bit 17" "Not acknowledged,Acknowledged"
eventfld.long 0x04 16. " ALIVE[16] ,MDIO ALIVE bit 16" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 15. " ALIVE[15] ,MDIO ALIVE bit 15" "Not acknowledged,Acknowledged"
eventfld.long 0x04 14. " ALIVE[14] ,MDIO ALIVE bit 14" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 13. " ALIVE[13] ,MDIO ALIVE bit 13" "Not acknowledged,Acknowledged"
eventfld.long 0x04 12. " ALIVE[12] ,MDIO ALIVE bit 12" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 11. " ALIVE[11] ,MDIO ALIVE bit 11" "Not acknowledged,Acknowledged"
eventfld.long 0x04 10. " ALIVE[10] ,MDIO ALIVE bit 10" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 9. " ALIVE[9] ,MDIO ALIVE bit 9" "Not acknowledged,Acknowledged"
eventfld.long 0x04 8. " ALIVE[8] ,MDIO ALIVE bit 8" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 7. " ALIVE[7] ,MDIO ALIVE bit 7" "Not acknowledged,Acknowledged"
eventfld.long 0x04 6. " ALIVE[6] ,MDIO ALIVE bit 6" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 5. " ALIVE[5] ,MDIO ALIVE bit 5" "Not acknowledged,Acknowledged"
eventfld.long 0x04 4. " ALIVE[4] ,MDIO ALIVE bit 4" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 3. " ALIVE[3] ,MDIO ALIVE bit 3" "Not acknowledged,Acknowledged"
eventfld.long 0x04 2. " ALIVE[2] ,MDIO ALIVE bit 2" "Not acknowledged,Acknowledged"
textline " "
eventfld.long 0x04 1. " ALIVE[1] ,MDIO ALIVE bit 1" "Not acknowledged,Acknowledged"
eventfld.long 0x04 0. " ALIVE[0] ,MDIO ALIVE bit 0" "Not acknowledged,Acknowledged"
rgroup.long 0x0c++0x3
line.long 0x00 "LINK,MDIO PHY Link Status Register"
bitfld.long 0x00 31. " LINK[31] ,MDIO link state bit 31" "No link,Link"
bitfld.long 0x00 30. " LINK[30] ,MDIO link state bit 30" "No link,Link"
bitfld.long 0x00 29. " LINK[29] ,MDIO link state bit 29" "No link,Link"
bitfld.long 0x00 28. " LINK[28] ,MDIO link state bit 28" "No link,Link"
textline " "
bitfld.long 0x00 27. " LINK[27] ,MDIO link state bit 27" "No link,Link"
bitfld.long 0x00 26. " LINK[26] ,MDIO link state bit 26" "No link,Link"
bitfld.long 0x00 25. " LINK[25] ,MDIO link state bit 25" "No link,Link"
bitfld.long 0x00 24. " LINK[24] ,MDIO link state bit 24" "No link,Link"
textline " "
bitfld.long 0x00 23. " LINK[23] ,MDIO link state bit 23" "No link,Link"
bitfld.long 0x00 22. " LINK[22] ,MDIO link state bit 22" "No link,Link"
bitfld.long 0x00 21. " LINK[21] ,MDIO link state bit 21" "No link,Link"
bitfld.long 0x00 20. " LINK[20] ,MDIO link state bit 20" "No link,Link"
textline " "
bitfld.long 0x00 19. " LINK[19] ,MDIO link state bit 19" "No link,Link"
bitfld.long 0x00 18. " LINK[18] ,MDIO link state bit 18" "No link,Link"
bitfld.long 0x00 17. " LINK[17] ,MDIO link state bit 17" "No link,Link"
bitfld.long 0x00 16. " LINK[16] ,MDIO link state bit 16" "No link,Link"
textline " "
bitfld.long 0x00 15. " LINK[15] ,MDIO link state bit 15" "No link,Link"
bitfld.long 0x00 14. " LINK[14] ,MDIO link state bit 14" "No link,Link"
bitfld.long 0x00 13. " LINK[13] ,MDIO link state bit 13" "No link,Link"
bitfld.long 0x00 12. " LINK[12] ,MDIO link state bit 12" "No link,Link"
textline " "
bitfld.long 0x00 11. " LINK[11] ,MDIO link state bit 11" "No link,Link"
bitfld.long 0x00 10. " LINK[10] ,MDIO link state bit 10" "No link,Link"
bitfld.long 0x00 9. " LINK[9] ,MDIO link state bit 9" "No link,Link"
bitfld.long 0x00 8. " LINK[8] ,MDIO link state bit 8" "No link,Link"
textline " "
bitfld.long 0x00 7. " LINK[7] ,MDIO link state bit 7" "No link,Link"
bitfld.long 0x00 6. " LINK[6] ,MDIO link state bit 6" "No link,Link"
bitfld.long 0x00 5. " LINK[5] ,MDIO link state bit 5" "No link,Link"
bitfld.long 0x00 4. " LINK[4] ,MDIO link state bit 4" "No link,Link"
textline " "
bitfld.long 0x00 3. " LINK[3] ,MDIO link state bit 3" "No link,Link"
bitfld.long 0x00 2. " LINK[2] ,MDIO link state bit 2" "No link,Link"
bitfld.long 0x00 1. " LINK[1] ,MDIO link state bit 1" "No link,Link"
bitfld.long 0x00 0. " LINK[0] ,MDIO link state bit 0" "No link,Link"
width 18.
group.long 0x10++0x7
line.long 0x00 "LINKINTRAW,MDIO Link Status Change Interrupt Register"
eventfld.long 0x00 1. " USERPHY1 ,MDIO link change event" "Not changed,Changed"
eventfld.long 0x00 0. " USERPHY0 ,MDIO link change event" "Not changed,Changed"
line.long 0x04 "LINKINTMASKED,MDIO Link Status Change Interrupt (Masked) Register"
eventfld.long 0x04 1. " USERPHY1 ,MDIO link change interrupt" "Not changed,Changed"
eventfld.long 0x04 0. " USERPHY0 ,MDIO link change interrupt" "Not changed,Changed"
group.long 0x20++0x3
line.long 0x00 "USERINTRAW,MDIO User Command Complete Interrupt Register"
eventfld.long 0x00 1. " USERACCESS1 ,MDIO user command complete event" "Not completed,Completed"
eventfld.long 0x00 0. " USERACCESS0 ,MDIO user command complete event" "Not completed,Completed"
group.long 0x24++0x03
line.long 0x00 "USERINTMASKED,MDIO User Command Complete Interrupt (Masked) Register"
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " USERACCESS1_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " USERACCESS0_set/clr ,Masked value of MDIO User command complete interrupt" "Not completed,Completed"
group.long 0x80++0x0f
line.long 0x00 "USERACCESS0,MDIO User Access Register 0"
bitfld.long 0x00 31. " GO ,GO bit" "No effect,MDIO accessed"
bitfld.long 0x00 30. " WRITE ,Write enable" "Read,Write"
textline " "
bitfld.long 0x00 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
hexmask.long.word 0x00 21.--25. 0x20 " REGADR ,Register address"
textline " "
hexmask.long.byte 0x00 16.--20. 1. " PHYADR ,PHY address"
hexmask.long.word 0x00 0.--15. 1. " DATA ,User data"
line.long 0x04 "USERPHYSEL0,MDIO User PHY Select Register 0"
bitfld.long 0x04 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
bitfld.long 0x04 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x04 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
line.long 0x08 "USERACCESS1,MDIO User Access Register 1"
bitfld.long 0x08 31. " GO ,GO bit" "No effect,MDIO accessed"
bitfld.long 0x08 30. " WRITE ,Write enable" "Read,Write"
textline " "
bitfld.long 0x08 29. " ACK ,Acknowledge bit" "No acknowledge,Acknowledge"
hexmask.long.word 0x08 21.--25. 0x20 " REGADR ,Register address"
textline " "
hexmask.long.byte 0x08 16.--20. 1. " PHYADR ,PHY address"
hexmask.long.word 0x08 0.--15. 1. " DATA ,User data"
line.long 0x0c "USERPHYSEL1,MDIO User PHY Select Register 1"
bitfld.long 0x0c 7. " LINKSEL ,Link status determination select" "Determined,Not supported"
bitfld.long 0x0c 6. " LINKINTENB ,Link change interrupt enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x0c 0.--4. 1. " PHYADDRMON ,PHY address whose link status is to be monitored"
width 0xb
tree.end
endif
tree.end
tree.end
tree.open "EMIF 4 Registers"
tree "DDR2/DDR3 Memory Controller Registers"
tree "DDR 0"
base ad:0x4C000000
width 9.
rgroup.long 0x04++0x03
line.long 0x00 "SDRSTAT,SDRAM Status Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 31. " BE ,Memory controller endian mode" "Little endian,?..."
bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual clock mode" "Not sync,Sync"
textline " "
bitfld.long 0x00 29. " FAST_INIT ,Fast initialization enable" "Disabled,Enabled"
bitfld.long 0x00 2. " PHY_DLL_READY ,DDR PHY Ready" "Not ready,Ready"
else
bitfld.long 0x00 0. " PHYRDY ,DDR PHY" "Not ready,Ready"
endif
if ((d.l(ad:0x4C000000+0x08)&0xE0000000)==0x40000000)
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
bitfld.long 0x00 27.--28. " IBANKPOS ,Internal Bank position selection" "IBANK EBANK PAGESIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE"
bitfld.long 0x00 24.--26. " DDRTERM ,DDR2 and DDR3 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
textline " "
bitfld.long 0x00 23. " DDQS ,DDR2 Differential DQS Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " DLL ,Disable DLL Select" "Enabled,Disabled"
textline " "
bitfld.long 0x00 18.--19. " DRIVE ,DDR2/3 Drive strength" "Full,Reduced,?..."
bitfld.long 0x00 14.--15. " NM ,Data Bus Width" "32 bits,16 bits,?..."
textline " "
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,7,?..."
bitfld.long 0x00 7.--9. " RSIZE ,Row Size Selection" "9 Rows,10 Rows,11 Rows,12 Rows,13 Rows,14 Rows,15 Rows,?..."
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 Bank,2 Bank,4 Bank,8 Bank,?..."
textline " "
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0 & CS1"
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 word / 8 column address,512 word/9 column address,1024 word/10 column address,2048 word/11 column address,?..."
elif ((d.l(ad:0x4C000000+0x08)&0xE0000000)==0x60000000)
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
bitfld.long 0x00 27.--28. " IBANKPOS ,Internal Bank position selection" "IBANK EBANK PAGESIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 24.--26. " DDRTERM ,DDR3 termination resistor value" "Disabled,RZQ/4,?..."
else
bitfld.long 0x00 24.--26. " DDRTERM ,DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
endif
textline " "
bitfld.long 0x00 21.--22. " DYNODT ,DDR3 Dynamic ODT" "Off,RZQ/4,RZQ/2,?..."
bitfld.long 0x00 20. " DLL ,Disable DLL Select" "Enabled,Disabled"
textline " "
bitfld.long 0x00 18.--19. " DRIVE ,DDR3 Drive strength" "RZQ/6,RZQ/7,?..."
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
bitfld.long 0x00 14.--15. " NM ,Data Bus Width" "32 bits,16 bits,?..."
textline " "
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,10,Reserved,10,Reserved,11,?..."
bitfld.long 0x00 7.--9. " RSIZE ,Row Size Selection" "9 Rows,10 Rows,11 Rows,12 Rows,13 Rows,14 Rows,15 Rows,?..."
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 Bank,2 Bank,4 Bank,8 Bank,?..."
textline " "
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0 & CS1"
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 word / 8 column address,512 word/9 column address,1024 word/10 column address,2048 word/11 column address,?..."
else
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
textline " "
textline " "
textline " "
textline " "
endif
group.long 0x0C++0x03
line.long 0x00 "SDRCR2,SDRAM Configuration Register 2"
bitfld.long 0x00 27. " EBANK_POS ,External Bank Position" "Lower OCP,Higher OCP"
group.long 0x10++0x03
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self-Refresh Temperature Range" "Normal,Extended"
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
hexmask.long.word 0x00 0.--15. 1. " RR ,Refresh rate"
else
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Reserved,Enabled"
hexmask.long.word 0x00 0.--15. 1. " RR ,Refresh rate"
endif
group.long 0x14++0x03
line.long 0x00 "SDRRCSR,SDRAM Refresh Control Shadow Register"
hexmask.long.word 0x00 0.--15. 1. " RR_SHDW ,Shadow field for RR in SDRRCR"
group.long 0x18++0x07
line.long 0x00 "SDRTIM1,SDRAM Timing 1 Register"
bitfld.long 0x00 25.--28. " T_RP ,T_RP = (tRP/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21.--24. " T_RCD ,T_RCD = (tRCD/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17.--20. " T_WR ,T_WR = (tWR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--16. " T_RAS ,T_RAS = (tRAS/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6.--11. " T_RC ,T_RC = (tRC/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 3.--5. " T_RRD ,T_RRD = (tRRD/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 0.--2. " T_WTR ,T_WTR = (tWTR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
line.long 0x04 "SDRTIM1SR,SDRAM Timing 1 Shadow Register"
bitfld.long 0x04 25.--28. " T_RP_SHDW ,Shadow field for T_RP in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 17.--20. " T_WR_SHDW ,Shadow field for T_WR in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x04 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--11. " T_RC_SHDW ,Shadow field for T_RC in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD in SDRTIMR1" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x04 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR in SDRTIMR1" "0,1,2,3,4,5,6,7"
group.long 0x20++0x07
line.long 0x00 "SDRTIM2,SDRAM Timing 2 Register"
bitfld.long 0x00 28.--30. " T_XP ,Specifies the minimum number of DDR[x]_CLK[y] cycles" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--24. 1. " T_XSNR ,Calculated by T_XSNR = (tXSNR/DDR[x]_CLK[y] period) - 1"
hexmask.long.word 0x00 6.--15. 1. " T_XSRD ,Calculated by T_XSRD = (tXSRD or tXSDLL) - 1"
textline " "
bitfld.long 0x00 3.--5. " T_RTP ,Calculated by T_RTP = (tRTP/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " T_CKE ,Calculated by T_CKE = (tCKE/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
line.long 0x04 "SDRTIM2SR,SDRAM Timing 2 Shadow Register"
bitfld.long 0x04 29.--30. " T_XP_SHDW ,Shadow field for T_XP in SDRTIMR2" "0,1,2,3"
hexmask.long.word 0x04 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR in SDRTIMR2"
hexmask.long.word 0x04 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD in SDRTIMR2"
textline " "
bitfld.long 0x04 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP in SDRTIMR2" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE in SDRTIMR2" "0,1,2,3,4,5,6,7"
if ((d.l(ad:0x4C000000+0x08)&0xE0000000)==0x40000000)
group.long 0x28++0x07
line.long 0x00 "SDRTIM3,SDRAM Timing 3 Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 28.--31. " T_PDLL_UL ,Number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,128,256,384,512,640,768,896,?..."
bitfld.long 0x00 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between W-to-W or R-to-R data phases to different chip selects" "0,1,2,3,4,5,6,7,?..."
else
bitfld.long 0x00 21.--23. " T_CKESR ,Calculated by T_CKESR = (tCKESR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
endif
textline " "
hexmask.long.word 0x00 4.--12. 1. " T_RFC ,Calculated by T_RFC = (tRFC/DDR[x]_CLK[y] period) - 1"
bitfld.long 0x00 0.--3. " T_RASMAX ,Specifies the maximum number of refresh rate intervals from Active to Precharge command." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
bitfld.long 0x04 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR in SDRTIMR3" "0,1,2,3,4,5,6,7"
textline " "
hexmask.long.word 0x04 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
bitfld.long 0x04 0.--3. " T_RASMAX_SHDW ,Shadow field for T_RASMAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x28++0x07
line.long 0x00 "SDRTIM3,SDRAM Timing 3 Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 28.--31. " T_PDLL_UL ,Number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between W-to-W or R-to-R data phases to different chip selects" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 15.--20. " T_ZQCS ,Specifies the minimum number of DDR[x]_CLK[y] cycles for ZQCS command," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
bitfld.long 0x00 21.--23. " T_CKESR ,Calculated by T_CKESR = (tCKESR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--20. " T_ZQCS ,Specifies the minimum number of DDR[x]_CLK[y] cycles for ZQCS command," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
textline " "
hexmask.long.word 0x00 4.--12. 1. " T_RFC ,Calculated by T_RFC = (tRFC/DDR[x]_CLK[y] period) - 1"
bitfld.long 0x00 0.--3. " T_RASMAX ,Specifies the maximum number of refresh rate intervals from Active to Precharge command." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
bitfld.long 0x04 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR in SDRTIMR3" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15.--20. " T_ZQCS_SHDW ,Shadow field for T_ZQCS in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
hexmask.long.word 0x04 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
bitfld.long 0x04 0.--3. " T_RASMAX_SHDW ,Shadow field for T_RASMAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x38++0x07
line.long 0x00 "PMCR,Power Management Control Register"
bitfld.long 0x00 12.--15. " PD_TIM ,Power Management timer for Power Down" "Power down Mode,16 DDR cycles,32 DDR cycles,64 DDR cycles,128 DDR cycles,256 DDR cycles,512 DDR cycles,1024 DDR cycles,2048 DDR cycles,4096 DDR cycles,8192 DDR cycles,16384 DDR cycles,32768 DDR cycles,65536 DDR cycles,131072 DDR cycles,262144 DDR cycles"
bitfld.long 0x00 11. " DP_DEN ,Deep Power Down Enable" "Normal Operation,Overrides LP_MODE"
bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management Enable" "Disabled,Clock Stop,Self Refresh,Disabled,Power Down,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 4.--7. " SR_TIM ,Power Management timer for Self Refresh" "Self Refresh Mode,16 DDR clocks,32 DDR clocks,64 DDR clocks,128 DDR clocks,256 DDR clocks,512 DDR clocks,1024 DDR clocks,2048 DDR clocks,4096 DDR clocks,8192 DDR clocks,16384 DDR clocks,32768 DDR clocks,65536 DDR clocks,131072 DDR clocks,262144 DDR clocks"
bitfld.long 0x00 0.--3. " CS_TIM ,Power Management timer for Clock Stop" "Clock Stop Mode,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks"
line.long 0x04 "PMCSR,Power Management Control Shadow Register"
bitfld.long 0x04 12.--15. " PD_TIM_SHDW ,PD_TIM_SHDW" "Power down Mode,16 DDR cycles,32 DDR cycles,64 DDR cycles,128 DDR cycles,256 DDR cycles,512 DDR cycles,1024 DDR cycles,2048 DDR cycles,4096 DDR cycles,8192 DDR cycles,16384 DDR cycles,32768 DDR cycles,65536 DDR cycles,131072 DDR cycles,262144 DDR cycles"
bitfld.long 0x04 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM in PMCR" "Self Refresh Mode,16 DDR clocks,32 DDR clocks,64 DDR clocks,128 DDR clocks,256 DDR clocks,512 DDR clocks,1024 DDR clocks,2048 DDR clocks,4096 DDR clocks,8192 DDR clocks,16384 DDR clocks,32768 DDR clocks,65536 DDR clocks,131072 DDR clocks,262144 DDR clocks"
bitfld.long 0x04 0.--3. " CS_TIM_SHDW ,Shadow field for CS_TIM in PMCR" "Clock Stop Mode,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks"
group.long 0x54++0x03
line.long 0x00 "PBBPR,Peripheral Bus Burst Priority Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1"
hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2"
textline " "
endif
hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority raise old counter"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
width 14.
rgroup.long 0x80++0x07
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
group.long 0x88++0x07
line.long 0x00 "PERF_CNT_CFG,Performance Counter Config Register"
bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "Count total SDRAM accesses,Count total SDRAM activates,Count total reads,Count total writes,?..."
textline " "
bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "Count total SDRAM accesses,Count total SDRAM activates,Count total reads,Count total writes,?..."
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
hexmask.long.byte 0x04 24.--31. 0x1 " MCONNID2 ,MConnID for Performance Counter2 register"
hexmask.long.byte 0x04 8.--15. 0x1 " MCONNID1 ,MConnID for Performance Counter1 register"
width 9.
endif
group.long 0xA0++0x03
line.long 0x00 "EOI,End of Interrupt Register"
bitfld.long 0x00 0. " EOI ,Software End of Interrupt Control" "System OCP Interrupt,?..."
wgroup.long 0xA4++0x03
line.long 0x00 "SOIRSR,System OCP Interrup RAW Status Register"
bitfld.long 0x00 0. " ERRSYS ,Raw status of system OCP interrupt for command or address error" "No effect,Set"
group.long 0xAC++0x03
line.long 0x00 "SOISR,Sytem OCP Interrupt Status Register"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " ERRSYS_set/clr ,Status of system OCP interrupt for SDRAM command or address error" "Disabled,Enabled"
group.long 0xC8++0x03
line.long 0x00 "ZQCR,SDRAM Output Impedance Calibration Configuration Register"
bitfld.long 0x00 31. " CS1EN ,Enables ZQ calibration for CS1" "Disabled,Enabled"
bitfld.long 0x00 30. " CS0EN ,Enables ZQ calibration for CS0" "Disabled,Enabled"
bitfld.long 0x00 29. " DUALCALEN ,ZQ Dual Calibration Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " SEFXITEN ,ZQCL on Self-Refresh - Active Power Down and Prechare Power-Down exit enable" "Disabled,Enabled"
bitfld.long 0x00 18.--19. " ZQINITMULT ,Indicates number of ZQCL intervals that make up a ZQINIT interval" "0,1,2,3"
bitfld.long 0x00 16.--17. " ZQCLMULT ,Indicates number of ZQCS intervals that make up a ZQCL interva" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " REFINTERVAL ,Number of refresh periods between ZQCS commands"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0xDC++0x03
line.long 0x00 "RWLCR,Read-Write Leveling Control Register"
bitfld.long 0x00 31. " RDWRLVLFULL_START ,Full leveling trigger" "Cleared,Started"
endif
if ((d.l(ad:0x4C000000+0x08)&0xE0000000)==0x60000000)
group.long 0xE4++0x07
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Enable IO receiver dynamic powerdown when not performing a read" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 18. " RDEYE_LVL_DIS ,Read eye auto-leveling disable" "No,Yes"
bitfld.long 0x00 17. " GATE_LVL_DIS ,Read gate auto-leveling disable" "No,Yes"
textline " "
bitfld.long 0x00 16. " WR_LVL_DIS ,Write auto-leveling disable" "No,Yes"
bitfld.long 0x00 15. " PHY_RST ,DDR PHY reset" "Not reset,Reset"
textline " "
bitfld.long 0x00 12.--13. " ID_LODT ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x00 8.--9. " RD_LODT ,Select controller termination during read accesses" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x00 0.--4. " RL ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
bitfld.long 0x04 20. " EN_DYN_PWRDN_SHDW ,Shadow field for EN_DYN_PWRDN in DDRPHYCR" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 18. " RDEYE_LVL_DIS_SHDW ,Read eye auto-leveling disable" "No,Yes"
bitfld.long 0x00 17. " GATE_LVL_DIS_SHDW ,Read gate auto-leveling disable" "No,Yes"
textline " "
bitfld.long 0x00 16. " WR_LVL_DIS_SHDW ,Write auto-leveling disable" "No,Yes"
bitfld.long 0x00 12.--13. " ID_LODT_SHDW ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x04 8.--9. " RD_LODT_SHDW ,Shadow field for RD_LODT in DDRPHYCR" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x04 0.--4. " RL_SHDW ,Shadow field for RL in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
else
group.long 0xE4++0x07
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Enable IO receiver dynamic powerdown when not performing a read" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 15. " PHY_RST ,DDR PHY reset" "Not reset,Reset"
bitfld.long 0x00 12.--13. " ID_LODT ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x00 8.--9. " RD_LODT ,Select controller termination during read accesses" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x00 0.--4. " RL ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
bitfld.long 0x04 20. " EN_DYN_PWRDN_SHDW ,Shadow field for EN_DYN_PWRDN in DDRPHYCR" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 12.--13. " ID_LODT_SHDW ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x04 8.--9. " RD_LODT_SHDW ,Shadow field for RD_LODT in DDRPHYCR" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x04 0.--4. " RL_SHDW ,Shadow field for RL in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
width 18.
group.long 0x100++0x0B
line.long 0x00 "PRI_COS_MAP,Priority to Class of Service Mapping Register"
bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Priority to class of service mapping enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "Not assigned,Class 1,Class 2,Not assigned"
textline " "
bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "Not assigned,Class 1,Class 2,Not assigned"
textline " "
bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "Not assigned,Class 1,Class 2,Not assigned"
line.long 0x04 "CONNID_COS_1_MAP,Connection ID to Class of Service 1 Mapping Register"
bitfld.long 0x04 31. " CONNID_COS_1_MAP_EN ,Connection ID to class of service mapping enable" "Disabled,Enabled"
hexmask.long.byte 0x04 23.--30. 0x1 " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1"
bitfld.long 0x04 20.--22. " MSK_1_COS_1 ,Mask for connection ID value 1 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0,Bits 3:0,Bits 4:0,Bits 5:0,Bits 6:0"
textline " "
hexmask.long.byte 0x04 12.--19. 0x1 " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1"
bitfld.long 0x04 10.--11. " MSK_2_COS_1 ,Mask for connection ID value 2 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
textline " "
hexmask.long.byte 0x04 2.--9. 0x1 " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1"
bitfld.long 0x04 0.--1. " MSK_3_COS_1 ,Mask for connection ID value 3 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
line.long 0x08 "CONNID_COS_2_MAP,Connection ID to Class of Service 2 Mapping Register"
bitfld.long 0x08 31. " CONNID_COS_2_MAP_EN ,Connection ID to class of service mapping enable" "Disabled,Enabled"
hexmask.long.byte 0x08 23.--30. 0x1 " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2"
bitfld.long 0x08 20.--22. " MSK_1_COS_2 ,Mask for connection ID value 1 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0,Bits 3:0,Bits 4:0,Bits 5:0,Bits 6:0"
textline " "
hexmask.long.byte 0x08 12.--19. 0x1 " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2"
bitfld.long 0x08 10.--11. " MSK_2_COS_2 ,Mask for connection ID value 2 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
textline " "
hexmask.long.byte 0x08 2.--9. 0x1 " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2"
bitfld.long 0x08 0.--1. " MSK_3_COS_2 ,Mask for connection ID value 3 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
group.long 0x120++0x03
line.long 0x00 "RD_WR_EXEC_THRSH,Read Write Execution Threshold Register"
bitfld.long 0x00 8.--12. " WR_THRSH ,Write threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RD_THRSH ,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
width 0xB
tree.end
tree "DDR 1"
base ad:0x4D000000
width 9.
rgroup.long 0x04++0x03
line.long 0x00 "SDRSTAT,SDRAM Status Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 31. " BE ,Memory controller endian mode" "Little endian,?..."
bitfld.long 0x00 30. " DUAL_CLK_MODE ,Dual clock mode" "Not sync,Sync"
textline " "
bitfld.long 0x00 29. " FAST_INIT ,Fast initialization enable" "Disabled,Enabled"
bitfld.long 0x00 2. " PHY_DLL_READY ,DDR PHY Ready" "Not ready,Ready"
else
bitfld.long 0x00 0. " PHYRDY ,DDR PHY" "Not ready,Ready"
endif
if ((d.l(ad:0x4D000000+0x08)&0xE0000000)==0x40000000)
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
bitfld.long 0x00 27.--28. " IBANKPOS ,Internal Bank position selection" "IBANK EBANK PAGESIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE"
bitfld.long 0x00 24.--26. " DDRTERM ,DDR2 and DDR3 termination resistor value" "Disabled,75 Ohm,150 Ohm,50 Ohm,?..."
textline " "
bitfld.long 0x00 23. " DDQS ,DDR2 Differential DQS Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " DLL ,Disable DLL Select" "Enabled,Disabled"
textline " "
bitfld.long 0x00 18.--19. " DRIVE ,DDR2/3 Drive strength" "Full,Reduced,?..."
bitfld.long 0x00 14.--15. " NM ,Data Bus Width" "32 bits,16 bits,?..."
textline " "
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,2,3,4,5,6,7,?..."
bitfld.long 0x00 7.--9. " RSIZE ,Row Size Selection" "9 Rows,10 Rows,11 Rows,12 Rows,13 Rows,14 Rows,15 Rows,?..."
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 Bank,2 Bank,4 Bank,8 Bank,?..."
textline " "
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0 & CS1"
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 word / 8 column address,512 word/9 column address,1024 word/10 column address,2048 word/11 column address,?..."
elif ((d.l(ad:0x4D000000+0x08)&0xE0000000)==0x60000000)
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
bitfld.long 0x00 27.--28. " IBANKPOS ,Internal Bank position selection" "IBANK EBANK PAGESIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE,IBANK EBANK PAGESIZE RSIZE"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 24.--26. " DDRTERM ,DDR3 termination resistor value" "Disabled,RZQ/4,?..."
else
bitfld.long 0x00 24.--26. " DDRTERM ,DDR3 termination resistor value" "Disabled,RZQ/4,RZQ/2,RZQ/6,RZQ/12,RZQ/8,?..."
endif
textline " "
bitfld.long 0x00 21.--22. " DYNODT ,DDR3 Dynamic ODT" "Off,RZQ/4,RZQ/2,?..."
bitfld.long 0x00 20. " DLL ,Disable DLL Select" "Enabled,Disabled"
textline " "
bitfld.long 0x00 18.--19. " DRIVE ,DDR3 Drive strength" "RZQ/6,RZQ/7,?..."
bitfld.long 0x00 16.--17. " CWL ,DDR3 CAS Write Latency" "5,6,7,8"
bitfld.long 0x00 14.--15. " NM ,Data Bus Width" "32 bits,16 bits,?..."
textline " "
bitfld.long 0x00 10.--13. " CL ,CAS Latency" "Reserved,Reserved,5,Reserved,6,Reserved,7,Reserved,8,Reserved,10,Reserved,10,Reserved,11,?..."
bitfld.long 0x00 7.--9. " RSIZE ,Row Size Selection" "9 Rows,10 Rows,11 Rows,12 Rows,13 Rows,14 Rows,15 Rows,?..."
bitfld.long 0x00 4.--6. " IBANK ,Bank Selection" "1 Bank,2 Bank,4 Bank,8 Bank,?..."
textline " "
bitfld.long 0x00 3. " EBANK ,Chip Selection" "CS0,CS0 & CS1"
bitfld.long 0x00 0.--2. " PAGESIZE ,Page Size Selection" "256 word / 8 column address,512 word/9 column address,1024 word/10 column address,2048 word/11 column address,?..."
else
group.long 0x08++0x03
line.long 0x00 "SDRCR,SDRAM Configuration Register"
bitfld.long 0x00 29.--31. " MEMTYPE ,SDRAM Type Selection" "Reserved,Reserved,DDR2,DDR3,?..."
textline " "
textline " "
textline " "
textline " "
endif
group.long 0x0C++0x03
line.long 0x00 "SDRCR2,SDRAM Configuration Register 2"
bitfld.long 0x00 27. " EBANK_POS ,External Bank Position" "Lower OCP,Higher OCP"
group.long 0x10++0x03
line.long 0x00 "SDRRCR,SDRAM Refresh Control Register"
bitfld.long 0x00 31. " INITREF_DIS ,Initialization and Refresh Disable" "No,Yes"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 29. " SRT ,DDR2 and DDR3 Self-Refresh Temperature Range" "Normal,Extended"
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24.--26. " PASR ,Partial Array Self Refresh" "Full,1/2,1/4,1/8,3/4,1/2,1/4,1/8"
hexmask.long.word 0x00 0.--15. 1. " RR ,Refresh rate"
else
bitfld.long 0x00 28. " ASR ,DDR3 Auto Self Refresh Enable" "Reserved,Enabled"
hexmask.long.word 0x00 0.--15. 1. " RR ,Refresh rate"
endif
group.long 0x14++0x03
line.long 0x00 "SDRRCSR,SDRAM Refresh Control Shadow Register"
hexmask.long.word 0x00 0.--15. 1. " RR_SHDW ,Shadow field for RR in SDRRCR"
group.long 0x18++0x07
line.long 0x00 "SDRTIM1,SDRAM Timing 1 Register"
bitfld.long 0x00 25.--28. " T_RP ,T_RP = (tRP/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 21.--24. " T_RCD ,T_RCD = (tRCD/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 17.--20. " T_WR ,T_WR = (tWR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 12.--16. " T_RAS ,T_RAS = (tRAS/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6.--11. " T_RC ,T_RC = (tRC/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 3.--5. " T_RRD ,T_RRD = (tRRD/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 0.--2. " T_WTR ,T_WTR = (tWTR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
line.long 0x04 "SDRTIM1SR,SDRAM Timing 1 Shadow Register"
bitfld.long 0x04 25.--28. " T_RP_SHDW ,Shadow field for T_RP in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 21.--24. " T_RCD_SHDW ,Shadow field for T_RCD in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 17.--20. " T_WR_SHDW ,Shadow field for T_WR in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x04 12.--16. " T_RAS_SHDW ,Shadow field for T_RAS in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--11. " T_RC_SHDW ,Shadow field for T_RC in SDRTIMR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 3.--5. " T_RRD_SHDW ,Shadow field for T_RRD in SDRTIMR1" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x04 0.--2. " T_WTR_SHDW ,Shadow field for T_WTR in SDRTIMR1" "0,1,2,3,4,5,6,7"
group.long 0x20++0x07
line.long 0x00 "SDRTIM2,SDRAM Timing 2 Register"
bitfld.long 0x00 28.--30. " T_XP ,Specifies the minimum number of DDR[x]_CLK[y] cycles" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x00 16.--24. 1. " T_XSNR ,Calculated by T_XSNR = (tXSNR/DDR[x]_CLK[y] period) - 1"
hexmask.long.word 0x00 6.--15. 1. " T_XSRD ,Calculated by T_XSRD = (tXSRD or tXSDLL) - 1"
textline " "
bitfld.long 0x00 3.--5. " T_RTP ,Calculated by T_RTP = (tRTP/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. " T_CKE ,Calculated by T_CKE = (tCKE/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
line.long 0x04 "SDRTIM2SR,SDRAM Timing 2 Shadow Register"
bitfld.long 0x04 29.--30. " T_XP_SHDW ,Shadow field for T_XP in SDRTIMR2" "0,1,2,3"
hexmask.long.word 0x04 16.--24. 1. " T_XSNR_SHDW ,Shadow field for T_XSNR in SDRTIMR2"
hexmask.long.word 0x04 6.--15. 1. " T_XSRD_SHDW ,Shadow field for T_XSRD in SDRTIMR2"
textline " "
bitfld.long 0x04 3.--5. " T_RTP_SHDW ,Shadow field for T_RTP in SDRTIMR2" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. " T_CKE_SHDW ,Shadow field for T_CKE in SDRTIMR2" "0,1,2,3,4,5,6,7"
if ((d.l(ad:0x4D000000+0x08)&0xE0000000)==0x40000000)
group.long 0x28++0x07
line.long 0x00 "SDRTIM3,SDRAM Timing 3 Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 28.--31. " T_PDLL_UL ,Number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,128,256,384,512,640,768,896,?..."
bitfld.long 0x00 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between W-to-W or R-to-R data phases to different chip selects" "0,1,2,3,4,5,6,7,?..."
else
bitfld.long 0x00 21.--23. " T_CKESR ,Calculated by T_CKESR = (tCKESR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
endif
textline " "
hexmask.long.word 0x00 4.--12. 1. " T_RFC ,Calculated by T_RFC = (tRFC/DDR[x]_CLK[y] period) - 1"
bitfld.long 0x00 0.--3. " T_RASMAX ,Specifies the maximum number of refresh rate intervals from Active to Precharge command." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
bitfld.long 0x04 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR in SDRTIMR3" "0,1,2,3,4,5,6,7"
textline " "
hexmask.long.word 0x04 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
bitfld.long 0x04 0.--3. " T_RASMAX_SHDW ,Shadow field for T_RASMAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
else
group.long 0x28++0x07
line.long 0x00 "SDRTIM3,SDRAM Timing 3 Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 28.--31. " T_PDLL_UL ,Number of DDR[X]_CLK cycles for PHY DLL to unlock" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 24.--27. " T_CSTA ,Mimimum number of DDR[X]_CLK cycles between W-to-W or R-to-R data phases to different chip selects" "0,1,2,3,4,5,6,7,?..."
bitfld.long 0x00 15.--20. " T_ZQCS ,Specifies the minimum number of DDR[x]_CLK[y] cycles for ZQCS command," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
bitfld.long 0x00 21.--23. " T_CKESR ,Calculated by T_CKESR = (tCKESR/DDR[x]_CLK[y] period) - 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 15.--20. " T_ZQCS ,Specifies the minimum number of DDR[x]_CLK[y] cycles for ZQCS command," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
textline " "
hexmask.long.word 0x00 4.--12. 1. " T_RFC ,Calculated by T_RFC = (tRFC/DDR[x]_CLK[y] period) - 1"
bitfld.long 0x00 0.--3. " T_RASMAX ,Specifies the maximum number of refresh rate intervals from Active to Precharge command." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "SDRTIM3SR,SDRAM Timing 3 Shadow Register"
bitfld.long 0x04 21.--23. " T_CKESR_SHDW ,Shadow field for T_CKESR in SDRTIMR3" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15.--20. " T_ZQCS_SHDW ,Shadow field for T_ZQCS in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
hexmask.long.word 0x04 4.--12. 1. " T_RFC_SHDW ,Shadow field for T_RFC in SDRTIMR3"
bitfld.long 0x04 0.--3. " T_RASMAX_SHDW ,Shadow field for T_RASMAX in SDRTIMR3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x38++0x07
line.long 0x00 "PMCR,Power Management Control Register"
bitfld.long 0x00 12.--15. " PD_TIM ,Power Management timer for Power Down" "Power down Mode,16 DDR cycles,32 DDR cycles,64 DDR cycles,128 DDR cycles,256 DDR cycles,512 DDR cycles,1024 DDR cycles,2048 DDR cycles,4096 DDR cycles,8192 DDR cycles,16384 DDR cycles,32768 DDR cycles,65536 DDR cycles,131072 DDR cycles,262144 DDR cycles"
bitfld.long 0x00 11. " DP_DEN ,Deep Power Down Enable" "Normal Operation,Overrides LP_MODE"
bitfld.long 0x00 8.--10. " LP_MODE ,Automatic Power Management Enable" "Disabled,Clock Stop,Self Refresh,Disabled,Power Down,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x00 4.--7. " SR_TIM ,Power Management timer for Self Refresh" "Self Refresh Mode,16 DDR clocks,32 DDR clocks,64 DDR clocks,128 DDR clocks,256 DDR clocks,512 DDR clocks,1024 DDR clocks,2048 DDR clocks,4096 DDR clocks,8192 DDR clocks,16384 DDR clocks,32768 DDR clocks,65536 DDR clocks,131072 DDR clocks,262144 DDR clocks"
bitfld.long 0x00 0.--3. " CS_TIM ,Power Management timer for Clock Stop" "Clock Stop Mode,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks"
line.long 0x04 "PMCSR,Power Management Control Shadow Register"
bitfld.long 0x04 12.--15. " PD_TIM_SHDW ,PD_TIM_SHDW" "Power down Mode,16 DDR cycles,32 DDR cycles,64 DDR cycles,128 DDR cycles,256 DDR cycles,512 DDR cycles,1024 DDR cycles,2048 DDR cycles,4096 DDR cycles,8192 DDR cycles,16384 DDR cycles,32768 DDR cycles,65536 DDR cycles,131072 DDR cycles,262144 DDR cycles"
bitfld.long 0x04 4.--7. " SR_TIM_SHDW ,Shadow field for SR_TIM in PMCR" "Self Refresh Mode,16 DDR clocks,32 DDR clocks,64 DDR clocks,128 DDR clocks,256 DDR clocks,512 DDR clocks,1024 DDR clocks,2048 DDR clocks,4096 DDR clocks,8192 DDR clocks,16384 DDR clocks,32768 DDR clocks,65536 DDR clocks,131072 DDR clocks,262144 DDR clocks"
bitfld.long 0x04 0.--3. " CS_TIM_SHDW ,Shadow field for CS_TIM in PMCR" "Clock Stop Mode,16 clocks,32 clocks,64 clocks,128 clocks,256 clocks,512 clocks,1024 clocks,2048 clocks,4096 clocks,8192 clocks,16384 clocks,32768 clocks,65536 clocks,131072 clocks,262144 clocks"
group.long 0x54++0x03
line.long 0x00 "PBBPR,Peripheral Bus Burst Priority Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
hexmask.long.byte 0x00 16.--23. 1. " COS_COUNT_1 ,Priority Raise Counter for class of service 1"
hexmask.long.byte 0x00 8.--15. 1. " COS_COUNT_2 ,Priority Raise Counter for class of service 2"
textline " "
endif
hexmask.long.byte 0x00 0.--7. 1. " PR_OLD_COUNT ,Priority raise old counter"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
width 14.
rgroup.long 0x80++0x07
line.long 0x00 "PERF_CNT_1,Performance Counter 1 Register"
line.long 0x04 "PERF_CNT_2,Performance Counter 2 Register"
group.long 0x88++0x07
line.long 0x00 "PERF_CNT_CFG,Performance Counter Config Register"
bitfld.long 0x00 31. " CNTR2_MCONNID_EN ,MConnID filter enable for Performance Counter 2 register" "Disabled,Enabled"
bitfld.long 0x00 16.--19. " CNTR2_CFG ,Filter configuration for Performance Counter 2" "Count total SDRAM accesses,Count total SDRAM activates,Count total reads,Count total writes,?..."
textline " "
bitfld.long 0x00 15. " CNTR1_MCONNID_EN ,MConnID filter enable for Performance Counter 1 register" "Disabled,Enabled"
bitfld.long 0x00 0.--3. " CNTR1_CFG ,Filter configuration for Performance Counter 1" "Count total SDRAM accesses,Count total SDRAM activates,Count total reads,Count total writes,?..."
line.long 0x04 "PERF_CNT_SEL,Performance Counter Master Region Select Register"
hexmask.long.byte 0x04 24.--31. 0x1 " MCONNID2 ,MConnID for Performance Counter2 register"
hexmask.long.byte 0x04 8.--15. 0x1 " MCONNID1 ,MConnID for Performance Counter1 register"
width 9.
endif
group.long 0xA0++0x03
line.long 0x00 "EOI,End of Interrupt Register"
bitfld.long 0x00 0. " EOI ,Software End of Interrupt Control" "System OCP Interrupt,?..."
wgroup.long 0xA4++0x03
line.long 0x00 "SOIRSR,System OCP Interrup RAW Status Register"
bitfld.long 0x00 0. " ERRSYS ,Raw status of system OCP interrupt for command or address error" "No effect,Set"
group.long 0xAC++0x03
line.long 0x00 "SOISR,Sytem OCP Interrupt Status Register"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " ERRSYS_set/clr ,Status of system OCP interrupt for SDRAM command or address error" "Disabled,Enabled"
group.long 0xC8++0x03
line.long 0x00 "ZQCR,SDRAM Output Impedance Calibration Configuration Register"
bitfld.long 0x00 31. " CS1EN ,Enables ZQ calibration for CS1" "Disabled,Enabled"
bitfld.long 0x00 30. " CS0EN ,Enables ZQ calibration for CS0" "Disabled,Enabled"
bitfld.long 0x00 29. " DUALCALEN ,ZQ Dual Calibration Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " SEFXITEN ,ZQCL on Self-Refresh - Active Power Down and Prechare Power-Down exit enable" "Disabled,Enabled"
bitfld.long 0x00 18.--19. " ZQINITMULT ,Indicates number of ZQCL intervals that make up a ZQINIT interval" "0,1,2,3"
bitfld.long 0x00 16.--17. " ZQCLMULT ,Indicates number of ZQCS intervals that make up a ZQCL interva" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--15. 1. " REFINTERVAL ,Number of refresh periods between ZQCS commands"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0xDC++0x03
line.long 0x00 "RWLCR,Read-Write Leveling Control Register"
bitfld.long 0x00 31. " RDWRLVLFULL_START ,Full leveling trigger" "Cleared,Started"
endif
if ((d.l(ad:0x4D000000+0x08)&0xE0000000)==0x60000000)
group.long 0xE4++0x07
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Enable IO receiver dynamic powerdown when not performing a read" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 18. " RDEYE_LVL_DIS ,Read eye auto-leveling disable" "No,Yes"
bitfld.long 0x00 17. " GATE_LVL_DIS ,Read gate auto-leveling disable" "No,Yes"
textline " "
bitfld.long 0x00 16. " WR_LVL_DIS ,Write auto-leveling disable" "No,Yes"
bitfld.long 0x00 15. " PHY_RST ,DDR PHY reset" "Not reset,Reset"
textline " "
bitfld.long 0x00 12.--13. " ID_LODT ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x00 8.--9. " RD_LODT ,Select controller termination during read accesses" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x00 0.--4. " RL ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
bitfld.long 0x04 20. " EN_DYN_PWRDN_SHDW ,Shadow field for EN_DYN_PWRDN in DDRPHYCR" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 18. " RDEYE_LVL_DIS_SHDW ,Read eye auto-leveling disable" "No,Yes"
bitfld.long 0x00 17. " GATE_LVL_DIS_SHDW ,Read gate auto-leveling disable" "No,Yes"
textline " "
bitfld.long 0x00 16. " WR_LVL_DIS_SHDW ,Write auto-leveling disable" "No,Yes"
bitfld.long 0x00 12.--13. " ID_LODT_SHDW ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x04 8.--9. " RD_LODT_SHDW ,Shadow field for RD_LODT in DDRPHYCR" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x04 0.--4. " RL_SHDW ,Shadow field for RL in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
else
group.long 0xE4++0x07
line.long 0x00 "DDRPHYCR,DDR PHY Control Register"
bitfld.long 0x00 20. " DYN_PWRDN_EN ,Enable IO receiver dynamic powerdown when not performing a read" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 15. " PHY_RST ,DDR PHY reset" "Not reset,Reset"
bitfld.long 0x00 12.--13. " ID_LODT ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x00 8.--9. " RD_LODT ,Select controller termination during read accesses" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x00 0.--4. " RL ,Latency for read data from DDR SDRAM in number of 1x cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "DDRPHYCSR,DDR PHY Control Shadow Register"
bitfld.long 0x04 20. " EN_DYN_PWRDN_SHDW ,Shadow field for EN_DYN_PWRDN in DDRPHYCR" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 12.--13. " ID_LODT_SHDW ,DDR controller side ODT selection when receiver is powered down" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
textline " "
endif
bitfld.long 0x04 8.--9. " RD_LODT_SHDW ,Shadow field for RD_LODT in DDRPHYCR" "Off,Enabled 50 ohms,Off,Enabled 100 ohms"
bitfld.long 0x04 0.--4. " RL_SHDW ,Shadow field for RL in DDRPHYCR" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
width 18.
group.long 0x100++0x0B
line.long 0x00 "PRI_COS_MAP,Priority to Class of Service Mapping Register"
bitfld.long 0x00 31. " PRI_COS_MAP_EN ,Priority to class of service mapping enable" "Disabled,Enabled"
bitfld.long 0x00 14.--15. " PRI_7_COS ,Class of service for commands with priority of 7" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 12.--13. " PRI_6_COS ,Class of service for commands with priority of 6" "Not assigned,Class 1,Class 2,Not assigned"
textline " "
bitfld.long 0x00 10.--11. " PRI_5_COS ,Class of service for commands with priority of 5" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 8.--9. " PRI_4_COS ,Class of service for commands with priority of 4" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 6.--7. " PRI_3_COS ,Class of service for commands with priority of 3" "Not assigned,Class 1,Class 2,Not assigned"
textline " "
bitfld.long 0x00 4.--5. " PRI_2_COS ,Class of service for commands with priority of 2" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 2.--3. " PRI_1_COS ,Class of service for commands with priority of 1" "Not assigned,Class 1,Class 2,Not assigned"
bitfld.long 0x00 0.--1. " PRI_0_COS ,Class of service for commands with priority of 0" "Not assigned,Class 1,Class 2,Not assigned"
line.long 0x04 "CONNID_COS_1_MAP,Connection ID to Class of Service 1 Mapping Register"
bitfld.long 0x04 31. " CONNID_COS_1_MAP_EN ,Connection ID to class of service mapping enable" "Disabled,Enabled"
hexmask.long.byte 0x04 23.--30. 0x1 " CONNID_1_COS_1 ,Connection ID value 1 for class of service 1"
bitfld.long 0x04 20.--22. " MSK_1_COS_1 ,Mask for connection ID value 1 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0,Bits 3:0,Bits 4:0,Bits 5:0,Bits 6:0"
textline " "
hexmask.long.byte 0x04 12.--19. 0x1 " CONNID_2_COS_1 ,Connection ID value 2 for class of service 1"
bitfld.long 0x04 10.--11. " MSK_2_COS_1 ,Mask for connection ID value 2 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
textline " "
hexmask.long.byte 0x04 2.--9. 0x1 " CONNID_3_COS_1 ,Connection ID value 3 for class of service 1"
bitfld.long 0x04 0.--1. " MSK_3_COS_1 ,Mask for connection ID value 3 for class of service 1" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
line.long 0x08 "CONNID_COS_2_MAP,Connection ID to Class of Service 2 Mapping Register"
bitfld.long 0x08 31. " CONNID_COS_2_MAP_EN ,Connection ID to class of service mapping enable" "Disabled,Enabled"
hexmask.long.byte 0x08 23.--30. 0x1 " CONNID_1_COS_2 ,Connection ID value 1 for class of service 2"
bitfld.long 0x08 20.--22. " MSK_1_COS_2 ,Mask for connection ID value 1 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0,Bits 3:0,Bits 4:0,Bits 5:0,Bits 6:0"
textline " "
hexmask.long.byte 0x08 12.--19. 0x1 " CONNID_2_COS_2 ,Connection ID value 2 for class of service 2"
bitfld.long 0x08 10.--11. " MSK_2_COS_2 ,Mask for connection ID value 2 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
textline " "
hexmask.long.byte 0x08 2.--9. 0x1 " CONNID_3_COS_2 ,Connection ID value 3 for class of service 2"
bitfld.long 0x08 0.--1. " MSK_3_COS_2 ,Mask for connection ID value 3 for class of service 2" "Disabled,Bit 0,Bits 1:0,Bits 2:0"
group.long 0x120++0x03
line.long 0x00 "RD_WR_EXEC_THRSH,Read Write Execution Threshold Register"
bitfld.long 0x00 8.--12. " WR_THRSH ,Write threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0.--4. " RD_THRSH ,Read threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
endif
width 0xB
tree.end
tree.end
tree "DDR2/3 PHY Register Descriptions"
tree "DDR0"
base ad:0x48198000
width 37.
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x0C++0x0F
line.long 0x00 "CMD0_IO_CONFIG_I_0,Command 0 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD0_IO_CONFIG_I_CLK_0,Command 0 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD0_IO_CONFIG_SR_0,Command 0 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD0_IO_CONFIG_SR_CLK_0,Command 0 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x1C++0x03
line.long 0x00 "CMD0_REG_PHY_CTRL_SLAVE_RATIO_0,Command 0 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x28++0x03
line.long 0x00 "CMD0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 0 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x2C++0x03
line.long 0x00 "CMD0_REG_PHY_INVERT_CLKOUT_0,Command 0 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Not inverted,Inverted"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x40++0x0F
line.long 0x00 "CMD1_IO_CONFIG_I_0,Command 1 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD1_IO_CONFIG_I_CLK_0,Command 1 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD1_IO_CONFIG_SR_0,Command 1 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD1_IO_CONFIG_SR_CLK_0,Command 1 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x50++0x03
line.long 0x00 "CMD1_REG_PHY_CTRL_SLAVE_RATIO_0,Command 1 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x5C++0x03
line.long 0x00 "CMD1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 1 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x60++0x03
line.long 0x00 "CMD1_REG_PHY_INVERT_CLKOUT_0,Command 1 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Core clock,Inverted core clock"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x74++0x0F
line.long 0x00 "CMD2_IO_CONFIG_I_0,Command 2 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD2_IO_CONFIG_I_CLK_0,Command 2 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD2_IO_CONFIG_SR_0,Command 2 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD2_IO_CONFIG_SR_CLK_0,Command 2 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x84++0x03
line.long 0x00 "CMD2_REG_PHY_CTRL_SLAVE_RATIO_0,Command 2 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x90++0x03
line.long 0x00 "CMD1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 1 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x94++0x03
line.long 0x00 "CMD1_REG_PHY_INVERT_CLKOUT_0,Command 1 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Core clock,Inverted core clock"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0xA8++0x7
line.long 0x00 "DATA0_IO_CONFIG_I_0,Data Macro 0 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA0_IO_CONFIG_I_CLK_0,Data Macro 0 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,Strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0xB0++0x07
hide.long 0x00 "DATA0_IO_CONFIG_SR_0,Data Macro 0 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA0_IO_CONFIG_SR_CLK_0,Data Macro 0 Data Strobe Slew Rate Configuration Register"
endif
group.long 0xC8++0x03
line.long 0x00 "DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 0 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0xDC++0x03
line.long 0x00 "DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 0 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x48198000+0xF8)&0x01)==0x01)
group.long 0xF0++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 0 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0xF0++0x03
hide.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 0 Write Leveling Init Ratio Register"
endif
group.long 0xF8++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM - Based on" "Previous data slice,Register"
if ((d.l(ad:0x48198000+0x104)&0x01)==0x01)
group.long 0xFC++0x03
line.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 0 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0xFC++0x03
hide.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 0 DQS Gate Training Init Ratio Register"
endif
group.long 0x104++0x03
line.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 0 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM - Based on" "Previous data slice,Register"
endif
group.long 0x108++0x03
line.long 0x00 "DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 0 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x120++0x03
line.long 0x00 "DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0,Data Macro 0 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x134++0x03
line.long 0x00 "DATA0_REG_PHY_USE_RANK0_DELAYS,Data Macro 0 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x138++0x03
line.long 0x00 "DATA0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 0 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x14C++0x7
line.long 0x00 "DATA1_IO_CONFIG_I_0,Data Macro 1 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA1_IO_CONFIG_I_CLK_0,Data Macro 1 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,Strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x154++0x07
hide.long 0x00 "DATA1_IO_CONFIG_SR_0,Data Macro 1 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA1_IO_CONFIG_SR_CLK_0,Data Macro 1 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x16C++0x03
line.long 0x00 "DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 1 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x180++0x03
line.long 0x00 "DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 1 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x48198000+0x19C)&0x01)==0x01)
group.long 0x194++0x03
line.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 1 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x194++0x03
hide.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 1 Write Leveling Init Ratio Register"
endif
group.long 0x19C++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x48198000+0x1A8)&0x01)==0x01)
group.long 0x1A0++0x03
line.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 1 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x1A0++0x03
hide.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 1 DQS Gate Training Init Ratio Register"
endif
group.long 0x1A8++0x03
line.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 1 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x1AC++0x03
line.long 0x00 "DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 1 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x1C4++0x03
line.long 0x00 "DATA1_REG_PHY_WR_Data,Data Macro 1 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x1D8++0x03
line.long 0x00 "DATA1_REG_PHY_USE_RANK0_DELAYS,Data Macro 1 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x1DC++0x03
line.long 0x00 "DATA1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 1 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x1F0++0x7
line.long 0x00 "DATA2_IO_CONFIG_I_0,Data Macro 2 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA2_IO_CONFIG_I_CLK_0,Data Macro 2 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x1F8++0x07
hide.long 0x00 "DATA2_IO_CONFIG_SR_0,Data Macro 2 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA2_IO_CONFIG_SR_CLK_0,Data Macro 2 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x210++0x03
line.long 0x00 "DATA2_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 2 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x224++0x03
line.long 0x00 "DATA2_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 2 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x48198000+0x240)&0x01)==0x01)
group.long 0x238++0x03
line.long 0x00 "DATA2_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 2 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x238++0x03
hide.long 0x00 "DATA2_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 2 Write Leveling Init Ratio Register"
endif
group.long 0x240++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x48198000+0x24C)&0x01)==0x01)
group.long 0x244++0x03
line.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 2 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x244++0x03
hide.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 2 DQS Gate Training Init Ratio Register"
endif
group.long 0x24C++0x03
line.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 2 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x250++0x03
line.long 0x00 "DATA2_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 2 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x268++0x03
line.long 0x00 "DATA2_REG_PHY_WR_Data,Data Macro 2 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x27C++0x03
line.long 0x00 "DATA2_REG_PHY_USE_RANK0_DELAYS,Data Macro 2 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x280++0x03
line.long 0x00 "DATA2_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 2 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x294++0x7
line.long 0x00 "DATA3_IO_CONFIG_I_0,Data Macro 3 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA3_IO_CONFIG_I_CLK_0,Data Macro 3 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x29C++0x07
hide.long 0x00 "DATA3_IO_CONFIG_SR_0,Data Macro 3 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA3_IO_CONFIG_SR_CLK_0,Data Macro 3 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x2B4++0x03
line.long 0x00 "DATA3_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 3 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x2C8++0x03
line.long 0x00 "DATA3_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 3 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x48198000+0x2E4)&0x01)==0x01)
group.long 0x2DC++0x03
line.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 3 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x2DC++0x03
hide.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 3 Write Leveling Init Ratio Register"
endif
group.long 0x2E4++0x03
line.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 3 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x48198000+0x2F0)&0x01)==0x01)
group.long 0x2E8++0x03
line.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 3 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x2E8++0x03
hide.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 3 DQS Gate Training Init Ratio Register"
endif
group.long 0x2F0++0x03
line.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 3 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x2F4++0x03
line.long 0x00 "DATA3_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 3 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x30C++0x03
line.long 0x00 "DATA3_REG_PHY_WR_Data,Data Macro 3 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x320++0x03
line.long 0x00 "DATA3_REG_PHY_USE_RANK0_DELAYS,Data Macro 3 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x324++0x03
line.long 0x00 "DATA3_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 3 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x694++0x03
line.long 0x00 "EMIF_CLK_GATE,EMIF Clock Gate Control Register"
rbitfld.long 0x00 3. " DDR1_CKE_STATUS ,CKE status for DDR1" "0,1"
rbitfld.long 0x00 2. " DDR0_CKE_STATUS ,CKE status for DDR0" "0,1"
textline " "
bitfld.long 0x00 1. " DDRPHY1_CLK_GATE ,DDR1 PHY clock enable" "Enabled,Disabled"
bitfld.long 0x00 0. " DDRPHY0_CLK_GATE ,DDR0 PHY clock enable" "Enabled,Disabled"
group.long 0xE04++0x0F
line.long 0x00 "DDR0_IO_CTRL,DDR Memory Controller0_ IO Control Register"
bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR0_RST signal active on reset" "Active,Inactive"
bitfld.long 0x00 30. " DDR_WUCLK_DISABLE ,Internal 32kHz wakeup clock disable" "No,Yes"
textline " "
bitfld.long 0x00 19.--20. " CS_SLEW ,CS pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 16.--18. " CS_IMPEDANCE ,CS pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x00 11.--12. " CMD_SLEW ,Command/Address pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 8.--10. " CMD_IMPEDANCE ,Command/Address pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x00 3.--4. " DATA_SLEW ,Data pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 0.--2. " DATA_IMPEDANCE ,Data pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
line.long 0x04 "DDR1_IO_CTRL,DDR Memory Controller0_ IO Control Register"
bitfld.long 0x04 31. " DDR3_RST_DEF_VAL ,DDR0_RST signal active on reset" "Active,Inactive"
bitfld.long 0x04 30. " DDR_WUCLK_DISABLE ,Internal 32kHz wakeup clock disable" "No,Yes"
textline " "
bitfld.long 0x04 19.--20. " CS_SLEW ,CS pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 16.--18. " CS_IMPEDANCE ,CS pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x04 11.--12. " CMD_SLEW ,Command/Address pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 8.--10. " CMD_IMPEDANCE ,Command/Address pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x04 3.--4. " DATA_SLEW ,Data pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 0.--2. " DATA_IMPEDANCE ,Data pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
line.long 0x08 "DDR_VTP_CTRL_0,DDR VTP Control Register"
bitfld.long 0x08 6. " ENABLE ,VTP macro enable" "Disabled,Enabled"
bitfld.long 0x08 5. " READY ,IO training sequence completion status" "Not ready,Ready"
textline " "
bitfld.long 0x08 4. " LOCK ,Dynamic update locking" "Enabled,Disabled"
bitfld.long 0x08 1.--3. " FILTER ,Update rate" "Reserved,On 2 requests,On 3 requests,On 4 requests,On 5 requests,On 6 requests,On 7 requests,?..."
textline " "
bitfld.long 0x08 0. " CLRZ ,Flops clear and counter reset" "Cleared,Not cleared"
line.long 0x0C "DDR_VTP_CTRL_1,DDR VTP Control Register"
bitfld.long 0x08 6. " ENABLE ,VTP macro enable" "Disabled,Enabled"
bitfld.long 0x08 5. " READY ,IO training sequence completion status" "Not ready,Ready"
textline " "
bitfld.long 0x08 4. " LOCK ,Dynamic update locking" "Enabled,Disabled"
bitfld.long 0x08 1.--3. " FILTER ,Update rate" "Reserved,On 2 requests,On 3 requests,On 4 requests,On 5 requests,On 6 requests,On 7 requests,?..."
textline " "
bitfld.long 0x08 0. " CLRZ ,Flops clear and counter reset" "Cleared,Not cleared"
else
group.long 0x358++0x03
line.long 0x00 "DDR_VTP_CTRL_0,DDR VTP Control Register"
bitfld.long 0x00 4. " WR_LEVEL ,Selects Leveling or Slave ratio" "Slave Ratio,Leveling Ratio"
bitfld.long 0x00 3. " LOCK ,Freeze Dynamic Update" "Normal operation,Enabled"
textline " "
bitfld.long 0x00 0.--2. " VTP_CTRL ,Update consecutive update request" "Off,5,3,7,2,6,4,5"
endif
width 0xB
tree.end
tree "DDR1"
base ad:0x4819A000
width 37.
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x0C++0x0F
line.long 0x00 "CMD0_IO_CONFIG_I_0,Command 0 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD0_IO_CONFIG_I_CLK_0,Command 0 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD0_IO_CONFIG_SR_0,Command 0 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD0_IO_CONFIG_SR_CLK_0,Command 0 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x1C++0x03
line.long 0x00 "CMD0_REG_PHY_CTRL_SLAVE_RATIO_0,Command 0 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x28++0x03
line.long 0x00 "CMD0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 0 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x2C++0x03
line.long 0x00 "CMD0_REG_PHY_INVERT_CLKOUT_0,Command 0 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Not inverted,Inverted"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x40++0x0F
line.long 0x00 "CMD1_IO_CONFIG_I_0,Command 1 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD1_IO_CONFIG_I_CLK_0,Command 1 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD1_IO_CONFIG_SR_0,Command 1 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD1_IO_CONFIG_SR_CLK_0,Command 1 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x50++0x03
line.long 0x00 "CMD1_REG_PHY_CTRL_SLAVE_RATIO_0,Command 1 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x5C++0x03
line.long 0x00 "CMD1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 1 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x60++0x03
line.long 0x00 "CMD1_REG_PHY_INVERT_CLKOUT_0,Command 1 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Core clock,Inverted core clock"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x74++0x0F
line.long 0x00 "CMD2_IO_CONFIG_I_0,Command 2 Address/Command Pad Configuration Register"
bitfld.long 0x00 0.--2. " ADDR_CMD_CFG ,Address/Command I/O Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "CMD2_IO_CONFIG_I_CLK_0,Command 2 Clock Pad Configuration Register"
bitfld.long 0x04 0.--2. " CLK_CFG ,Clock output Pad for pull up/pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x08 "CMD2_IO_CONFIG_SR_0,Command 2 Address/Command Slew Rate Configuration Register"
bitfld.long 0x08 0.--1. " SR ,Program addr/cmd IO Pads output Slew Rate" "Fastest,Fast,Slow,Slowest"
line.long 0x0C "CMD2_IO_CONFIG_SR_CLK_0,Command 2 Clock Pad Slew Rate"
bitfld.long 0x0C 0.--1. " SR ,Program clock IO Pads (CK/CK#) output Slew Rate" "Fastest,Fast,Slow,Slowest"
endif
group.long 0x84++0x03
line.long 0x00 "CMD2_REG_PHY_CTRL_SLAVE_RATIO_0,Command 2 Address/CommandSlave Ratio Register"
hexmask.long.word 0x00 0.--9. 1. " CMD_SLAVE_RATIO ,Ratio value for address/command launch timing in DDR PHY macro"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x90++0x03
line.long 0x00 "CMD1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Command 1 Address/Command DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,The max number of delay line taps variation allowed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
group.long 0x94++0x03
line.long 0x00 "CMD1_REG_PHY_INVERT_CLKOUT_0,Command 1 Invert Clockout Selection Register"
bitfld.long 0x00 0. " INVERT_CLK_SEL ,Inverts the polarity of DRAM clock" "Core clock,Inverted core clock"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0xA8++0x7
line.long 0x00 "DATA0_IO_CONFIG_I_0,Data Macro 0 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA0_IO_CONFIG_I_CLK_0,Data Macro 0 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,Strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0xB0++0x07
hide.long 0x00 "DATA0_IO_CONFIG_SR_0,Data Macro 0 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA0_IO_CONFIG_SR_CLK_0,Data Macro 0 Data Strobe Slew Rate Configuration Register"
endif
group.long 0xC8++0x03
line.long 0x00 "DATA0_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 0 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0xDC++0x03
line.long 0x00 "DATA0_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 0 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x4819A000+0xF8)&0x01)==0x01)
group.long 0xF0++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 0 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0xF0++0x03
hide.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 0 Write Leveling Init Ratio Register"
endif
group.long 0xF8++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM - Based on" "Previous data slice,Register"
if ((d.l(ad:0x4819A000+0x104)&0x01)==0x01)
group.long 0xFC++0x03
line.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 0 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0xFC++0x03
hide.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 0 DQS Gate Training Init Ratio Register"
endif
group.long 0x104++0x03
line.long 0x00 "DATA0_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 0 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM - Based on" "Previous data slice,Register"
endif
group.long 0x108++0x03
line.long 0x00 "DATA0_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 0 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x120++0x03
line.long 0x00 "DATA0_REG_PHY_WR_DATA_SLAVE_RATIO_0,Data Macro 0 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x134++0x03
line.long 0x00 "DATA0_REG_PHY_USE_RANK0_DELAYS,Data Macro 0 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x138++0x03
line.long 0x00 "DATA0_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 0 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x14C++0x7
line.long 0x00 "DATA1_IO_CONFIG_I_0,Data Macro 1 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA1_IO_CONFIG_I_CLK_0,Data Macro 1 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,Strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x154++0x07
hide.long 0x00 "DATA1_IO_CONFIG_SR_0,Data Macro 1 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA1_IO_CONFIG_SR_CLK_0,Data Macro 1 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x16C++0x03
line.long 0x00 "DATA1_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 1 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x180++0x03
line.long 0x00 "DATA1_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 1 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x4819A000+0x19C)&0x01)==0x01)
group.long 0x194++0x03
line.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 1 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x194++0x03
hide.long 0x00 "DATA1_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 1 Write Leveling Init Ratio Register"
endif
group.long 0x19C++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x4819A000+0x1A8)&0x01)==0x01)
group.long 0x1A0++0x03
line.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 1 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x1A0++0x03
hide.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 1 DQS Gate Training Init Ratio Register"
endif
group.long 0x1A8++0x03
line.long 0x00 "DATA1_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 1 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x1AC++0x03
line.long 0x00 "DATA1_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 1 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x1C4++0x03
line.long 0x00 "DATA1_REG_PHY_WR_Data,Data Macro 1 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x1D8++0x03
line.long 0x00 "DATA1_REG_PHY_USE_RANK0_DELAYS,Data Macro 1 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x1DC++0x03
line.long 0x00 "DATA1_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 1 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x1F0++0x7
line.long 0x00 "DATA2_IO_CONFIG_I_0,Data Macro 2 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA2_IO_CONFIG_I_CLK_0,Data Macro 2 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x1F8++0x07
hide.long 0x00 "DATA2_IO_CONFIG_SR_0,Data Macro 2 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA2_IO_CONFIG_SR_CLK_0,Data Macro 2 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x210++0x03
line.long 0x00 "DATA2_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 2 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x224++0x03
line.long 0x00 "DATA2_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 2 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x4819A000+0x240)&0x01)==0x01)
group.long 0x238++0x03
line.long 0x00 "DATA2_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 2 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x238++0x03
hide.long 0x00 "DATA2_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 2 Write Leveling Init Ratio Register"
endif
group.long 0x240++0x03
line.long 0x00 "DATA0_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 0 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x4819A000+0x24C)&0x01)==0x01)
group.long 0x244++0x03
line.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 2 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x244++0x03
hide.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 2 DQS Gate Training Init Ratio Register"
endif
group.long 0x24C++0x03
line.long 0x00 "DATA2_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 2 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x250++0x03
line.long 0x00 "DATA2_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 2 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x268++0x03
line.long 0x00 "DATA2_REG_PHY_WR_Data,Data Macro 2 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x27C++0x03
line.long 0x00 "DATA2_REG_PHY_USE_RANK0_DELAYS,Data Macro 2 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x280++0x03
line.long 0x00 "DATA2_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 2 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
group.long 0x294++0x7
line.long 0x00 "DATA3_IO_CONFIG_I_0,Data Macro 3 Data Pad Data Pad Configuration Register"
bitfld.long 0x00 0.--2. " DQ_DM_CFG ,DQ/DM IO Pad Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
line.long 0x04 "DATA3_IO_CONFIG_I_CLK_0,Data Macro 3 Data Strobe Pad Configuration Register"
bitfld.long 0x04 0.--2. " DQS_CFG ,strobe IO Pads (DQS/DQS#) Pull up/Pull down output impedance" "0,1,2,3,4,5,6,7"
hgroup.long 0x29C++0x07
hide.long 0x00 "DATA3_IO_CONFIG_SR_0,Data Macro 3 Data Slew Rate Configuration Register"
hide.long 0x04 "DATA3_IO_CONFIG_SR_CLK_0,Data Macro 3 Data Strobe Slew Rate Configuration Register"
endif
group.long 0x2B4++0x03
line.long 0x00 "DATA3_REG_PHY_RD_DQS_SLAVE_RATIO_0,Data Macro 3 Read DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_SLAVE_RATIO_CS1 ,Ratio value for Read DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_SLAVE_RATIO_CS0 ,Ratio value for Read DQS slave DLL for CS0"
group.long 0x2C8++0x03
line.long 0x00 "DATA3_REG_PHY_WR_DQS_SLAVE_RATIO_0,Data Macro 3 Write DQS Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DQS_SLAVE_RATIO_CS1 ,Ratio value for Write DQS slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DQS_SLAVE_RATIO_CS0 ,Ratio value for Write DQS slave DLL for CS0"
sif (cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP")
if ((d.l(ad:0x4819A000+0x2E4)&0x01)==0x01)
group.long 0x2DC++0x03
line.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 3 Write Leveling Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WRLVL_INIT_RATIO_CS1 ,The user programmable init ratio used by Write Leveling FSM"
hexmask.long.word 0x00 0.--9. 1. " WRLVL_INIT_RATIO_CS0 ,The user programmable init ratio used by Write Leveling FSM"
else
hgroup.long 0x2DC++0x03
hide.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_RATIO_0,Data Macro 3 Write Leveling Init Ratio Register"
endif
group.long 0x2E4++0x03
line.long 0x00 "DATA3_REG_PHY_WRLVL_INIT_MODE_0,Data Macro 3 Write Leveling Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " WRLVL_INIT_MODE_SEL ,The user programmable init ratio selection mode for Write Leveling FSM- Based on" "Previous data slice,Register"
if ((d.l(ad:0x4819A000+0x2F0)&0x01)==0x01)
group.long 0x2E8++0x03
line.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 3 DQS Gate Training Init Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " GATELVL_INIT_RATIO_CS1 ,The user programmable init ratio used by DQS Gate Training FSM"
hexmask.long.word 0x00 0.--9. 1. " GATELVL_INIT_RATIO_CS0 ,The user programmable init ratio used by DQS Gate Training FSM"
else
hgroup.long 0x2E8++0x03
hide.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_RATIO_0,Data Macro 3 DQS Gate Training Init Ratio Register"
endif
group.long 0x2F0++0x03
line.long 0x00 "DATA3_REG_PHY_GATELVL_INIT_MODE_0,Data Macro 3 DQS Gate Training Init Mode Ratio Selection Register"
bitfld.long 0x00 0. " GATELVL_INIT_MODE_SEL ,User programmable init ratio selection mode for DQS Gate Training FSM- Based on" "Previous data slice,Register"
endif
group.long 0x2F4++0x03
line.long 0x00 "DATA3_REG_PHY_FIFO_WE_SLAVE_RATIO_0,Data Macro 3 DQS Gate Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " RD_DQS_GATE_SLAVE_RATIO_CS1 ,Ratio value for Read DQS Gate slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " RD_DQS_GATE_SLAVE_RATIO_CS0 ,Ratio value for Read DQS Gate slave DLL for CS0"
group.long 0x30C++0x03
line.long 0x00 "DATA3_REG_PHY_WR_Data,Data Macro 3 Write Data Slave Ratio Register"
hexmask.long.word 0x00 10.--19. 1. " WR_DATA_SLAVE_RATIO_CS1 ,Ratio value for write data slave DLL for CS1"
hexmask.long.word 0x00 0.--9. 1. " WR_DATA_SLAVE_RATIO_CS0 ,Ratio value for write data slave DLL for CS0"
group.long 0x320++0x03
line.long 0x00 "DATA3_REG_PHY_USE_RANK0_DELAYS,Data Macro 3 Delay Selection Register"
bitfld.long 0x00 0. " RANK0_DELAY ,Delay Selection - Rank 0 delays are used for all ranks during read/write / Each Rank uses its own delay" "Rank 0,Each Rank"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x324++0x03
line.long 0x00 "DATA3_REG_PHY_DLL_LOCK_DIFF_0,DDR PHY Data Macro 3 DLL Lock Difference Register"
bitfld.long 0x00 0.--3. " DLL_LOCK_DIFF ,Lock difference" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
group.long 0x694++0x03
line.long 0x00 "EMIF_CLK_GATE,EMIF Clock Gate Control Register"
rbitfld.long 0x00 3. " DDR1_CKE_STATUS ,CKE status for DDR1" "0,1"
rbitfld.long 0x00 2. " DDR0_CKE_STATUS ,CKE status for DDR0" "0,1"
textline " "
bitfld.long 0x00 1. " DDRPHY1_CLK_GATE ,DDR1 PHY clock enable" "Enabled,Disabled"
bitfld.long 0x00 0. " DDRPHY0_CLK_GATE ,DDR0 PHY clock enable" "Enabled,Disabled"
group.long 0xE04++0x0F
line.long 0x00 "DDR0_IO_CTRL,DDR Memory Controller0_ IO Control Register"
bitfld.long 0x00 31. " DDR3_RST_DEF_VAL ,DDR0_RST signal active on reset" "Active,Inactive"
bitfld.long 0x00 30. " DDR_WUCLK_DISABLE ,Internal 32kHz wakeup clock disable" "No,Yes"
textline " "
bitfld.long 0x00 19.--20. " CS_SLEW ,CS pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 16.--18. " CS_IMPEDANCE ,CS pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x00 11.--12. " CMD_SLEW ,Command/Address pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 8.--10. " CMD_IMPEDANCE ,Command/Address pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x00 3.--4. " DATA_SLEW ,Data pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x00 0.--2. " DATA_IMPEDANCE ,Data pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
line.long 0x04 "DDR1_IO_CTRL,DDR Memory Controller0_ IO Control Register"
bitfld.long 0x04 31. " DDR3_RST_DEF_VAL ,DDR0_RST signal active on reset" "Active,Inactive"
bitfld.long 0x04 30. " DDR_WUCLK_DISABLE ,Internal 32kHz wakeup clock disable" "No,Yes"
textline " "
bitfld.long 0x04 19.--20. " CS_SLEW ,CS pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 16.--18. " CS_IMPEDANCE ,CS pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x04 11.--12. " CMD_SLEW ,Command/Address pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 8.--10. " CMD_IMPEDANCE ,Command/Address pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
textline " "
bitfld.long 0x04 3.--4. " DATA_SLEW ,Data pins slew rate" "Fastest,1,2,Slowest"
bitfld.long 0x04 0.--2. " DATA_IMPEDANCE ,Data pins output impedance" "0,1,2,50 Ohm,4,5,6,7"
line.long 0x08 "DDR_VTP_CTRL_0,DDR VTP Control Register"
bitfld.long 0x08 6. " ENABLE ,VTP macro enable" "Disabled,Enabled"
bitfld.long 0x08 5. " READY ,IO training sequence completion status" "Not ready,Ready"
textline " "
bitfld.long 0x08 4. " LOCK ,Dynamic update locking" "Enabled,Disabled"
bitfld.long 0x08 1.--3. " FILTER ,Update rate" "Reserved,On 2 requests,On 3 requests,On 4 requests,On 5 requests,On 6 requests,On 7 requests,?..."
textline " "
bitfld.long 0x08 0. " CLRZ ,Flops clear and counter reset" "Cleared,Not cleared"
line.long 0x0C "DDR_VTP_CTRL_1,DDR VTP Control Register"
bitfld.long 0x08 6. " ENABLE ,VTP macro enable" "Disabled,Enabled"
bitfld.long 0x08 5. " READY ,IO training sequence completion status" "Not ready,Ready"
textline " "
bitfld.long 0x08 4. " LOCK ,Dynamic update locking" "Enabled,Disabled"
bitfld.long 0x08 1.--3. " FILTER ,Update rate" "Reserved,On 2 requests,On 3 requests,On 4 requests,On 5 requests,On 6 requests,On 7 requests,?..."
textline " "
bitfld.long 0x08 0. " CLRZ ,Flops clear and counter reset" "Cleared,Not cleared"
else
group.long 0x358++0x03
line.long 0x00 "DDR_VTP_CTRL_0,DDR VTP Control Register"
bitfld.long 0x00 4. " WR_LEVEL ,Selects Leveling or Slave ratio" "Slave Ratio,Leveling Ratio"
bitfld.long 0x00 3. " LOCK ,Freeze Dynamic Update" "Normal operation,Enabled"
textline " "
bitfld.long 0x00 0.--2. " VTP_CTRL ,Update consecutive update request" "Off,5,3,7,2,6,4,5"
endif
width 0xB
tree.end
tree.end
tree.end
tree.open "GPIO (General Purpose Input/Output)"
tree "GPIO 0"
base ad:0x48032000
width 25.
rgroup.long 0x00++0x3
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
textline " "
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
group.long 0x10++0x3
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
wgroup.long 0x20++0x3
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
width 25.
group.long 0x24++0x7
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
width 25.
group.long 0x2c++0x3
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
group.long 0x30++0x3
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
width 25.
group.long 0x44++0x07
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
endif
width 25.
rgroup.long 0x114++0x3
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
group.long 0x130++0x7
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
line.long 0x04 "GPIO_OE,Output Enable Register"
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
textline " "
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
textline " "
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
textline " "
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
textline " "
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
textline " "
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
textline " "
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
textline " "
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
width 25.
rgroup.long 0x138++0x3
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
sif (cpuis("AM387*")||cpuis("DRA62*"))
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
textline " "
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
textline " "
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
textline " "
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
textline " "
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
textline " "
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
textline " "
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
textline " "
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
endif
width 25.
group.long 0x13c++0x3
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
textline " "
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
textline " "
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
textline " "
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
textline " "
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
textline " "
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
textline " "
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
textline " "
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
width 25.
group.long 0x140++0x17
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
width 11.
tree.end
tree "GPIO 1"
base ad:0x4804c000
width 25.
rgroup.long 0x00++0x3
line.long 0x00 "GPIO_REVISION,GPIO Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Old/current scheme " "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
hexmask.long.byte 0x00 11.--15. 1. " RTL ,RTL version"
textline " "
hexmask.long.byte 0x00 8.--10. 1. " MAJOR ,Major Revision"
hexmask.long.byte 0x00 6.--7. 1. " CUSTOM ,Special version for a particular device"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
group.long 0x10++0x3
line.long 0x00 "GPIO_SYSCONFIG,GPIO System Configuration Register"
bitfld.long 0x00 3.--4. " IDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle"
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup capability enable" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
wgroup.long 0x20++0x3
line.long 0x00 "GPIO_EOI,GPIO End Of Interrupt Control Register"
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt Control" "Line #1,Line #2"
width 25.
group.long 0x24++0x7
line.long 0x00 "GPIO_IRQSTATUS_RAW_0,GPIO Status/Set Raw Register for Interrupt 1"
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
line.long 0x04 "GPIO_IRQSTATUS_RAW_1,GPIO Status/Set Raw Register for Interrupt 2"
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 raw status" "No interrupt,Interrupt"
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 raw status" "No interrupt,Interrupt"
width 25.
group.long 0x2c++0x3
line.long 0x00 "GPIO_IRQSTATUS_0_set/clr,GPIO Status Register for Interrupt 1"
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
group.long 0x30++0x3
line.long 0x00 "GPIO_IRQSTATUS_1_set/clr,GPIO Status Register for Interrupt 2"
setclrfld.long 0x00 31. 0x08 31. 0x10 31. " INTLINE[31]_set/clr ,Interrupt 31 status" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x08 30. 0x10 30. " INTLINE[30]_set/clr ,Interrupt 30 status" "No interrupt,Interrupt"
setclrfld.long 0x00 29. 0x08 29. 0x10 29. " INTLINE[29]_set/clr ,Interrupt 29 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 28. 0x08 28. 0x10 28. " INTLINE[28]_set/clr ,Interrupt 28 status" "No interrupt,Interrupt"
setclrfld.long 0x00 27. 0x08 27. 0x10 27. " INTLINE[27]_set/clr ,Interrupt 27 status" "No interrupt,Interrupt"
setclrfld.long 0x00 26. 0x08 26. 0x10 26. " INTLINE[26]_set/clr ,Interrupt 26 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 25. 0x08 25. 0x10 25. " INTLINE[25]_set/clr ,Interrupt 25 status" "No interrupt,Interrupt"
setclrfld.long 0x00 24. 0x08 24. 0x10 24. " INTLINE[24]_set/clr ,Interrupt 24 status" "No interrupt,Interrupt"
setclrfld.long 0x00 23. 0x08 23. 0x10 23. " INTLINE[23]_set/clr ,Interrupt 23 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 22. 0x08 22. 0x10 22. " INTLINE[22]_set/clr ,Interrupt 22 status" "No interrupt,Interrupt"
setclrfld.long 0x00 21. 0x08 21. 0x10 21. " INTLINE[21]_set/clr ,Interrupt 21 status" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x08 20. 0x10 20. " INTLINE[20]_set/clr ,Interrupt 20 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x08 19. 0x10 19. " INTLINE[19]_set/clr ,Interrupt 19 status" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x08 18. 0x10 18. " INTLINE[18]_set/clr ,Interrupt 18 status" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x08 17. 0x10 17. " INTLINE[17]_set/clr ,Interrupt 17 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 16. 0x08 16. 0x10 16. " INTLINE[16]_set/clr ,Interrupt 16 status" "No interrupt,Interrupt"
setclrfld.long 0x00 15. 0x08 15. 0x10 15. " INTLINE[15]_set/clr ,Interrupt 15 status" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x08 14. 0x10 14. " INTLINE[14]_set/clr ,Interrupt 14 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x10 13. " INTLINE[13]_set/clr ,Interrupt 13 status" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x08 12. 0x10 12. " INTLINE[12]_set/clr ,Interrupt 12 status" "No interrupt,Interrupt"
setclrfld.long 0x00 11. 0x08 11. 0x10 11. " INTLINE[11]_set/clr ,Interrupt 11 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 10. 0x08 10. 0x10 10. " INTLINE[10]_set/clr ,Interrupt 10 status" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x08 9. 0x10 9. " INTLINE[9]_set/clr ,Interrupt 9 status" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x08 8. 0x10 8. " INTLINE[8]_set/clr ,Interrupt 8 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x10 7. " INTLINE[7]_set/clr ,Interrupt 7 status" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x08 6. 0x10 6. " INTLINE[6]_set/clr ,Interrupt 6 status" "No interrupt,Interrupt"
setclrfld.long 0x00 5. 0x08 5. 0x10 5. " INTLINE[5]_set/clr ,Interrupt 5 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x10 4. " INTLINE[4]_set/clr ,Interrupt 4 status" "No interrupt,Interrupt"
setclrfld.long 0x00 3. 0x08 3. 0x10 3. " INTLINE[3]_set/clr ,Interrupt 3 status" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x08 2. 0x10 2. " INTLINE[2]_set/clr ,Interrupt 2 status" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x10 1. " INTLINE[1]_set/clr ,Interrupt 1 status" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x08 0. 0x10 0. " INTLINE[0]_set/clr ,Interrupt 0 status" "No interrupt,Interrupt"
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147"))
width 25.
group.long 0x44++0x07
line.long 0x00 "GPIO_IRQWAKEN_0,Wakeup Enable Register for Interrupt 1"
bitfld.long 0x00 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
line.long 0x04 "GPIO_IRQWAKEN_1,Wakeup Enable Register for Interrupt 2"
bitfld.long 0x04 31. " INTLINE[31] ,Interrupt 31 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 30. " INTLINE[30] ,Interrupt 30 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 29. " INTLINE[29] ,Interrupt 29 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " INTLINE[28] ,Interrupt 28 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 27. " INTLINE[27] ,Interrupt 27 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 26. " INTLINE[26] ,Interrupt 26 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 25. " INTLINE[25] ,Interrupt 25 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 24. " INTLINE[24] ,Interrupt 24 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 23. " INTLINE[23] ,Interrupt 23 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " INTLINE[22] ,Interrupt 22 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 21. " INTLINE[21] ,Interrupt 21 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 20. " INTLINE[20] ,Interrupt 20 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " INTLINE[19] ,Interrupt 19 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 18. " INTLINE[18] ,Interrupt 18 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 17. " INTLINE[17] ,Interrupt 17 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 16. " INTLINE[16] ,Interrupt 16 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 15. " INTLINE[15] ,Interrupt 15 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 14. " INTLINE[14] ,Interrupt 14 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " INTLINE[13] ,Interrupt 13 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 12. " INTLINE[12] ,Interrupt 12 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 11. " INTLINE[11] ,Interrupt 11 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " INTLINE[10] ,Interrupt 10 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 9. " INTLINE[9] ,Interrupt 9 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 8. " INTLINE[8] ,Interrupt 8 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " INTLINE[7] ,Interrupt 7 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " INTLINE[6] ,Interrupt 6 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " INTLINE[5] ,Interrupt 5 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " INTLINE[4] ,Interrupt 4 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 3. " INTLINE[3] ,Interrupt 3 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " INTLINE[2] ,Interrupt 2 Wakeup Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " INTLINE[1] ,Interrupt 1 Wakeup Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " INTLINE[0] ,Interrupt 0 Wakeup Enable" "Disabled,Enabled"
endif
width 25.
rgroup.long 0x114++0x3
line.long 0x00 "GPIO_SYSSTATUS,GPIO System Status Information Register"
bitfld.long 0x00 0. " RESETDONE ,Reset status information" "On-going,Completed"
group.long 0x130++0x7
line.long 0x00 "GPIO_CTRL,GPIO Module Control Register"
bitfld.long 0x00 1.--2. " GATINGRATIO ,Gating ratio" "Interface,Interface/2,Interface/4,Interface/8"
bitfld.long 0x00 0. " DISABLEMODULE ,Module disable" "Enabled,Disabled"
line.long 0x04 "GPIO_OE,Output Enable Register"
bitfld.long 0x04 31. " OUTPUTEN[31] ,GPIO bit 31 configuration" "Output,Input"
bitfld.long 0x04 30. " OUTPUTEN[30] ,GPIO bit 30 configuration" "Output,Input"
bitfld.long 0x04 29. " OUTPUTEN[29] ,GPIO bit 29 configuration" "Output,Input"
bitfld.long 0x04 28. " OUTPUTEN[28] ,GPIO bit 28 configuration" "Output,Input"
textline " "
bitfld.long 0x04 27. " OUTPUTEN[27] ,GPIO bit 27 configuration" "Output,Input"
bitfld.long 0x04 26. " OUTPUTEN[26] ,GPIO bit 26 configuration" "Output,Input"
bitfld.long 0x04 25. " OUTPUTEN[25] ,GPIO bit 25 configuration" "Output,Input"
bitfld.long 0x04 24. " OUTPUTEN[24] ,GPIO bit 24 configuration" "Output,Input"
textline " "
bitfld.long 0x04 23. " OUTPUTEN[23] ,GPIO bit 23 configuration" "Output,Input"
bitfld.long 0x04 22. " OUTPUTEN[22] ,GPIO bit 22 configuration" "Output,Input"
bitfld.long 0x04 21. " OUTPUTEN[21] ,GPIO bit 21 configuration" "Output,Input"
bitfld.long 0x04 20. " OUTPUTEN[20] ,GPIO bit 20 configuration" "Output,Input"
textline " "
bitfld.long 0x04 19. " OUTPUTEN[19] ,GPIO bit 19 configuration" "Output,Input"
bitfld.long 0x04 18. " OUTPUTEN[18] ,GPIO bit 18 configuration" "Output,Input"
bitfld.long 0x04 17. " OUTPUTEN[17] ,GPIO bit 17 configuration" "Output,Input"
bitfld.long 0x04 16. " OUTPUTEN[16] ,GPIO bit 16 configuration" "Output,Input"
textline " "
bitfld.long 0x04 15. " OUTPUTEN[15] ,GPIO bit 15 configuration" "Output,Input"
bitfld.long 0x04 14. " OUTPUTEN[14] ,GPIO bit 14 configuration" "Output,Input"
bitfld.long 0x04 13. " OUTPUTEN[13] ,GPIO bit 13 configuration" "Output,Input"
bitfld.long 0x04 12. " OUTPUTEN[12] ,GPIO bit 12 configuration" "Output,Input"
textline " "
bitfld.long 0x04 11. " OUTPUTEN[11] ,GPIO bit 11 configuration" "Output,Input"
bitfld.long 0x04 10. " OUTPUTEN[10] ,GPIO bit 10 configuration" "Output,Input"
bitfld.long 0x04 9. " OUTPUTEN[9] ,GPIO bit 9 configuration" "Output,Input"
bitfld.long 0x04 8. " OUTPUTEN[8] ,GPIO bit 8 configuration" "Output,Input"
textline " "
bitfld.long 0x04 7. " OUTPUTEN[7] ,GPIO bit 7 configuration" "Output,Input"
bitfld.long 0x04 6. " OUTPUTEN[6] ,GPIO bit 6 configuration" "Output,Input"
bitfld.long 0x04 5. " OUTPUTEN[5] ,GPIO bit 5 configuration" "Output,Input"
bitfld.long 0x04 4. " OUTPUTEN[4] ,GPIO bit 4 configuration" "Output,Input"
textline " "
bitfld.long 0x04 3. " OUTPUTEN[3] ,GPIO bit 3 configuration" "Output,Input"
bitfld.long 0x04 2. " OUTPUTEN[2] ,GPIO bit 2 configuration" "Output,Input"
bitfld.long 0x04 1. " OUTPUTEN[1] ,GPIO bit 1 configuration" "Output,Input"
bitfld.long 0x04 0. " OUTPUTEN[0] ,GPIO bit 0 configuration" "Output,Input"
width 25.
rgroup.long 0x138++0x3
line.long 0x00 "GPIO_DATAIN,Sampled Input Data Register"
sif (cpuis("AM387*")||cpuis("DRA62*"))
bitfld.long 0x00 31. " DATAIN[31] ,Sampled Input 31" "Low,High"
bitfld.long 0x00 30. " DATAIN[30] ,Sampled Input 30" "Low,High"
bitfld.long 0x00 29. " DATAIN[29] ,Sampled Input 29" "Low,High"
bitfld.long 0x00 28. " DATAIN[28] ,Sampled Input 28" "Low,High"
textline " "
bitfld.long 0x00 27. " DATAIN[27] ,Sampled Input 27" "Low,High"
bitfld.long 0x00 26. " DATAIN[26] ,Sampled Input 26" "Low,High"
bitfld.long 0x00 25. " DATAIN[25] ,Sampled Input 25" "Low,High"
bitfld.long 0x00 24. " DATAIN[24] ,Sampled Input 24" "Low,High"
textline " "
bitfld.long 0x00 23. " DATAIN[23] ,Sampled Input 23" "Low,High"
bitfld.long 0x00 22. " DATAIN[22] ,Sampled Input 22" "Low,High"
bitfld.long 0x00 21. " DATAIN[21] ,Sampled Input 21" "Low,High"
bitfld.long 0x00 20. " DATAIN[20] ,Sampled Input 20" "Low,High"
textline " "
bitfld.long 0x00 19. " DATAIN[19] ,Sampled Input 19" "Low,High"
bitfld.long 0x00 18. " DATAIN[18] ,Sampled Input 18" "Low,High"
bitfld.long 0x00 17. " DATAIN[17] ,Sampled Input 17" "Low,High"
bitfld.long 0x00 16. " DATAIN[16] ,Sampled Input 16" "Low,High"
textline " "
bitfld.long 0x00 15. " DATAIN[15] ,Sampled Input 15" "Low,High"
bitfld.long 0x00 14. " DATAIN[14] ,Sampled Input 14" "Low,High"
bitfld.long 0x00 13. " DATAIN[13] ,Sampled Input 13" "Low,High"
bitfld.long 0x00 12. " DATAIN[12] ,Sampled Input 12" "Low,High"
textline " "
bitfld.long 0x00 11. " DATAIN[11] ,Sampled Input 11" "Low,High"
bitfld.long 0x00 10. " DATAIN[10] ,Sampled Input 10" "Low,High"
bitfld.long 0x00 9. " DATAIN[9] ,Sampled Input 9" "Low,High"
bitfld.long 0x00 8. " DATAIN[8] ,Sampled Input 8" "Low,High"
textline " "
bitfld.long 0x00 7. " DATAIN[7] ,Sampled Input 7" "Low,High"
bitfld.long 0x00 6. " DATAIN[6] ,Sampled Input 6" "Low,High"
bitfld.long 0x00 5. " DATAIN[5] ,Sampled Input 5" "Low,High"
bitfld.long 0x00 4. " DATAIN[4] ,Sampled Input 4" "Low,High"
textline " "
bitfld.long 0x00 3. " DATAIN[3] ,Sampled Input 3" "Low,High"
bitfld.long 0x00 2. " DATAIN[2] ,Sampled Input 2" "Low,High"
bitfld.long 0x00 1. " DATAIN[1] ,Sampled Input 1" "Low,High"
bitfld.long 0x00 0. " DATAIN[0] ,Sampled Input 0" "Low,High"
endif
width 25.
group.long 0x13c++0x3
line.long 0x00 "GPIO_DATAOUT,Output Data Register"
setclrfld.long 0x00 31. 0x58 31. 0x54 31. " DATAOUTPUT[31]_set/clr ,Output data bit 31 " "0,1"
setclrfld.long 0x00 30. 0x58 30. 0x54 30. " DATAOUTPUT[30]_set/clr ,Output data bit 30 " "0,1"
setclrfld.long 0x00 29. 0x58 29. 0x54 29. " DATAOUTPUT[29]_set/clr ,Output data bit 29 " "0,1"
setclrfld.long 0x00 28. 0x58 28. 0x54 28. " DATAOUTPUT[28]_set/clr ,Output data bit 28 " "0,1"
textline " "
setclrfld.long 0x00 27. 0x58 27. 0x54 27. " DATAOUTPUT[27]_set/clr ,Output data bit 27 " "0,1"
setclrfld.long 0x00 26. 0x58 26. 0x54 26. " DATAOUTPUT[26]_set/clr ,Output data bit 26 " "0,1"
setclrfld.long 0x00 25. 0x58 25. 0x54 25. " DATAOUTPUT[25]_set/clr ,Output data bit 25 " "0,1"
setclrfld.long 0x00 24. 0x58 24. 0x54 24. " DATAOUTPUT[24]_set/clr ,Output data bit 24 " "0,1"
textline " "
setclrfld.long 0x00 23. 0x58 23. 0x54 23. " DATAOUTPUT[23]_set/clr ,Output data bit 23 " "0,1"
setclrfld.long 0x00 22. 0x58 22. 0x54 22. " DATAOUTPUT[22]_set/clr ,Output data bit 22 " "0,1"
setclrfld.long 0x00 21. 0x58 21. 0x54 21. " DATAOUTPUT[21]_set/clr ,Output data bit 21 " "0,1"
setclrfld.long 0x00 20. 0x58 20. 0x54 20. " DATAOUTPUT[20]_set/clr ,Output data bit 20 " "0,1"
textline " "
setclrfld.long 0x00 19. 0x58 19. 0x54 19. " DATAOUTPUT[19]_set/clr ,Output data bit 19 " "0,1"
setclrfld.long 0x00 18. 0x58 18. 0x54 18. " DATAOUTPUT[18]_set/clr ,Output data bit 18 " "0,1"
setclrfld.long 0x00 17. 0x58 17. 0x54 17. " DATAOUTPUT[17]_set/clr ,Output data bit 17 " "0,1"
setclrfld.long 0x00 16. 0x58 16. 0x54 16. " DATAOUTPUT[16]_set/clr ,Output data bit 16 " "0,1"
textline " "
setclrfld.long 0x00 15. 0x58 15. 0x54 15. " DATAOUTPUT[15]_set/clr ,Output data bit 15 " "0,1"
setclrfld.long 0x00 14. 0x58 14. 0x54 14. " DATAOUTPUT[14]_set/clr ,Output data bit 14 " "0,1"
setclrfld.long 0x00 13. 0x58 13. 0x54 13. " DATAOUTPUT[13]_set/clr ,Output data bit 13 " "0,1"
setclrfld.long 0x00 12. 0x58 12. 0x54 12. " DATAOUTPUT[12]_set/clr ,Output data bit 12 " "0,1"
textline " "
setclrfld.long 0x00 11. 0x58 11. 0x54 11. " DATAOUTPUT[11]_set/clr ,Output data bit 11 " "0,1"
setclrfld.long 0x00 10. 0x58 10. 0x54 10. " DATAOUTPUT[10]_set/clr ,Output data bit 10 " "0,1"
setclrfld.long 0x00 9. 0x58 9. 0x54 9. " DATAOUTPUT[9]_set/clr ,Output data bit 9 " "0,1"
setclrfld.long 0x00 8. 0x58 8. 0x54 8. " DATAOUTPUT[8]_set/clr ,Output data bit 8 " "0,1"
textline " "
setclrfld.long 0x00 7. 0x58 7. 0x54 7. " DATAOUTPUT[7]_set/clr ,Output data bit 7 " "0,1"
setclrfld.long 0x00 6. 0x58 6. 0x54 6. " DATAOUTPUT[6]_set/clr ,Output data bit 6 " "0,1"
setclrfld.long 0x00 5. 0x58 5. 0x54 5. " DATAOUTPUT[5]_set/clr ,Output data bit 5 " "0,1"
setclrfld.long 0x00 4. 0x58 4. 0x54 4. " DATAOUTPUT[4]_set/clr ,Output data bit 4 " "0,1"
textline " "
setclrfld.long 0x00 3. 0x58 3. 0x54 3. " DATAOUTPUT[3]_set/clr ,Output data bit 3 " "0,1"
setclrfld.long 0x00 2. 0x58 2. 0x54 2. " DATAOUTPUT[2]_set/clr ,Output data bit 2 " "0,1"
setclrfld.long 0x00 1. 0x58 1. 0x54 1. " DATAOUTPUT[1]_set/clr ,Output data bit 1 " "0,1"
setclrfld.long 0x00 0. 0x58 0. 0x54 0. " DATAOUTPUT[0]_set/clr ,Output data bit 0 " "0,1"
width 25.
group.long 0x140++0x17
line.long 0x00 "GPIO_LEVELDETECT0,Low-level Detection Enable Register"
bitfld.long 0x00 31. " LEVELDETECT0[31] ,Low Level Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x00 30. " LEVELDETECT0[30] ,Low Level Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x00 29. " LEVELDETECT0[29] ,Low Level Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x00 28. " LEVELDETECT0[28] ,Low Level Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 27. " LEVELDETECT0[27] ,Low Level Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x00 26. " LEVELDETECT0[26] ,Low Level Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x00 25. " LEVELDETECT0[25] ,Low Level Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x00 24. " LEVELDETECT0[24] ,Low Level Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 23. " LEVELDETECT0[23] ,Low Level Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x00 22. " LEVELDETECT0[22] ,Low Level Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x00 21. " LEVELDETECT0[21] ,Low Level Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x00 20. " LEVELDETECT0[20] ,Low Level Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 19. " LEVELDETECT0[19] ,Low Level Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x00 18. " LEVELDETECT0[18] ,Low Level Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x00 17. " LEVELDETECT0[17] ,Low Level Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x00 16. " LEVELDETECT0[16] ,Low Level Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 15. " LEVELDETECT0[15] ,Low Level Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x00 14. " LEVELDETECT0[14] ,Low Level Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x00 13. " LEVELDETECT0[13] ,Low Level Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x00 12. " LEVELDETECT0[12] ,Low Level Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " LEVELDETECT0[11] ,Low Level Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x00 10. " LEVELDETECT0[10] ,Low Level Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x00 9. " LEVELDETECT0[9] ,Low Level Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x00 8. " LEVELDETECT0[8] ,Low Level Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " LEVELDETECT0[7] ,Low Level Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x00 6. " LEVELDETECT0[6] ,Low Level Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " LEVELDETECT0[5] ,Low Level Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x00 4. " LEVELDETECT0[4] ,Low Level Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " LEVELDETECT0[3] ,Low Level Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " LEVELDETECT0[2] ,Low Level Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " LEVELDETECT0[1] ,Low Level Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LEVELDETECT0[0] ,Low Level Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x04 "GPIO_LEVELDETECT1,High-level Detection Enable Register"
bitfld.long 0x04 31. " LEVELDETECT1[31] ,High Level Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x04 30. " LEVELDETECT1[30] ,High Level Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x04 29. " LEVELDETECT1[29] ,High Level Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x04 28. " LEVELDETECT1[28] ,High Level Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 27. " LEVELDETECT1[27] ,High Level Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x04 26. " LEVELDETECT1[26] ,High Level Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x04 25. " LEVELDETECT1[25] ,High Level Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x04 24. " LEVELDETECT1[24] ,High Level Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 23. " LEVELDETECT1[23] ,High Level Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x04 22. " LEVELDETECT1[22] ,High Level Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x04 21. " LEVELDETECT1[21] ,High Level Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x04 20. " LEVELDETECT1[20] ,High Level Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 19. " LEVELDETECT1[19] ,High Level Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x04 18. " LEVELDETECT1[18] ,High Level Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x04 17. " LEVELDETECT1[17] ,High Level Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x04 16. " LEVELDETECT1[16] ,High Level Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 15. " LEVELDETECT1[15] ,High Level Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x04 14. " LEVELDETECT1[14] ,High Level Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x04 13. " LEVELDETECT1[13] ,High Level Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x04 12. " LEVELDETECT1[12] ,High Level Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " LEVELDETECT1[11] ,High Level Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x04 10. " LEVELDETECT1[10] ,High Level Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x04 9. " LEVELDETECT1[9] ,High Level Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x04 8. " LEVELDETECT1[8] ,High Level Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " LEVELDETECT1[7] ,High Level Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x04 6. " LEVELDETECT1[6] ,High Level Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x04 5. " LEVELDETECT1[5] ,High Level Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x04 4. " LEVELDETECT1[4] ,High Level Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " LEVELDETECT1[3] ,High Level Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x04 2. " LEVELDETECT1[2] ,High Level Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x04 1. " LEVELDETECT1[1] ,High Level Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x04 0. " LEVELDETECT1[0] ,High Level Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x08 "GPIO_RISINGDETECT,Rising-edge Detection Enable Register"
bitfld.long 0x08 31. " RISINGDETECT[31] ,Rising Edge Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x08 30. " RISINGDETECT[30] ,Rising Edge Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x08 29. " RISINGDETECT[29] ,Rising Edge Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x08 28. " RISINGDETECT[28] ,Rising Edge Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 27. " RISINGDETECT[27] ,Rising Edge Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x08 26. " RISINGDETECT[26] ,Rising Edge Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x08 25. " RISINGDETECT[25] ,Rising Edge Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x08 24. " RISINGDETECT[24] ,Rising Edge Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 23. " RISINGDETECT[23] ,Rising Edge Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x08 22. " RISINGDETECT[22] ,Rising Edge Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x08 21. " RISINGDETECT[21] ,Rising Edge Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x08 20. " RISINGDETECT[20] ,Rising Edge Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " RISINGDETECT[19] ,Rising Edge Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x08 18. " RISINGDETECT[18] ,Rising Edge Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x08 17. " RISINGDETECT[17] ,Rising Edge Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x08 16. " RISINGDETECT[16] ,Rising Edge Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " RISINGDETECT[15] ,Rising Edge Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x08 14. " RISINGDETECT[14] ,Rising Edge Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x08 13. " RISINGDETECT[13] ,Rising Edge Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x08 12. " RISINGDETECT[12] ,Rising Edge Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " RISINGDETECT[11] ,Rising Edge Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x08 10. " RISINGDETECT[10] ,Rising Edge Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x08 9. " RISINGDETECT[9] ,Rising Edge Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x08 8. " RISINGDETECT[8] ,Rising Edge Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " RISINGDETECT[7] ,Rising Edge Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x08 6. " RISINGDETECT[6] ,Rising Edge Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x08 5. " RISINGDETECT[5] ,Rising Edge Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x08 4. " RISINGDETECT[4] ,Rising Edge Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RISINGDETECT[3] ,Rising Edge Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x08 2. " RISINGDETECT[2] ,Rising Edge Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x08 1. " RISINGDETECT[1] ,Rising Edge Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x08 0. " RISINGDETECT[0] ,Rising Edge Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x0c "GPIO_FALLINGDETECT,Falling-edge Detection Enable Register"
bitfld.long 0x0c 31. " FALLINGDETECT[31] ,Falling Edge Interrupt 31 Enable" "Disabled,Enabled"
bitfld.long 0x0c 30. " FALLINGDETECT[30] ,Falling Edge Interrupt 30 Enable" "Disabled,Enabled"
bitfld.long 0x0c 29. " FALLINGDETECT[29] ,Falling Edge Interrupt 29 Enable" "Disabled,Enabled"
bitfld.long 0x0c 28. " FALLINGDETECT[28] ,Falling Edge Interrupt 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 27. " FALLINGDETECT[27] ,Falling Edge Interrupt 27 Enable" "Disabled,Enabled"
bitfld.long 0x0c 26. " FALLINGDETECT[26] ,Falling Edge Interrupt 26 Enable" "Disabled,Enabled"
bitfld.long 0x0c 25. " FALLINGDETECT[25] ,Falling Edge Interrupt 25 Enable" "Disabled,Enabled"
bitfld.long 0x0c 24. " FALLINGDETECT[24] ,Falling Edge Interrupt 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 23. " FALLINGDETECT[23] ,Falling Edge Interrupt 23 Enable" "Disabled,Enabled"
bitfld.long 0x0c 22. " FALLINGDETECT[22] ,Falling Edge Interrupt 22 Enable" "Disabled,Enabled"
bitfld.long 0x0c 21. " FALLINGDETECT[21] ,Falling Edge Interrupt 21 Enable" "Disabled,Enabled"
bitfld.long 0x0c 20. " FALLINGDETECT[20] ,Falling Edge Interrupt 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 19. " FALLINGDETECT[19] ,Falling Edge Interrupt 19 Enable" "Disabled,Enabled"
bitfld.long 0x0c 18. " FALLINGDETECT[18] ,Falling Edge Interrupt 18 Enable" "Disabled,Enabled"
bitfld.long 0x0c 17. " FALLINGDETECT[17] ,Falling Edge Interrupt 17 Enable" "Disabled,Enabled"
bitfld.long 0x0c 16. " FALLINGDETECT[16] ,Falling Edge Interrupt 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 15. " FALLINGDETECT[15] ,Falling Edge Interrupt 15 Enable" "Disabled,Enabled"
bitfld.long 0x0c 14. " FALLINGDETECT[14] ,Falling Edge Interrupt 14 Enable" "Disabled,Enabled"
bitfld.long 0x0c 13. " FALLINGDETECT[13] ,Falling Edge Interrupt 13 Enable" "Disabled,Enabled"
bitfld.long 0x0c 12. " FALLINGDETECT[12] ,Falling Edge Interrupt 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 11. " FALLINGDETECT[11] ,Falling Edge Interrupt 11 Enable" "Disabled,Enabled"
bitfld.long 0x0c 10. " FALLINGDETECT[10] ,Falling Edge Interrupt 10 Enable" "Disabled,Enabled"
bitfld.long 0x0c 9. " FALLINGDETECT[9] ,Falling Edge Interrupt 9 Enable" "Disabled,Enabled"
bitfld.long 0x0c 8. " FALLINGDETECT[8] ,Falling Edge Interrupt 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 7. " FALLINGDETECT[7] ,Falling Edge Interrupt 7 Enable" "Disabled,Enabled"
bitfld.long 0x0c 6. " FALLINGDETECT[6] ,Falling Edge Interrupt 6 Enable" "Disabled,Enabled"
bitfld.long 0x0c 5. " FALLINGDETECT[5] ,Falling Edge Interrupt 5 Enable" "Disabled,Enabled"
bitfld.long 0x0c 4. " FALLINGDETECT[4] ,Falling Edge Interrupt 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 3. " FALLINGDETECT[3] ,Falling Edge Interrupt 3 Enable" "Disabled,Enabled"
bitfld.long 0x0c 2. " FALLINGDETECT[2] ,Falling Edge Interrupt 2 Enable" "Disabled,Enabled"
bitfld.long 0x0c 1. " FALLINGDETECT[1] ,Falling Edge Interrupt 1 Enable" "Disabled,Enabled"
bitfld.long 0x0c 0. " FALLINGDETECT[0] ,Falling Edge Interrupt 0 Enable" "Disabled,Enabled"
line.long 0x10 "GPIO_DEBOUNCENABLE,Debounce Enable Register"
bitfld.long 0x10 31. " DEBOUNCEENABLE[31] ,Input Debounce 31 Enable" "Disabled,Enabled"
bitfld.long 0x10 30. " DEBOUNCEENABLE[30] ,Input Debounce 30 Enable" "Disabled,Enabled"
bitfld.long 0x10 29. " DEBOUNCEENABLE[29] ,Input Debounce 29 Enable" "Disabled,Enabled"
bitfld.long 0x10 28. " DEBOUNCEENABLE[28] ,Input Debounce 28 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 27. " DEBOUNCEENABLE[27] ,Input Debounce 27 Enable" "Disabled,Enabled"
bitfld.long 0x10 26. " DEBOUNCEENABLE[26] ,Input Debounce 26 Enable" "Disabled,Enabled"
bitfld.long 0x10 25. " DEBOUNCEENABLE[25] ,Input Debounce 25 Enable" "Disabled,Enabled"
bitfld.long 0x10 24. " DEBOUNCEENABLE[24] ,Input Debounce 24 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 23. " DEBOUNCEENABLE[23] ,Input Debounce 23 Enable" "Disabled,Enabled"
bitfld.long 0x10 22. " DEBOUNCEENABLE[22] ,Input Debounce 22 Enable" "Disabled,Enabled"
bitfld.long 0x10 21. " DEBOUNCEENABLE[21] ,Input Debounce 21 Enable" "Disabled,Enabled"
bitfld.long 0x10 20. " DEBOUNCEENABLE[20] ,Input Debounce 20 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 19. " DEBOUNCEENABLE[19] ,Input Debounce 19 Enable" "Disabled,Enabled"
bitfld.long 0x10 18. " DEBOUNCEENABLE[18] ,Input Debounce 18 Enable" "Disabled,Enabled"
bitfld.long 0x10 17. " DEBOUNCEENABLE[17] ,Input Debounce 17 Enable" "Disabled,Enabled"
bitfld.long 0x10 16. " DEBOUNCEENABLE[16] ,Input Debounce 16 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 15. " DEBOUNCEENABLE[15] ,Input Debounce 15 Enable" "Disabled,Enabled"
bitfld.long 0x10 14. " DEBOUNCEENABLE[14] ,Input Debounce 14 Enable" "Disabled,Enabled"
bitfld.long 0x10 13. " DEBOUNCEENABLE[13] ,Input Debounce 13 Enable" "Disabled,Enabled"
bitfld.long 0x10 12. " DEBOUNCEENABLE[12] ,Input Debounce 12 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 11. " DEBOUNCEENABLE[11] ,Input Debounce 11 Enable" "Disabled,Enabled"
bitfld.long 0x10 10. " DEBOUNCEENABLE[10] ,Input Debounce 10 Enable" "Disabled,Enabled"
bitfld.long 0x10 9. " DEBOUNCEENABLE[9] ,Input Debounce 9 Enable" "Disabled,Enabled"
bitfld.long 0x10 8. " DEBOUNCEENABLE[8] ,Input Debounce 8 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " DEBOUNCEENABLE[7] ,Input Debounce 7 Enable" "Disabled,Enabled"
bitfld.long 0x10 6. " DEBOUNCEENABLE[6] ,Input Debounce 6 Enable" "Disabled,Enabled"
bitfld.long 0x10 5. " DEBOUNCEENABLE[5] ,Input Debounce 5 Enable" "Disabled,Enabled"
bitfld.long 0x10 4. " DEBOUNCEENABLE[4] ,Input Debounce 4 Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 3. " DEBOUNCEENABLE[3] ,Input Debounce 3 Enable" "Disabled,Enabled"
bitfld.long 0x10 2. " DEBOUNCEENABLE[2] ,Input Debounce 2 Enable" "Disabled,Enabled"
bitfld.long 0x10 1. " DEBOUNCEENABLE[1] ,Input Debounce 1 Enable" "Disabled,Enabled"
bitfld.long 0x10 0. " DEBOUNCEENABLE[0] ,Input Debounce 0 Enable" "Disabled,Enabled"
line.long 0x14 "GPIO_DEBOUNCINGTIME,Debounce Time Register"
hexmask.long.byte 0x14 0.--7. 1. " DEBOUNCETIME ,Input Debouncing Value (in 31 ms steps)"
width 11.
tree.end
tree.end
tree "GPMC (General Purpose Memory Controller)"
base ad:0x50000000
width 23.
tree "Miscellaneous Registers"
rgroup.long 0x00++0x3
line.long 0x00 "GPMC_REVISION,IP Revision Code"
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
group.long 0x10++0x3
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||cpuis("AM389*")||cpuis("AM335*")||cpuis("C6A816*")||cpuis("AM387*")||cpuis("DRA6*")||cpu()=="DM8148"||cpu()=="DM8147"||cpu()=="C6A8148"||cpu()=="C6A8147"||cpu()=="C6A8143"||cpuis("DM8165")||cpuis("DM8166")||cpuis("DM8167")||cpuis("DM8168")||cpuis("DM8165DSP")||cpuis("DM8166DSP")||cpuis("DM8167DSP")||cpuis("DM8168DSP"))
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The OCP Interface"
bitfld.long 0x00 3.--4. " SIDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
else
line.long 0x00 "GPMC_SYSCONFIG,Various Parameters Of The Interconnect Control"
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,?..."
endif
textline " "
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
textline " "
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Applied"
rgroup.long 0x14++0x3
line.long 0x00 "GPMC_SYSSTATUS,Status Information About The Module"
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.long 0x18++0x7
line.long 0x00 "GPMC_IRQSTATUS,Interrupt Status Register"
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
eventfld.long 0x00 11. " WAIT3EDGEDETECTIONSTATUS ,Status of the Wait3 Edge Detection interrupt" "Not detected,Detected"
textline " "
eventfld.long 0x00 10. " WAIT2EDGEDETECTIONSTATUS ,Status of the Wait2 Edge Detection interrupt" "Not detected,Detected"
textline " "
endif
eventfld.long 0x00 9. " WAIT1EDGEDETECTIONSTATUS ,Status of the Wait1 Edge Detection interrupt" "Not detected,Detected"
textline " "
eventfld.long 0x00 8. " WAIT0EDGEDETECTIONSTATUS ,Status of the Wait0 Edge Detection interrupt" "Not detected,Detected"
textline " "
eventfld.long 0x00 1. " TERMINALCOUNTSTATUS ,Status of the TerminalCountEvent interrupt (COUNTVALUE)" ">0,=0"
textline " "
eventfld.long 0x00 0. " FIFOEVENTSTATUS ,Status of the FIFOEvent interrupt" "<FIFOTHRESHOLD,=FIFOTHRESHOLD"
line.long 0x04 "GPMC_IRQENABLE,Interrupt Enable Register"
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
bitfld.long 0x04 11. " WAIT3EDGEDETECTIONENABLE ,Enables the Wait3 Edge Detection interrupt" "Masked,Enabled"
textline " "
bitfld.long 0x04 10. " WAIT2EDGEDETECTIONENABLE ,Enables the Wait2 Edge Detection interrupt" "Masked,Enabled"
textline " "
endif
bitfld.long 0x04 9. " WAIT1EDGEDETECTIONENABLE ,Enables the Wait1 Edge Detection interrupt" "Masked,Enabled"
textline " "
bitfld.long 0x04 8. " WAIT0EDGEDETECTIONENABLE ,Enables the Wait0 Edge Detection interrupt" "Masked,Enabled"
textline " "
bitfld.long 0x04 1. " TERMINALCOUNTEVENTENABLE ,Enables TerminalCountEvent interrupt" "Masked,Enabled"
textline " "
bitfld.long 0x04 0. " FIFOEVENTENABLE ,Enables the FIFOEvent interrupt" "Masked,Enabled"
group.long 0x40++0x3
line.long 0x00 "GPMC_TIMEOUT_CONTROL,Start Value Of The Timeout Counter Set Register"
hexmask.long.word 0x00 4.--12. 1. " TIMEOUTSTARTVALUE ,Start value of the time-out counter"
textline " "
bitfld.long 0x00 0. " TIMEOUTENABLE ,Enable bit of the TimeOut feature" "Disabled,Enabled"
rgroup.long 0x44++0x03
line.long 0x00 "GPMC_ERR_ADDRESS,Stores The Address Of The Illegal Access"
hexmask.long 0x00 0.--30. 1. " ILLEGALADD ,Address of illegal access"
group.long 0x48++0x03
line.long 0x00 "GPMC_ERR_TYPE,Stores The Type Of Error"
bitfld.long 0x00 8.--10. " ILLEGALMCMD ,System Command of the transaction that caused the error" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 4. " ERRORNOTSUPPADD ,Not supported Address error" "No error,Error"
textline " "
bitfld.long 0x00 3. " ERRORNOTSUPPMCMD ,Not supported Command error" "No error,Error"
textline " "
bitfld.long 0x00 2. " ERRORTIMEOUT ,Time-out error" "No error,Error"
textline " "
bitfld.long 0x00 0. " ERRORVALID ,Error validity status" "Not valid,Valid"
group.long 0x50++0x7
line.long 0x00 "GPMC_CONFIG,Global Configuration Of The GPMC Module"
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
bitfld.long 0x00 11. " WAIT3PINPOLARITY ,Selects the polarity of input pin WAIT3" "Low,High"
textline " "
bitfld.long 0x00 10. " WAIT2PINPOLARITY ,Selects the polarity of input pin WAIT2" "Low,High"
textline " "
endif
bitfld.long 0x00 9. " WAIT1PINPOLARITY ,Selects the polarity of input pin WAIT1" "Low,High"
textline " "
bitfld.long 0x00 8. " WAIT0PINPOLARITY ,Selects the polarity of input pin WAIT0" "Low,High"
textline " "
sif (!(cpuis("AM387*")))
bitfld.long 0x00 4. " WRITEPROTECT ,Controls the /WP output pin level" "Low,High"
textline " "
endif
sif (cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "Not supported,Supported"
else
bitfld.long 0x00 1. " LIMITEDADDRESS ,Limited Address device support" "No effect,A26-A11 not modified"
endif
textline " "
bitfld.long 0x00 0. " NANDFORCEPOSTEDWRITE ,Enables the Force Posted Write feature to NAND Cmd/Add/Data location" "Disabled,Enabled"
rgroup.long 0x54++0x03
line.long 0x00 "GPMC_STATUS,Global Status Bits Of The GPMC Module"
sif (((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&(!(cpuis("AM389*")))&&(!(cpuis("AM335*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(!(cpuis("DRA6*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143"))
bitfld.long 0x00 11. " WAIT3STATUS ,Copy of input pin WAIT3" "Asserted,De-asserted"
textline " "
bitfld.long 0x00 10. " WAIT2STATUS ,Copy of input pin WAIT2" "Asserted,De-asserted"
textline " "
endif
bitfld.long 0x00 9. " WAIT1STATUS ,Copy of input pin WAIT1" "Asserted,De-asserted"
textline " "
bitfld.long 0x00 8. " WAIT0STATUS ,Copy of input pin WAIT0" "Asserted,De-asserted"
textline " "
bitfld.long 0x00 0. " EMPTYWRITEBUFFERSTATUS ,Stores the empty status of the write buffer" "Not empty,Empty"
group.long 0x1E0++0x7
line.long 0x00 "GPMC_PREFETCH_CONFIG1,Prefetch Engine Configuration 1"
bitfld.long 0x00 28.--30. " CYCLEOPTIMIZATION ,Defines the number of GPMC_FCLK cycles to be subtracted" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 27. " ENABLEOPTIMIZEDACCESS ,Enables access cycle optimization" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24.--26. " ENGINECSSELECTOR ,/CS where Prefetch Postwrite engine is active" "/CS0,/CS1,/CS2,/CS3,/CS4,/CS5,/CS6,/CS7"
textline " "
bitfld.long 0x00 23. " PFPWENROUNDROBIN ,PFPW RoundRobin arbitration enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16.--19. " PFPWWEIGHTEDPRIO ,Arbitration between a direct memory access and a PFPW engine access (next access is granted to the PFPW engine)" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
textline " "
hexmask.long.byte 0x00 8.--14. 1. " FIFOTHRESHOLD ,Maximum number of bytes read/write from the FIFO"
textline " "
bitfld.long 0x00 7. " ENABLEENGINE ,Prefetch Postwite engine enable" "Disabled,Enabled"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,?..."
else
bitfld.long 0x00 4.--5. " WAITPINSELECTOR ,Selects which wait pin edge detector should start the engine in synchronized mode" "Wait0EdgeDetection,Wait1EdgeDetection,Wait2EdgeDetection,Wait3EdgeDetection"
endif
textline " "
bitfld.long 0x00 3. " SYNCHROMODE ,Selects when the engine starts the access to CS" "StartEngine set,StartEngine set/wait to nonwait edge"
textline " "
bitfld.long 0x00 2. " DMAMODE ,Selects interrupt synchronization or DMA request synchronization" "Interrupt,DMA request"
textline " "
bitfld.long 0x00 0. " ACCESSMODE ,Selects prefetch read or write-posting accesses" "Prefetch read,Write-posting"
line.long 0x04 "GPMC_PREFETCH_CONFIG2,Prefetch Engine Configuration 2"
hexmask.long.word 0x04 0.--13. 1. " TRANSFERCOUNT ,Number of bytes to be read/write by the engine to the selected CS"
group.long 0x1EC++0x03
line.long 0x00 "GPMC_PREFETCH_CONTROL,Prefetch Engine Control"
bitfld.long 0x00 0. " STARTENGINE ,Reset FIFO pointer and start the engine" "Stopped,Running"
rgroup.long 0x1f0++0x03
line.long 0x00 "GPMC_PREFETCH_STATUS,Prefetch Engine Status"
hexmask.long.byte 0x00 24.--30. 1. " FIFOPOINTER ,Number of available bytes to be read/write"
textline " "
bitfld.long 0x00 16. " FIFOTHRESHOLDSTATUS ,Set when FIFOPOINTER exceeds FIFOTHRESHOLD value" "<=FIFOTHRESHOLD,>FIFOTHRESHOLD"
textline " "
hexmask.long.word 0x00 0.--13. 1. " COUNTVALUE ,Number of remaining bytes to be read/write"
group.long 0x1f4++0x0b
line.long 0x00 "GPMC_ECC_CONFIG,ECC Configuration"
bitfld.long 0x00 16. " ECCALGORITHM ,ECC algorithm used" "Hamming,BCH"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*")||(cpuis("AM335*"))||cpuis("C6A816*"))||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 12.--13. " ECCBCHTSEL ,Error correction capability used for BCH" "t=4,t=8,t=16,?..."
else
bitfld.long 0x00 12. " ECCBCHT8 ,Error correction capability used for BCH" "t=4,t=8"
endif
textline " "
bitfld.long 0x00 8.--11. " ECCWRAPMODE ,Spare area organization definition for the BCH algorithm" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " ECC16B ,Selects an ECC calculated on 16 columns" "8 columns,16 columns"
textline " "
bitfld.long 0x00 4.--6. " ECCTOPSECTOR ,Number of sectors to process with the BCH algorithm" "1,2,3,4,5,6,7,8"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143"))
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,?..."
else
bitfld.long 0x00 1.--3. " ECCCS ,Selects the CS where ECC is computed" "Chip-select 0,Chip-select 1,Chip-select 2,Chip-select 3,Chip-select 4,Chip-select 5,Chip-select 6,Chip-select 7"
endif
textline " "
bitfld.long 0x00 0. " ECCENABLE ,Enables the ECC feature" "Disabled,Enabled"
line.long 0x04 "GPMC_ECC_CONTROL,ECC Control"
eventfld.long 0x04 8. " ECCCLEAR ,Clear all ECC result registers" "No effect,Clear"
textline " "
bitfld.long 0x04 0.--3. " ECCPOINTER ,ECC result register" "ECC engine disabled,ECC result register 1,ECC result register 2,ECC result register 3,ECC result register 4,ECC result register 5,ECC result register 6,ECC result register 7,ECC result register 8,ECC result register 9,?..."
line.long 0x08 "GPMC_ECC_SIZE_CONFIG,ECC Size"
hexmask.long.byte 0x08 22.--29. 1. " ECCSIZE1 ,Defines ECC size 1"
hexmask.long.byte 0x08 12.--19. 1. " ECCSIZE0 ,Defines ECC size 0"
textline " "
bitfld.long 0x08 8. " ECC9RESULTSIZE ,Selects ECC size for ECC 9 result register" "ECCSize0,ECCSize1"
bitfld.long 0x08 7. " ECC8RESULTSIZE ,Selects ECC size for ECC 8 result register" "ECCSize0,ECCSize1"
textline " "
bitfld.long 0x08 6. " ECC7RESULTSIZE ,Selects ECC size for ECC 7 result register" "ECCSize0,ECCSize1"
bitfld.long 0x08 5. " ECC6RESULTSIZE ,Selects ECC size for ECC 6 result register" "ECCSize0,ECCSize1"
textline " "
bitfld.long 0x08 4. " ECC5RESULTSIZE ,Selects ECC size for ECC 5 result register" "ECCSize0,ECCSize1"
bitfld.long 0x08 3. " ECC4RESULTSIZE ,Selects ECC size for ECC 4 result register" "ECCSize0,ECCSize1"
textline " "
bitfld.long 0x08 2. " ECC3RESULTSIZE ,Selects ECC size for ECC 3 result register" "ECCSize0,ECCSize1"
bitfld.long 0x08 1. " ECC2RESULTSIZE ,Selects ECC size for ECC 2 result register" "ECCSize0,ECCSize1"
textline " "
bitfld.long 0x08 0. " ECC1RESULTSIZE ,Selects ECC size for ECC 1 result register" "ECCSize0,ECCSize1"
group.long 0x2D0++0x3
line.long 0x00 "GPMC_BCH_SWDATA,Pass Data To The BCH ECC Calculator"
hexmask.long.word 0x00 0.--15. 1. " BCH_DATA ,Data to be included in the BCH calculation"
tree.end
tree "Chip Select #0"
group.long 0x60++0x3
line.long 0x00 "GPMC_CONFIG1_CS0,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x60+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS0,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,0CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,0CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,0CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,0CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x60+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS0,0ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,0ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,0ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,0ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,0ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,0ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,0ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x60+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS0,0WE and 0OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,0WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,0WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,0WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,0OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,0OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,0OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,0OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,0OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x60+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS0,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x60+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS0,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x60+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS0,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x60+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS0,Address Location"
wgroup.long (0x60+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS0,Address Location"
group.long (0x60+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS0,Address Location"
tree.end
tree "Chip Select #1"
group.long 0x90++0x3
line.long 0x00 "GPMC_CONFIG1_CS1,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x90+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS1,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,1CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,1CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,1CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,1CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x90+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS1,1ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,1ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,1ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,1ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,1ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,1ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,1ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x90+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS1,1WE and 1OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,1WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,1WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,1WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,1OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,1OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,1OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,1OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,1OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x90+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS1,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x90+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS1,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x90+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS1,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x90+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS1,Address Location"
wgroup.long (0x90+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS1,Address Location"
group.long (0x90+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS1,Address Location"
tree.end
tree "Chip Select #2"
group.long 0xC0++0x3
line.long 0x00 "GPMC_CONFIG1_CS2,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0xC0+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS2,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,2CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,2CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,2CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,2CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xC0+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS2,2ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,2ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,2ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,2ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,2ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,2ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,2ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xC0+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS2,2WE and 2OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,2WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,2WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,2WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,2OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,2OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,2OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,2OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,2OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xC0+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS2,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0xC0+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS2,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xC0+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS2,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0xC0+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS2,Address Location"
wgroup.long (0xC0+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS2,Address Location"
group.long (0xC0+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS2,Address Location"
tree.end
tree "Chip Select #3"
group.long 0xF0++0x3
line.long 0x00 "GPMC_CONFIG1_CS3,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0xF0+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS3,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,3CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,3CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,3CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,3CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xF0+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS3,3ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,3ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,3ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,3ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,3ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,3ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,3ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xF0+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS3,3WE and 3OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,3WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,3WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,3WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,3OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,3OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,3OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,3OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,3OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xF0+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS3,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0xF0+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS3,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0xF0+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS3,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0xF0+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS3,Address Location"
wgroup.long (0xF0+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS3,Address Location"
group.long (0xF0+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS3,Address Location"
tree.end
tree "Chip Select #4"
group.long 0x120++0x3
line.long 0x00 "GPMC_CONFIG1_CS4,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x120+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS4,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,4CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,4CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,4CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,4CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x120+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS4,4ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,4ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,4ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,4ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,4ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,4ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,4ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x120+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS4,4WE and 4OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,4WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,4WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,4WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,4OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,4OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,4OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,4OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,4OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x120+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS4,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x120+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS4,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x120+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS4,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x120+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS4,Address Location"
wgroup.long (0x120+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS4,Address Location"
group.long (0x120+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS4,Address Location"
tree.end
tree "Chip Select #5"
group.long 0x150++0x3
line.long 0x00 "GPMC_CONFIG1_CS5,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x150+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS5,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,5CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,5CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,5CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,5CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x150+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS5,5ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,5ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,5ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,5ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,5ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,5ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,5ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x150+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS5,5WE and 5OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,5WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,5WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,5WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,5OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,5OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,5OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,5OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,5OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x150+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS5,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x150+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS5,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x150+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS5,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x150+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS5,Address Location"
wgroup.long (0x150+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS5,Address Location"
group.long (0x150+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS5,Address Location"
tree.end
tree "Chip Select #6"
group.long 0x180++0x3
line.long 0x00 "GPMC_CONFIG1_CS6,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x180+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS6,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,6CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,6CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,6CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,6CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x180+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS6,6ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,6ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,6ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,6ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,6ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,6ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,6ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x180+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS6,6WE and 6OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,6WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,6WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,6WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,6OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,6OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,6OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,6OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,6OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x180+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS6,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x180+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS6,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x180+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS6,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x180+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS6,Address Location"
wgroup.long (0x180+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS6,Address Location"
group.long (0x180+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS6,Address Location"
tree.end
tree "Chip Select #7"
group.long 0x1B0++0x3
line.long 0x00 "GPMC_CONFIG1_CS7,Signal Control Parameters Per Chip-select"
bitfld.long 0x00 31. " WRAPBURST ,Enables the wrapping burst capability" "Not supported,Supported"
textline " "
bitfld.long 0x00 30. " READMULTIPLE ,Selects the read single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 29. " READTYPE ,Selects the read mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 28. " WRITEMULTIPLE ,Selects the write single or multiple access" "Single,Multiple"
textline " "
bitfld.long 0x00 27. " WRITETYPE ,Selects the write mode operation" "Asynchronous,Synchronous"
textline " "
bitfld.long 0x00 25.--26. " CLKACTIVATIONTIME ,Output GPMC_CLK activation time" "At StartAccess,One cycle after,Two cycles after,?..."
textline " "
bitfld.long 0x00 23.--24. " ATTACHEDDEVICEPAGELENGTH ,Specifies the attached device page (burst) length" "4 Words,8 Words,16 Words,?..."
textline " "
bitfld.long 0x00 22. " WAITREADMONITORING ,Wait monitoring configuration for Read accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 21. " WAITWRITEMONITORING ,Wait monitoring configuration for Write accesses" "Not monitored,Monitored"
textline " "
bitfld.long 0x00 18.--19. " WAITMONITORINGTIME ,Selects input pin Wait monitoring time" "With valid data,One cycle before,Two cycles before,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,?..."
else
bitfld.long 0x00 16.--17. " WAITPINSELECT ,Input WAIT pin for this chip-select" "WAIT0,WAIT1,WAIT2,WAIT3"
endif
textline " "
bitfld.long 0x00 12.--13. " DEVICESIZE ,Device size attached" "8 bit,16 bit,?..."
textline " "
bitfld.long 0x00 10.--11. " DEVICETYPE ,Selects the attached device type" "NOR Flash like,Reserved,NAND Flash like,?..."
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||cpuis("AM387*")||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Non-multiplexed,AAD-multiplexed,Addr/data-multiplexed,?..."
else
bitfld.long 0x00 9. " MUXADDDATA ,Enables the address/data-multiplexed protocol" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 4. " TIMEPARAGRANULARITY ,Signals timing latencies scalar factor" "x1 latencies,x2 latencies"
textline " "
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||cpuis("C6A816*"))
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/3,1/4"
else
bitfld.long 0x00 0.--1. " GPMCFCLKDIVIDER ,Divides the GPMC_FCLK clock" "1,1/2,1/4,1/8"
endif
group.long (0x1B0+0x04)++0x3
line.long 0x00 "GPMC_CONFIG2_CS7,Chip-select Signal Timing Parameter Configuration"
bitfld.long 0x00 16.--20. " CSWROFFTIME ,7CS de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " CSRDOFFTIME ,7CS de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " CSEXTRADELAY ,7CS Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 0.--3. " CSONTIME ,7CS assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x1B0+0x08)++0x3
line.long 0x00 "GPMC_CONFIG3_CS7,7ADV Signal Timing Parameter Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 28.--30. " ADVAADMUXWROFFTIME ,7ADV de-assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 24.--26. " ADVAADMUXRDOFFTIME ,7ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 16.--20. " ADVWROFFTIME ,7ADV de-assertion time from start-cycle time for write accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " ADVRDOFFTIME ,7ADV de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " ADVEXTRADELAY ,7ADV Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " ADVAADMUXONTIME ,7ADV assertion time for first address phase when using the AAD-Mux protocol (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " ADVONTIME ,7ADV assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x1B0+0x0C)++0x3
line.long 0x00 "GPMC_CONFIG4_CS7,7WE and 7OE signals timing parameter configuration"
bitfld.long 0x00 24.--28. " WEOFFTIME ,7WE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 23. " WEEXTRADELAY ,7WE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
bitfld.long 0x00 16.--19. " WEONTIME ,7WE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 13.--15. " OEAADMUXOFFTIME ,7OE de-assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 8.--12. " OEOFFTIME ,7OE de-assertion time from start-cycle time for read accesses (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 7. " OEEXTRADELAY ,7OE Add Extra Half GPMC_FCLK cycle" "Not delayed,Delayed"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 4.--6. " OEAADMUXONTIME ,7OE assertion time for the first address phase in an AAD-Mux access (GPMC_FCLK cycle)" "0,1,2,3,4,5,6,7"
textline " "
endif
bitfld.long 0x00 0.--3. " OEONTIME ,7OE assertion time from start-cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x1B0+0x10)++0x3
line.long 0x00 "GPMC_CONFIG5_CS7,ACCESSTIME And CYCLETIME Timing Parameters Configuration"
bitfld.long 0x00 24.--27. " PAGEBURSTACCESSTIME ,Delay between successive words in a multiple access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 16.--20. " RDACCESSTIME ,Delay between start-cycle time and first data valid" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--12. " WRCYCLETIME ,Total write cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 0.--4. " RDCYCLETIME ,Total read cycle time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long (0x1B0+0x14)++0x3
line.long 0x00 "GPMC_CONFIG6_CS7,WrAccessTime And WrDataOnADmuxBus And CYCLE2CYCLE And BUSTURNAROUND Parameters Configuration"
bitfld.long 0x00 24.--28. " WRACCESSTIME ,Delay from start access time to the GPMC_FCLK rising edge" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 16.--19. " WRDATAONADMUXBUS ,Specifies on which GPMC_FCLK first data of the synchronous burst write is driven" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 8.--11. " CYCLE2CYCLEDELAY ,Chip-select high pulse delay between two successive accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " CYCLE2CYCLESAMECSEN ,Add Cycle2CycleDelay to the same chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 6. " CYCLE2CYCLEDIFFCSEN ,Add Cycle2CycleDelay to a different chip-select" "No delay,Delay"
textline " "
bitfld.long 0x00 0.--3. " BUSTURNAROUND ,Bus turn around latency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long (0x1B0+0x18)++0x3
line.long 0x00 "GPMC_CONFIG7_CS7,Chip-select Address Mapping Configuration"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "256 MB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
else
bitfld.long 0x00 8.--11. " MASKADDRESS ,Chip-select mask address" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,128 MB,Reserved,Reserved,Reserved,64MB,Reserved,32MB,16MB"
endif
textline " "
bitfld.long 0x00 6. " CSVALID ,Chip-select enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " BASEADDRESS ,Chip-select base address"
wgroup.long (0x1B0+0x1C)++0x3
line.long 0x00 "GPMC_NAND_COMMAND_CS7,Address Location"
wgroup.long (0x1B0+0x20)++0x3
line.long 0x00 "GPMC_NAND_ADDRESS_CS7,Address Location"
group.long (0x1B0+0x24)++0x3
line.long 0x00 "GPMC_NAND_DATA_CS7,Address Location"
tree.end
tree "Result Registers"
width 19.
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rgroup.long 0x200++0x23
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
else
group.long 0x200++0x23
line.long 0x0 "GPMC_ECC1_RESULT,ECC1 Result Register"
bitfld.long 0x0 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x0 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x0 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x0 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x0 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x0 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x0 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x0 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x0 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x0 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x0 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x0 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x0 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x0 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x0 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x0 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x0 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x0 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x0 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x0 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x0 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x0 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x0 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x0 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x4 "GPMC_ECC2_RESULT,ECC2 Result Register"
bitfld.long 0x4 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x4 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x4 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x4 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x4 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x4 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x4 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x4 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x4 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x4 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x4 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x4 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x4 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x4 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x4 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x4 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x4 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x4 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x4 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x4 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x4 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x4 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x4 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x4 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x8 "GPMC_ECC3_RESULT,ECC3 Result Register"
bitfld.long 0x8 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x8 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x8 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x8 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x8 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x8 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x8 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x8 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x8 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x8 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x8 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x8 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x8 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x8 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x8 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x8 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x8 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x8 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x8 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x8 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x8 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x8 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x8 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x8 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0xC "GPMC_ECC4_RESULT,ECC4 Result Register"
bitfld.long 0xC 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0xC 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0xC 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0xC 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0xC 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0xC 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0xC 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0xC 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0xC 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0xC 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0xC 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0xC 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0xC 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0xC 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0xC 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0xC 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0xC 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0xC 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0xC 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0xC 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0xC 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0xC 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0xC 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0xC 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x10 "GPMC_ECC5_RESULT,ECC5 Result Register"
bitfld.long 0x10 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x10 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x10 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x10 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x10 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x10 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x10 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x10 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x10 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x10 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x10 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x10 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x10 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x10 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x10 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x10 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x10 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x10 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x10 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x10 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x10 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x10 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x10 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x10 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x14 "GPMC_ECC6_RESULT,ECC6 Result Register"
bitfld.long 0x14 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x14 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x14 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x14 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x14 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x14 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x14 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x14 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x14 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x14 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x14 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x14 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x14 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x14 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x14 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x14 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x14 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x14 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x14 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x14 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x14 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x14 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x14 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x14 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x18 "GPMC_ECC7_RESULT,ECC7 Result Register"
bitfld.long 0x18 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x18 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x18 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x18 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x18 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x18 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x18 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x18 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x18 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x18 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x18 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x18 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x18 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x18 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x18 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x18 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x18 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x18 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x18 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x18 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x18 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x18 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x18 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x18 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x1C "GPMC_ECC8_RESULT,ECC8 Result Register"
bitfld.long 0x1C 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x1C 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x1C 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x1C 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x1C 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x1C 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x1C 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x1C 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x1C 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x1C 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x1C 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x1C 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x1C 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x1C 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x1C 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x1C 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x1C 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x1C 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x1C 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x1C 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x1C 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x1C 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x1C 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x1C 0. " P1E ,Even Column Parity bit 1" "0,1"
line.long 0x20 "GPMC_ECC9_RESULT,ECC9 Result Register"
bitfld.long 0x20 27. " P2048O ,Odd Row Parity bit 2048" "0,1"
bitfld.long 0x20 26. " P1024O ,Odd Row Parity bit 1024" "0,1"
bitfld.long 0x20 25. " P512O ,Odd Row Parity bit 512" "0,1"
bitfld.long 0x20 24. " P256O ,Odd Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x20 23. " P128O ,Odd Row Parity bit 128" "0,1"
bitfld.long 0x20 22. " P64O ,Odd Row Parity bit 64" "0,1"
bitfld.long 0x20 21. " P32O ,Odd Row Parity bit 32" "0,1"
bitfld.long 0x20 20. " P16O ,Odd Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x20 19. " P8O ,Odd Row Parity bit 8" "0,1"
bitfld.long 0x20 18. " P4O ,Odd Column Parity bit 4" "0,1"
bitfld.long 0x20 17. " P2O ,Odd Column Parity bit 2" "0,1"
bitfld.long 0x20 16. " P1O ,Odd Column Parity bit 1" "0,1"
textline " "
bitfld.long 0x20 11. " P2048E ,Even Row Parity bit 2048" "0,1"
bitfld.long 0x20 10. " P1024E ,Even Row Parity bit 1024" "0,1"
bitfld.long 0x20 9. " P512E ,Even Row Parity bit 512" "0,1"
bitfld.long 0x20 8. " P256E ,Even Row Parity bit 256" "0,1"
textline " "
bitfld.long 0x20 7. " P128E ,Even Row Parity bit 128" "0,1"
bitfld.long 0x20 6. " P64E ,Even Row Parity bit 64" "0,1"
bitfld.long 0x20 5. " P32E ,Even Row Parity bit 32" "0,1"
bitfld.long 0x20 4. " P16E ,Even Row Parity bit 16" "0,1"
textline " "
bitfld.long 0x20 3. " P8E ,Even Row Parity bit 8" "0,1"
bitfld.long 0x20 2. " P4E ,Even Column Parity bit 4" "0,1"
bitfld.long 0x20 1. " P2E ,Even Column Parity bit 2" "0,1"
bitfld.long 0x20 0. " P1E ,Even Column Parity bit 1" "0,1"
endif
group.long 0x240++0xF
line.long 0x00 "GPMC_BCH_RESULT0_0,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_0,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_0,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_0,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x240+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_0,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_0,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_0,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_0 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x250++0xF
line.long 0x00 "GPMC_BCH_RESULT0_1,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_1,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_1,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_1,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x250+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_1,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_1,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_1,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_1 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x260++0xF
line.long 0x00 "GPMC_BCH_RESULT0_2,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_2,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_2,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_2,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x260+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_2,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_2,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_2,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_2 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x270++0xF
line.long 0x00 "GPMC_BCH_RESULT0_3,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_3,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_3,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_3,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x270+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_3,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_3,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_3,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_3 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x280++0xF
line.long 0x00 "GPMC_BCH_RESULT0_4,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_4,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_4,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_4,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x280+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_4,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_4,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_4,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_4 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x290++0xF
line.long 0x00 "GPMC_BCH_RESULT0_5,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_5,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_5,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_5,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x290+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_5,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_5,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_5,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_5 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x2A0++0xF
line.long 0x00 "GPMC_BCH_RESULT0_6,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_6,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_6,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_6,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x2A0+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_6,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_6,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_6,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_6 ,BCH ECC result (bits 192 to 207)"
endif
endif
group.long 0x2B0++0xF
line.long 0x00 "GPMC_BCH_RESULT0_7,BCH ECC result (bits 0 to 31)"
line.long 0x04 "GPMC_BCH_RESULT1_7,BCH ECC result (bits 32 to 63)"
line.long 0x08 "GPMC_BCH_RESULT2_7,BCH ECC result (bits 64 to 95)"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 127)"
else
line.long 0x0C "GPMC_BCH_RESULT3_7,BCH ECC result (bits 96 to 103)"
hexmask.long.byte 0x0C 0.--7. 1. " BCH_RESULT_3 ,BCH ECC result (bits 96 to 103)"
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM389*"))||(cpuis("AM335*"))||cpuis("C6A816*")||(cpuis("AM387*"))||(cpuis("DRA6*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long (0x2B0+0xc0)++0xb
line.long 0x00 "GPMC_BCH_RESULT4_7,BCH ECC result (bits 128 to 159)"
line.long 0x04 "GPMC_BCH_RESULT5_7,BCH ECC result (bits 160 to 191)"
line.long 0x08 "GPMC_BCH_RESULT6_7,BCH ECC result (bits 192 to 207)"
sif (!((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))&&!(cpuis("AM387*"))&&!(cpuis("AM335*"))&&(!cpuis("DRA62*")))
hexmask.long.word 0x08 0.--15. 1. " BCH_RESULT_6_7 ,BCH ECC result (bits 192 to 207)"
endif
endif
tree.end
width 0xb
tree.end
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
tree.open "HDMI (High-Definition Multimedia Interface)"
tree "HDMI_WP (HDMI Wrapper Registers)"
base ad:0x46C00000
width 24.
rgroup.long 0x00++0x03
line.long 0x00 "HDMI_WP_REVISION,IP Revision Identifier"
group.long 0x10++0x03
line.long 0x00 "HDMI_WP_SYSCONFIG,Clock management configuration"
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode"
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x24++0x03
line.long 0x00 "HDMI_WP_IRQSTATUS_RAW,Raw Interrupt Status"
bitfld.long 0x00 10. " AUDIO_FIFO_SAMPLE_REQ_INTR ,Settable raw status for audio events" "Not pending,Pending"
bitfld.long 0x00 9. " AUDIO_FIFO_OVERFLOW_INTR ,Settable raw status for audio events" "Not pending,Pending"
textline " "
bitfld.long 0x00 8. " AUDIO_FIFO_UNDERFLOW_INTR ,Settable raw status for audio events" "Not pending,Pending"
bitfld.long 0x00 4. " OCP_TIME_OUT_INTR ,Settable raw status for OCP time Out interrupt" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " CORE_INTR ,Settable raw status for Core interrupt" "Not pending,Pending"
group.long 0x28++0x03
line.long 0x00 "HDMI_WP_IRQSTATUS,Interrupt Status"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AUDIO_FIFO_SAMPLE_REQ_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AUDIO_FIFO_OVERFLOW_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AUDIO_FIFO_UNDERFLOW_INTR_set/clr ,Status for audio events" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " OCP_TIME_OUT_INTR_set/clr ,Status for OCP time Out interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " CORE_INTR_set/clr ,Status for Core interrupt" "No interrupt,Interrupt"
group.long 0x44++0x03
line.long 0x00 "HDMI_WP_DEBOUNCE,glitch filter on Line 5Vshort and Rxdet"
hexmask.long.byte 0x00 8.--13. 1. " RXDET ,Glitch filter for RXDET input"
hexmask.long.byte 0x00 0.--5. 1. " LINE5VSHORT ,Glitch filter for line 5v short input"
group.long 0x50++0x03
line.long 0x00 "HDMI_WP_VIDEO_CFG,Configuration of HDMI Wrapper video"
bitfld.long 0x00 8.--10. " PACKING_MODE ,Packing mode" "10bits,24bits,20bitsYUV422,Reserved,Reserved,Reserved,Reserved,NoPack"
bitfld.long 0x00 5. " CORE_VSYNC_INV ,VSYNC signal provided to the HDMI core invert" "Not inverted,Inverted"
textline " "
bitfld.long 0x00 4. " CORE_HSYNC_INV ,HSYNC signal provided to the HDMI core invert" "Not inverted,Inverted"
bitfld.long 0x00 0.--1. " MODE ,Mode" "0,?..."
group.long 0x70++0x03
line.long 0x00 "HDMI_WP_CLK,Configuration of clocks"
bitfld.long 0x00 16. " OCP_TIME_OUT_DIS ,Time out in case CEC_DDC_CLK not provided" "No timeout,Timeout"
hexmask.long.byte 0x00 0.--5. 1. " CEC_DIV ,CEC clock divisor"
if ((d.l(ad:(0x46C00000+0x80))&0x10)==0x0)
group.long 0x80++0x03
line.long 0x00 "HDMI_WP_AUDIO_CFG,Audio Configuration in FIFO"
bitfld.long 0x00 24.--26. " STEREO_CHANNEL_ENABLE ,Number of stereo channels enabled in the HDMI_CORE module" "No channel,1 channel,2 channels,3 channels,4 channels,?..."
hexmask.long.byte 0x00 16.--23. 1. " AUDIO_CHANNEL_LOCATION ,Active channels"
textline " "
bitfld.long 0x00 5. " BLOCK_START_END_DISABLE ,Block end start generation disable" "No,Yes"
bitfld.long 0x00 4. " IEC ,Indicate if the format of the FIFO is compliant with the IEC format" "L-PCM,IEC 60958/61937"
textline " "
bitfld.long 0x00 3. " JUSTIFY ,Justification" "Justify left,Justify right"
bitfld.long 0x00 1. " SAMPLE_NBR ,Number of sample per word (32bits)" "1 sample,2 samples"
textline " "
bitfld.long 0x00 0. " SAMPLE_SIZE ,Audio sample size" "16 bits,24 bits"
else
group.long 0x80++0x03
line.long 0x00 "HDMI_WP_AUDIO_CFG,Audio Configuration in FIFO"
bitfld.long 0x00 24.--26. " STEREO_CHANNEL_ENABLE ,Number of stereo channels enabled in the HDMI_CORE module" "No channel,1 channel,2 channels,3 channels,4 channels,?..."
hexmask.long.byte 0x00 16.--23. 1. " AUDIO_CHANNEL_LOCATION ,Active channels"
textline " "
bitfld.long 0x00 5. " BLOCK_START_END_DISABLE ,Block end start generation disable" "Enabled,Disabled"
bitfld.long 0x00 4. " IEC ,Indicate if the format of the FIFO is compliant with the IEC format" "L-PCM,IEC 60958/61937"
endif
group.long 0x84++0x07
line.long 0x00 "HDMI_WP_AUDIO_CFG2,Audio configuration of DMA"
hexmask.long.byte 0x00 8.--15. 1. " DMA_TRANSFER ,Control the dma request"
hexmask.long.byte 0x00 0.--7. 1. " BLOCK_SIZE ,Define the block size if audio sample are compressed"
line.long 0x04 "HDMI_WP_AUDIO_CTRL,Audio FIFO control"
bitfld.long 0x04 31. " WRAPPER_ENABLE ,Enable the audio wrapper" "Disabled,Enabled"
bitfld.long 0x04 30. " CORE_REQ_ENABLE ,Enables the Audio data request generated by the core" "Disabled,Enabled"
textline " "
hexmask.long.word 0x04 16.--25. 1. " NUMBER_OF_SAMPLE ,Number of valid sample (16 or 24 bits) in the FIFO (depends of the fifo format setting)"
bitfld.long 0x04 9. " DMA_OR_IRQ ,Indicated if the threshold generates a DMA or an IRQ" "DMA,IRQ"
textline " "
hexmask.long.word 0x04 0.--8. 1. " TRESHOLD_VALUE ,Treshold value"
wgroup.long 0x8C++0x03
line.long 0x00 "HDMI_WP_AUDIO_DATA,TX Data of FIFO"
width 0xb
tree.end
tree "HDMI_IP_CORE_SYSTEM (HDMI Core System Registers)"
base ad:0x46C00400
width 24.
rgroup.long 0x000++0x13
line.long 0x00 "VND_IDL,Vendor ID Register"
hexmask.long.byte 0x00 0.--7. 1. " VND_ID ,Provides unique vendor identification through I2C. Vendor ID Low Byte"
line.long 0x04 "VND_IDH,Vendor ID Register"
hexmask.long.byte 0x04 0.--7. 1. " VND_ID ,Provides unique vendor identification through I2C. Vendor ID High Byte"
line.long 0x08 "DEV_IDL,Device ID Register"
hexmask.long.byte 0x08 0.--7. 1. " DEV_ID ,Provides unique device type identification through I2C. Device ID Low Byte"
line.long 0x0C "DEV_IDH,Device ID Register"
hexmask.long.byte 0x0C 0.--7. 1. " DEV_ID ,Provides unique device type identification through I2C. Device ID High Byte"
line.long 0x10 "DEV_REV,Device Revision Register"
hexmask.long.byte 0x10 0.--7. 1. " DEV_REV ,Allows distinction between revisions of same device."
group.long 0x014++0x03
line.long 0x00 "SRST,Software Reset Register"
bitfld.long 0x00 1. " FIFORST ,Audio FIFO reset" "No reset,Reset"
bitfld.long 0x00 0. " SWRST ,Software reset" "No reset,Reset"
group.long 0x020++0x0B
line.long 0x00 "SYS_CTRL1,System Control Register 1"
bitfld.long 0x00 6. " VSYNC ,The current status of the VSYNC input pin" "Low,High"
bitfld.long 0x00 5. " VEN ,VSYNC enable" "Fixed LOW,Follow VSYNC"
textline " "
bitfld.long 0x00 4. " HEN ,HSYNC enable" "Fixed LOW,Follow HSYNC"
bitfld.long 0x00 2. " BSEL ,Input Bus Select" "12bit,24bit"
textline " "
bitfld.long 0x00 1. " EDGE ,Edge select" "Falling edge,Rising edge"
bitfld.long 0x00 0. " PD ,Power down mode: HIGH is normal operation" "Low,High"
line.long 0x04 "SYS_STAT,System Status Register"
bitfld.long 0x04 2. " RSEN ,Receiver Sense" "Not connected,Connected"
bitfld.long 0x04 1. " HPD ,Hot Plug Detect" "Low,High"
textline " "
bitfld.long 0x04 0. " P_STABLE ,IDCK (io_pclkpin) to TMDS clock (v_ck2x) is stable and the Transmitter can send reliable data on the TMDS link" "Low,High"
line.long 0x08 "SYS_CTRL3,Legacy Registers"
bitfld.long 0x08 1.--2. " CTL ,The states of these control bits are transmitted across the TMDS link during blanking times for DVI 1.0 mode only" "0,1,2,3"
group.long 0x034++0x03
line.long 0x00 "DCTL,Data Control Register"
bitfld.long 0x00 2. " VID_BLANK ,Video output blank enable" "Disabled,Enabled"
bitfld.long 0x00 1. " AUD_MUTE ,Send zeroes in audio pocket enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " HDCP_SEL ,Value of the pin io_hdcp_sel" "Unencrypted,Only encrypted"
group.long 0x03C++0x03
line.long 0x00 "HDCP_CTRL,HDCP Control Register"
bitfld.long 0x00 6. " ENC_ON ,Encryption status" "Disabled,Enabled"
bitfld.long 0x00 5. " BKSV_ERR ,BKSV error" "No error,Error"
textline " "
bitfld.long 0x00 4. " RX_RPTR ,Repeater" "Single HDMI,HDMI Receiver"
bitfld.long 0x00 3. " TX_ANSTOP ,AN control" "Not stopped,Stopped"
textline " "
bitfld.long 0x00 2. " CP_RESTN ,Content protection reset" "Reset,No reset"
bitfld.long 0x00 1. " RI_RDY ,Ri Ready" "Not ready,Ready"
textline " "
bitfld.long 0x00 0. " ENC_EN ,Encryption enabled" "Disabled,Enabled"
tree "BKSV"
group.long 0x040++0x13
line.long 0x0 "BKSV_0,HDCP BKSV Register 0"
hexmask.long.byte 0x0 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
line.long 0x4 "BKSV_1,HDCP BKSV Register 1"
hexmask.long.byte 0x4 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
line.long 0x8 "BKSV_2,HDCP BKSV Register 2"
hexmask.long.byte 0x8 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
line.long 0xC "BKSV_3,HDCP BKSV Register 3"
hexmask.long.byte 0xC 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
line.long 0x10 "BKSV_4,HDCP BKSV Register 4"
hexmask.long.byte 0x10 0.--7. 1. " BKSV ,HDCP Receiver Key Selection Vector register value"
tree.end
tree "AN"
group.long 0x054++0x1F
line.long 0x0 "AN_0,HDCP AN Register 0"
hexmask.long.byte 0x0 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x4 "AN_1,HDCP AN Register 1"
hexmask.long.byte 0x4 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x8 "AN_2,HDCP AN Register 2"
hexmask.long.byte 0x8 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0xC "AN_3,HDCP AN Register 3"
hexmask.long.byte 0xC 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x10 "AN_4,HDCP AN Register 4"
hexmask.long.byte 0x10 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x14 "AN_5,HDCP AN Register 5"
hexmask.long.byte 0x14 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x18 "AN_6,HDCP AN Register 6"
hexmask.long.byte 0x18 0.--7. 1. " AN ,HDCP pseudo-random value"
line.long 0x1C "AN_7,HDCP AN Register 7"
hexmask.long.byte 0x1C 0.--7. 1. " AN ,HDCP pseudo-random value"
tree.end
tree "AKSV"
rgroup.long 0x074++0x13
line.long 0x0 "AKSV_0,HDCP AKSV Register 0"
hexmask.long.byte 0x0 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
line.long 0x4 "AKSV_1,HDCP AKSV Register 1"
hexmask.long.byte 0x4 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
line.long 0x8 "AKSV_2,HDCP AKSV Register 2"
hexmask.long.byte 0x8 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
line.long 0xC "AKSV_3,HDCP AKSV Register 3"
hexmask.long.byte 0xC 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
line.long 0x10 "AKSV_4,HDCP AKSV Register 4"
hexmask.long.byte 0x10 0.--7. 1. " AKSV ,HDCP-capable Transmitter s Key Selection Vector"
tree.end
rgroup.long 0x088++0x13
line.long 0x00 "RI1,HDCP Ri Register"
hexmask.long.byte 0x00 0.--7. 1. " RI ,Ri Register"
line.long 0x04 "RI2,HDCP Ri Register"
hexmask.long.byte 0x04 0.--7. 1. " RI ,Ri Register"
line.long 0x08 "RI_128_COMP,HDCP Ri 128 Compare Register"
hexmask.long.byte 0x08 0.--6. 1. " RI_128_COMP ,Limit counter for Ri comparison"
line.long 0x0C "I_CNT,HDCP I Counter Register"
hexmask.long.byte 0x0C 0.--6. 1. " I_CNT ,Current value of I counter"
line.long 0x10 "RI_STAT,Ri Status Register"
bitfld.long 0x10 0. " RI_STARTED ,Ri check started status" "Low,High"
group.long 0x09C++0x07
line.long 0x00 "RI_CMD,Ri Command Register"
bitfld.long 0x00 1. " BCAP_EN ,Enable polling of the BCAP_DONE bit" "Disable,Enable"
bitfld.long 0x00 0. " RI_EN ,Enable Ri check" "Disable,Enable"
line.long 0x04 "RI_START,Ri Line Start Register"
hexmask.long.byte 0x04 0.--7. 1. " RI_LINE_START ,Ri Check start line"
rgroup.long 0x0A4++0x07
line.long 0x00 "RI_RX_L,Ri From RX Registers"
hexmask.long.byte 0x00 0.--7. 1. " RI_RX ,HDMI Receiver s Ri value if any of the Ri Check errors occurred"
line.long 0x04 "RI_RX_H,Ri From RX Registers"
hexmask.long.byte 0x04 0.--7. 1. " RI_RX ,HDMI Receiver s Ri value if any of the Ri Check errors occurred"
group.long 0x0AC++0x03
line.long 0x00 "RI_DEBUG,Ri Debug Registers"
bitfld.long 0x00 7. " RI_DBG_TRASH ,Force a corruption of the Ri values" "Continue,Force"
bitfld.long 0x00 6. " RI_DBG_HOLD ,Hold the Ri value steady" "Continue,Hold"
group.long 0x0C8++0x0B
line.long 0x00 "DE_DLY,Video DE Delay Register"
hexmask.long.byte 0x00 0.--7. 1. " DE_DLY ,Width of the area to the left of the active display"
line.long 0x04 "DE_CTRL,Video DE Control Register"
bitfld.long 0x04 6. " DE_GEN ,Generate DE signal" "Disable,Enable"
bitfld.long 0x04 5. " VS_POL ,VSYNC polarity" "Positive,Negative"
textline " "
bitfld.long 0x04 4. " HS_POL ,HSYNC polarity" "Positive,Negative"
bitfld.long 0x04 0.--3. " DE_DLY ,The bit-field defines DE_DLY[11:8]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DE_TOP,Video DE Top Register"
hexmask.long.byte 0x08 0.--7. 1. " DE_TOP ,Defines the height of the area above the active display"
group.long 0x0D8++0x0F
line.long 0x00 "DE_CNTL,Video DE Count Register"
hexmask.long.byte 0x00 0.--7. 1. " DE_CNT ,Defines the width of the active display"
line.long 0x04 "DE_CNTH,Video DE Count Register"
bitfld.long 0x04 0.--3. " DE_CNT ,Defines the width of the active display" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DE_LINL,Video DE Line Register"
hexmask.long.byte 0x08 0.--7. 1. " DE_LIN ,Defines the height of the active display"
line.long 0x0C "DE_LINH,Video DE Line Register"
bitfld.long 0x0C 0.--2. " DE_LIN ,Defines the height of the active display" "0,1,2,3,4,5,6,7"
rgroup.long 0x0E8++0x0F
line.long 0x00 "HRES_L,Video H Resolution Register"
hexmask.long.byte 0x00 0.--7. 1. " H_RES ,Measures the time between two HSYNC active edges. The unit of measure is pixels"
line.long 0x04 "HRES_H,Video H Resolution Register"
bitfld.long 0x04 0.--4. " H_RES ,Measures the time between two HSYNC active edges" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "VRES_L,Video V Refresh Register"
hexmask.long.byte 0x08 0.--7. 1. " V_RES ,Measures the time between two VSYNC active edges"
line.long 0x0C "VRES_H,Video V Refresh Register"
bitfld.long 0x0C 0.--2. " V_RES ,Measures the time between two VSYNC active edges" "0,1,2,3,4,5,6,7"
group.long 0x0F8++0x07
line.long 0x00 "IADJUST,Video Interlace Adjustment Register"
bitfld.long 0x00 2. " DE_ADJ ,VSYNC disable" "Enabled,Disabled"
bitfld.long 0x00 1. " F2VADJ ,Field 2 adjust enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " F2VOFST ,Field 2 offset" "Low,High"
line.long 0x04 "POL_DETECT,Video SYNC Polarity Detection Register"
bitfld.long 0x04 2. " I_DET ,Interlace detect" "Progressive,Interlace"
bitfld.long 0x04 1. " VPOL_DET ,Detected input VSYNC polarity using internal circuit" "Active high,Active low"
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bitfld.long 0x04 0. " HPOL_DET ,Detected input HSYNC polarity using internal circuit" "Active high,Active low"
group.long 0x100++0x1F
line.long 0x00 "HBIT_2HSYNC1,Video Hbit to HSYNC Register"
hexmask.long.byte 0x00 0.--7. 1. " HBIT_TO_HSYNC ,Creates HSYNC pulses"
line.long 0x04 "HBIT_2HSYNC2,Video Hbit to HSYNC Register"
hexmask.long.byte 0x04 0.--7. 1. " HBIT_TO_HSYNC ,Creates HSYNC pulses"
line.long 0x08 "FLD2_HS_OFSTL,Video Field2 HSYNC Offset Register"
hexmask.long.byte 0x08 0.--7. 1. " FIELD2_OFST ,Determines VSYNC pixel offset for the odd field of an interlaced source"
line.long 0x0C "FLD2_HS_OFSTH,Video Field2 HSYNC Offset Register"
bitfld.long 0x0C 0.--3. " FIELD2_OFST ,Determines VSYNC pixel offset for the odd field of an interlaced source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "HWIDTH1,Video HSYNC Length Register"
hexmask.long.byte 0x10 0.--7. 1. " HWIDTH ,Sets the width of the HSYNC pulses"
line.long 0x14 "HWIDTH2,Video HSYNC Length Register"
bitfld.long 0x14 0.--1. " HWIDTH ,Sets the width of the HSYNC pulses" "0,1,2,3"
line.long 0x18 "VBIT_TO_VSYNC,Video Vbit to VSYNC Register"
hexmask.long.byte 0x18 0.--5. 1. " VBIT_TO_VSYNC ,VBIT to VSYNC delay"
line.long 0x1C "VWIDTH,Video VSYNC Length Register"
hexmask.long.byte 0x1C 0.--5. 1. " VWIDTH ,Sets the width of VSYNC pulse"
group.long 0x120++0x23
line.long 0x00 "VID_CTRL,Video Control Register"
bitfld.long 0x00 7. " IFPOL ,Invert field polarity" "Not inverted,Inverted"
bitfld.long 0x00 5. " EXTN ,Extended Bit mode" "8bit,12bit"
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bitfld.long 0x00 4. " CSCSEL ,Color Space Conversion Standard select" "BT.601,BT.709"
bitfld.long 0x00 0.--1. " ICLK ,Clock mode" "Not replicated,Replicated 1 time,Reserved,Replicated 4 times"
line.long 0x04 "VID_ACEN,Video Action Enable Register"
bitfld.long 0x04 6.--7. " WIDE_BUS ,Identifies the number of bits per input video channel" "8bits_24bits,10bits_30bits,12bits_36bits,?..."
bitfld.long 0x04 4. " CLIP_CS_ID ,Identifies the output color space on the link" "RGBOutput,YCbCrOutput"
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bitfld.long 0x04 3. " RANGE_CLIP ,Enable Range Clip from 16 to 235 (RGB and Y)/240 (CbCr)" "Disabled,Enabled"
bitfld.long 0x04 2. " RGB_2_YCBCR ,Enable RGB to YCbCr color-space converter" "Disabled,Enabled"
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bitfld.long 0x04 1. " RANGE_CMPS ,Enable Range Compress 0-255 to 16-234" "Disabled,Enabled"
bitfld.long 0x04 0. " DOWN_SMPL ,Enable down sampler 4:4:4 to 4:2:2" "Disabled,Enabled"
line.long 0x08 "VID_MODE,Video Mode1 Register"
bitfld.long 0x08 6.--7. " DITHER_MODE ,Identifies the number of bits per output video channel" "8bits,10bits,12bits,?..."
bitfld.long 0x08 5. " DITHER ,Dither enable," "Disabled,Enabled"
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bitfld.long 0x08 4. " RANGE ,Data Range 16-to-235 to 0-to-255 expansion" "Disabled,Enabled"
bitfld.long 0x08 3. " CSC ,YcbCr to RGB Color Space Conversion" "Disabled,Enabled"
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bitfld.long 0x08 2. " UPSMP ,Upsampling 4:2:2 to 4:4:4" "Disabled,Enabled"
bitfld.long 0x08 1. " DEMUX ,One- to Two-Data-Channel Demux" "Disabled,Enabled"
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bitfld.long 0x08 0. " SYNCEX ,Embedded Sync Extraction" "Disabled,Enabled"
line.long 0x0C "VID_BLANK1,Video Blanking Registers"
hexmask.long.byte 0x0C 0.--7. 1. " VID_BLANK1 ,Defines the video blanking value for Channel 1 (Blue)"
line.long 0x10 "VID_BLANK2,Video Blanking Registers"
hexmask.long.byte 0x10 0.--7. 1. " VID_BLANK2 ,Defines the video blanking value for Channel 2 (Green)"
line.long 0x14 "VID_BLANK3,Video Blanking Registers"
hexmask.long.byte 0x14 0.--7. 1. " VID_BLANK3 ,Defines the video blanking value for Channel 3 (Red)"
line.long 0x18 "DC_HEADER,Deep Color Header Register"
hexmask.long.byte 0x18 0.--7. 1. " DC_HEADER ,Least siginificant byte of the deep color header that sends the TMDS dynamic phase once per frame"
line.long 0x1C "VID_DITHER,Video Mode2 Register"
bitfld.long 0x1C 6. " M_D2 ,Dither + round option" "Disabled,Enabled"
bitfld.long 0x1C 5. " UP2 ,Dither + 2 b10 option" "Disabled,Enabled"
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bitfld.long 0x1C 4. " STR_422_EN ,Enable Mode 4:2:2 for Dithering and Clipping" "Disable,Enable"
bitfld.long 0x1C 3. " D_BC_EN ,Enable adding random number on Blue channel data" "Disable,Enable"
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bitfld.long 0x1C 2. " D_GC_EN ,Enable adding random number on Green channel data" "Disable,Enable"
bitfld.long 0x1C 1. " D_RC_EN ,Enable adding random number on Red channel data" "Disable,Enable"
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bitfld.long 0x1C 0. " DRD ,Dither round" "Disable,Enable"
line.long 0x20 "RGB2XVYCC_CT,RGB_2_xvYCC control Register"
bitfld.long 0x20 2. " XV_CO_OV ,Override internal CSC coefficients with register 51 to XX values" "Disabled,Enabled"
bitfld.long 0x20 1. " XV_FUS ,xvYCC Fullscale mode" "Disabled,Enabled"
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bitfld.long 0x20 0. " XV_EN ,xvYCC Enable" "Disabled,Enabled"
group.long 0x144++0x07
line.long 0x00 "R2Y_COEFF_LOW,RGB_2_xvYCC Conversion R to Y Register"
hexmask.long.byte 0x00 0.--7. 1. " R2YCOEFF_L ,RGB to xvYCC conversion R to Y coefficient lower byte"
line.long 0x04 "R2Y_COEFF_UP,RGB_2_xvYCC Conversion R to Y Register"
hexmask.long.byte 0x04 0.--7. 1. " R2YCOEFF_H ,RGB to xvYCC conversion R to Y coefficient upper byte"
group.long 0x14C++0x07
line.long 0x00 "G2Y_COEFF_LOW,RGB_2_xvYCC Conversion G to Y Register"
hexmask.long.byte 0x00 0.--7. 1. " G2YCOEFF_L ,RGB to xvYCC conversion G to Y coefficient lower byte"
line.long 0x04 "G2Y_COEFF_UP,RGB_2_xvYCC Conversion G to Y Register"
hexmask.long.byte 0x04 0.--7. 1. " G2YCOEFF_H ,RGB to xvYCC conversion G to Y coefficient upper byte"
group.long 0x154++0x07
line.long 0x00 "B2Y_COEFF_LOW,RGB_2_xvYCC Conversion B to Y Register"
hexmask.long.byte 0x00 0.--7. 1. " B2YCOEFF_L ,RGB to xvYCC conversion B to Y coefficient lower byte"
line.long 0x04 "B2Y_COEFF_UP,RGB_2_xvYCC Conversion B to Y Register"
hexmask.long.byte 0x04 0.--7. 1. " B2YCOEFF_H ,RGB to xvYCC conversion B to Y coefficient upper byte"
group.long 0x15C++0x07
line.long 0x00 "R2CB_COEFF_LOW,RGB_2_xvYCC Conversion R to Cb Register"
hexmask.long.byte 0x00 0.--7. 1. " R2CBCOEFF_L ,RGB to xvYCC conversion R to Cb coefficient lower byte"
line.long 0x04 "R2CB_COEFF_UP,RGB_2_xvYCC Conversion R to Cb Register"
hexmask.long.byte 0x04 0.--7. 1. " R2CBCOEFF_H ,RGB to xvYCC conversion R to Cb coefficient upper byte"
group.long 0x164++0x07
line.long 0x00 "G2CB_COEFF_LOW,RGB_2_xvYCC Conversion G to Cb Register"
hexmask.long.byte 0x00 0.--7. 1. " G2CBCOEFF_L ,RGB to xvYCC conversion G to Cb coefficient lower byte"
line.long 0x04 "G2CB_COEFF_UP,RGB_2_xvYCC Conversion G to Cb Register"
hexmask.long.byte 0x04 0.--7. 1. " G2CBCOEFF_H ,RGB to xvYCC conversion G to Cb coefficient upper byte"
group.long 0x16C++0x07
line.long 0x00 "B2CB_COEFF_LOW,RGB_2_xvYCC Conversion B to Cb Register"
hexmask.long.byte 0x00 0.--7. 1. " B2CBCOEFF_L ,RGB to xvYCC conversion B to Cb coefficient lower byte"
line.long 0x04 "B2CB_COEFF_UP,RGB_2_xvYCC Conversion B to Cb Register"
hexmask.long.byte 0x04 0.--7. 1. " B2CBCOEFF_H ,RGB to xvYCC conversion B to Cb coefficient upper byte"
group.long 0x174++0x07
line.long 0x00 "R2CR_COEFF_LOW,RGB_2_xvYCC Conversion R to Cr Register"
hexmask.long.byte 0x00 0.--7. 1. " R2CRCOEFF_L ,RGB to xvYCC conversion R to Cr coefficient lower byte"
line.long 0x04 "R2CR_COEFF_UP,RGB_2_xvYCC Conversion R to Cr Register"
hexmask.long.byte 0x04 0.--7. 1. " R2CRCOEFF_H ,RGB to xvYCC conversion R to Cr coefficient upper byte"
group.long 0x17C++0x07
line.long 0x00 "G2CR_COEFF_LOW,RGB_2_xvYCC Conversion G to Cr Register"
hexmask.long.byte 0x00 0.--7. 1. " G2CRCOEFF_L ,RGB to xvYCC conversion G to Cr coefficient lower byte"
line.long 0x04 "G2CR_COEFF_UP,RGB_2_xvYCC Conversion G to Cr Register"
hexmask.long.byte 0x04 0.--7. 1. " G2CRCOEFF_H ,RGB to xvYCC conversion G to Cr coefficient upper byte"
group.long 0x184++0x07
line.long 0x00 "B2CR_COEFF_LOW,RGB_2_xvYCC Conversion B to Cr Register"
hexmask.long.byte 0x00 0.--7. 1. " B2CRCOEFF_L ,RGB to xvYCC conversion B to Cr coefficient lower byte"
line.long 0x04 "B2CR_COEFF_UP,RGB_2_xvYCC Conversion B to Cr Register"
hexmask.long.byte 0x04 0.--7. 1. " B2CRCOEFF_H ,RGB to xvYCC conversion B to Cr coefficient upper byte"
group.long 0x18C++0x17
line.long 0x00 "RGB_OFFSET_LOW,RGB_2_xvYCC RGB Input Offset Register"
hexmask.long.byte 0x00 0.--7. 1. " RGB_OFFS_L ,Input RGB offset value lower byte"
line.long 0x04 "RGB_OFFSET_UP,RGB_2_xvYCC RGB Input Offset Register"
hexmask.long.byte 0x04 0.--7. 1. " RGB_OFFS_H ,Input RGB offset value upper byte"
line.long 0x08 "Y_OFFSET_LOW,RGB_2_xvYCC Conversion Y Output Offset Register"
hexmask.long.byte 0x08 0.--6. 1. " Y_OFFS_L ,Output Y offset value lower 7 bits"
line.long 0x0C "Y_OFFSET_UP,RGB_2_xvYCC Conversion Y Output Offset Register"
hexmask.long.byte 0x0C 0.--6. 1. " Y_OFFS_H ,Output Y offset value upper 7 bits"
line.long 0x10 "CBCR_OFFSET_LOW,RGB_2_xvYCC Conversion CbCr Output Offset Register"
hexmask.long.byte 0x10 0.--6. 1. " CBCR_OFFS_L ,Output CbCr offset value lower 7 bits"
line.long 0x14 "CBCR_OFFSET_UP,RGB_2_xvYCC Conversion CbCr Output Offset Register"
hexmask.long.byte 0x14 0.--6. 1. " CBCR_OFFS_H ,Output CbCr offset value upper 7 bits"
rgroup.long 0x1C0++0x03
line.long 0x00 "INTR_STATE,Interrupt State Register"
bitfld.long 0x00 0. " INTR ,Interrupt State" "No intrrupt,Interrupt"
rgroup.long 0x1C4++0x0B
line.long 0x00 "INTR1,Interrupt Source Register"
bitfld.long 0x00 7. " SOFT ,Software Induced Interrupt" "No interrupt,Interrupt"
bitfld.long 0x00 6. " HPD ,Monitor Detect Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " RSEN ,Receiver Sense Interrupt asserted if RSEN has changed" "No interrupt,Interrupt"
bitfld.long 0x00 4. " DROP_SAMPLE ,New preamble forced to drop sample (S/PDIF input only)" "No interrupt,Interrupt"
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bitfld.long 0x00 3. " BIP_HASE_ERR ,Input S/PDIF stream has bi-phase error" "No interrupt,Interrupt"
bitfld.long 0x00 2. " RI_128 ,Input counted past frame count threshold set in RI_128_COMP register" "No interrupt,Interrupt"
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bitfld.long 0x00 1. " OVER_RUN ,Audio FIFO Overflow" "No interrupt,Interrupt"
bitfld.long 0x00 0. " UNDER_RUN ,Audio FIFO Underflow" "No interrupt,Interrupt"
line.long 0x04 "INTR2,Interrupt Source Register"
bitfld.long 0x04 7. " BCAP_DONE ,FIFORDY bit (0x74:0x40[5]) is set to 1" "No interrupt,Interrupt"
bitfld.long 0x04 6. " SPDIF_PAR ,S/PDIF Parity Error" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " ENC_DIS ,The ENC_EN bit (in register HDCP_CTRL) changed from 1 to 0" "No interrupt,Interrupt"
bitfld.long 0x04 4. " PREAM_ERR ,This condition is the opposite of the condition that causes DROP_SAMPLE (in register INTR1)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " CTS_CHG ,Change in ACR CTS Value" "No interrupt,Interrupt"
bitfld.long 0x04 2. " ACR_OVR ,ACR Packet Overwrite" "No interrupt,Interrupt"
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bitfld.long 0x04 1. " TCLK_STBL ,TCLK_STABLE (register SYS_STA.P_STABLE) changes state" "No interrupt,Interrupt"
bitfld.long 0x04 0. " VSYNC_REC ,Asserted when VSYNC active edge is recognized" "No interrupt,Interrupt"
line.long 0x08 "INTR3,Interrupt Source Register"
bitfld.long 0x08 7. " RI_ERR_3 ,Ri and Ri do not match during frame 127 (ICNT .1)" "No interrupt,Interrupt"
bitfld.long 0x08 6. " RI_ERR_2 ,Ri and Ri do not match during frame 0 (ICNT)" "No interrupt,Interrupt"
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bitfld.long 0x08 5. " RI_ERR_1 ,Ri did not change between frame 127 and 0" "No interrupt,Interrupt"
bitfld.long 0x08 4. " RI_ERR_0 ,Ri not read within one frame" "No interrupt,Interrupt"
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bitfld.long 0x08 3. " DDC_CMD_DONE ,DDC command is complete" "No interrupt,Interrupt"
bitfld.long 0x08 2. " DDC_FIFO_HALF ,DDC FIFO is half full" "No interrupt,Interrupt"
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bitfld.long 0x08 1. " DDC_FIFO_FULL ,DDC FIFO is full" "No interrupt,Interrupt"
bitfld.long 0x08 0. " DDC_FIFO_EMPTY ,DDC FIFO is empty" "No interrupt,Interrupt"
group.long 0x1D0++0x0B
line.long 0x00 "INTR4,Interrupt Source Register"
eventfld.long 0x00 3. " REG_INTR4_STAT3 ,CEC interrupt" "No interrupt,Interrupt"
eventfld.long 0x00 2. " REG_INTR4_STAT2 ,Interrupt bit" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " REG_INTR4_STAT1 ,Interrupt bit" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DSD_INVALID ,DSD stream got invalid sequence" "No interrupt,Interrupt"
line.long 0x04 "INT_UNMASK1,Interrupt Unmask Register"
bitfld.long 0x04 7. " SOFT ,Software Induced Interrupt" "No interrupt,Interrupt"
bitfld.long 0x04 6. " HPD ,Monitor Detect Interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " RSEN ,Receiver Sense Interrupt asserted if RSEN has changed" "No interrupt,Interrupt"
bitfld.long 0x04 4. " DROP_SAMPLE ,New preamble forced to drop sample (S/PDIF input only)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " BIP_HASE_ERR ,Input S/PDIF stream has bi-phase error" "No interrupt,Interrupt"
bitfld.long 0x04 2. " RI_128 ,Input counted past frame count threshold set in RI_128_COMP register" "No interrupt,Interrupt"
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bitfld.long 0x04 1. " OVER_RUN ,Audio FIFO Overflow" "No interrupt,Interrupt"
bitfld.long 0x04 0. " UNDER_RUN ,Audio FIFO Underflow" "No interrupt,Interrupt"
line.long 0x08 "INT_UNMASK2,Interrupt Unmask Register"
bitfld.long 0x08 7. " BCAP_DONE ,FIFORDY bit (0x74:0x40[5]) is set to 1" "No interrupt,Interrupt"
bitfld.long 0x08 6. " SPDIF_PAR ,S/PDIF Parity Error" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 5. " ENC_DIS ,The ENC_EN bit (in register HDCP_CTRL) changed from 1 to 0" "No interrupt,Interrupt"
bitfld.long 0x08 4. " PREAM_ERR ,This condition is the opposite of the condition that causes DROP_SAMPLE (in register INTR1)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 3. " CTS_CHG ,Change in ACR CTS Value" "No interrupt,Interrupt"
bitfld.long 0x08 2. " ACR_OVR ,ACR Packet Overwrite" "No interrupt,Interrupt"
textline " "
bitfld.long 0x08 1. " TCLK_STBL ,TCLK_STABLE (register SYS_STA.P_STABLE) changes state" "No interrupt,Interrupt"
bitfld.long 0x08 0. " VSYNC_REC ,Asserted when VSYNC active edge is recognized" "No interrupt,Interrupt"
rgroup.long 0x1DC++0x03
line.long 0x00 "INT_UNMASK3,Interrupt Unmask Register"
bitfld.long 0x00 7. " RI_ERR_3 ,Ri and Ri do not match during frame 127 (ICNT .1)" "No interrupt,Interrupt"
bitfld.long 0x00 6. " RI_ERR_2 ,Ri and Ri do not match during frame 0 (ICNT)" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " RI_ERR_1 ,Ri did not change between frame 127 and 0" "No interrupt,Interrupt"
bitfld.long 0x00 4. " RI_ERR_0 ,Ri not read within one frame" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " DDC_CMD_DONE ,DDC command is complete" "No interrupt,Interrupt"
bitfld.long 0x00 2. " DDC_FIFO_HALF ,DDC FIFO is half full" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " DDC_FIFO_FULL ,DDC FIFO is full" "No interrupt,Interrupt"
bitfld.long 0x00 0. " DDC_FIFO_EMPTY ,DDC FIFO is empty" "No interrupt,Interrupt"
group.long 0x1E0++0x07
line.long 0x00 "INT_UNMASK4,Interrupt Unmask Register"
eventfld.long 0x00 3. " REG_INTR4_STAT3 ,CEC interrupt" "No interrupt,Interrupt"
eventfld.long 0x00 2. " REG_INTR4_STAT2 ,Interrupt bit" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " REG_INTR4_STAT1 ,Interrupt bit" "No interrupt,Interrupt"
eventfld.long 0x00 0. " DSD_INVALID ,DSD stream got invalid sequence" "No interrupt,Interrupt"
line.long 0x04 "INT_CTRL,Interrupt Control Register"
bitfld.long 0x04 3. " SOFT_INTR ,Set software interrupt" "Clear,Set"
bitfld.long 0x04 2. " OPEN_DRAIN ,INT pin output type" "Push/Pull,Open Drain pin"
textline " "
bitfld.long 0x04 1. " POLARITY ,INT pin assertion level" "Assert HIGH,Assert LOW"
group.long 0x240++0x03
line.long 0x00 "XVYCC2RGB_CTL,xvYCC_2_RGB Control Register"
bitfld.long 0x00 4. " EXP_ONLY ,CSC bypass" "Not bypassed,Bypassed"
bitfld.long 0x00 3. " BYP_ALL ,All functions bypass" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x00 2. " SW_OVR ,Software Over Ride" "Disabled,Enabled"
bitfld.long 0x00 1. " FULLRANGE ,xvYCC full-range expansion enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " XVYCCSEL ,Source select" "YcbCr,xvYCC"
group.long 0x244++0x07
line.long 0x00 "Y2R_COEFF_LOW,RGB_2_xvYCC Conversion Y to R Register"
hexmask.long.byte 0x00 0.--7. 1. " Y2RCOEFF_L ,xvYCC to RGB conversion Y to R coefficient lower byte"
line.long 0x04 "Y2R_COEFF_UP,RGB_2_xvYCC Conversion Y to R Register"
hexmask.long.byte 0x04 0.--4. 1. " Y2RCOEFF_H ,xvYCC to RGB conversion Y to R coefficient upper byte"
group.long 0x24C++0x07
line.long 0x00 "CR2R_COEFF_LOW,RGB_2_xvYCC Conversion Cr to R Register"
hexmask.long.byte 0x00 0.--7. 1. " CR2RCOEFF_L ,xvYCC to RGB conversion Cr to R coefficient lower byte"
line.long 0x04 "CR2R_COEFF_UP,RGB_2_xvYCC Conversion Cr to R Register"
hexmask.long.byte 0x04 0.--4. 1. " CR2RCOEFF_H ,xvYCC to RGB conversion Cr to R coefficient upper byte"
group.long 0x254++0x07
line.long 0x00 "CB2B_COEFF_LOW,RGB_2_xvYCC Conversion Cb to B Register"
hexmask.long.byte 0x00 0.--7. 1. " CB2BCOEFF_L ,xvYCC to RGB conversion Cb to B coefficient lower byte"
line.long 0x04 "CB2B_COEFF_UP,RGB_2_xvYCC Conversion Cb to B Register"
hexmask.long.byte 0x04 0.--4. 1. " CB2BCOEFF_H ,xvYCC to RGB conversion Cb to B coefficient upper byte"
group.long 0x25C++0x07
line.long 0x00 "CR2G_COEFF_LOW,RGB_2_xvYCC Conversion Cr to G Register"
hexmask.long.byte 0x00 0.--7. 1. " CR2GCOEFF_L ,xvYCC to RGB conversion Cr to G coefficient lower byte"
line.long 0x04 "CR2G_COEFF_UP,RGB_2_xvYCC Conversion Cr to G Register"
hexmask.long.byte 0x04 0.--4. 1. " CR2GCOEFF_H ,xvYCC to RGB conversion Cr to G coefficient upper byte"
group.long 0x264++0x07
line.long 0x00 "CB2G_COEFF_LOW,RGB_2_xvYCC Conversion Cb to G Register"
hexmask.long.byte 0x00 0.--7. 1. " CB2GCOEFF_L ,xvYCC to RGB conversion Cb to G coefficient lower byte"
line.long 0x04 "CB2G_COEFF_UP,RGB_2_xvYCC Conversion Cb to G Register"
hexmask.long.byte 0x04 0.--4. 1. " CB2GCOEFF_H ,xvYCC to RGB conversion Cb to G coefficient upper byte"
group.long 0x26C++0x23
line.long 0x00 "YOFFSET1_LOW,xvYCC_2_RGB Conversion Y Offset Register"
hexmask.long.byte 0x00 0.--7. 1. " YOFFS1_L ,xvYCC2RGB Y Offset Coefficient lower byte"
line.long 0x04 "YOFFSET1_UP,xvYCC_2_RGB Conversion Y Offset Register"
bitfld.long 0x04 0.--3. " YOFFS1_H ,xvYCC2RGB Y Offset Coefficient upper byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "OFFSET1_LOW,xvYCC_2_RGB Conversion Offset1 Register"
hexmask.long.byte 0x08 0.--7. 1. " OFFS1_L ,xvYCC2RGB Offset1 Coefficient lower byte"
line.long 0x0C "OFFSET1_MID,xvYCC_2_RGB Conversion Offset1 Register"
hexmask.long.byte 0x0C 0.--7. 1. " OFFS1_M ,xvYCC2RGB Y Offset Coefficient mid byte"
line.long 0x10 "OFFSET1_UP,xvYCC_2_RGB Conversion Offset1 Register"
hexmask.long.byte 0x10 0.--7. 1. " OFFS1_H ,xvYCC2RGB Y Offset Coefficient upper byte"
line.long 0x14 "OFFSET2_LOW,xvYCC_2_RGB Conversion Offset2 Register"
hexmask.long.byte 0x14 0.--7. 1. " OFFS2_L ,xvYCC2RGB Offset2 Coefficient lower byte "
line.long 0x18 "OFFSET2_UP,xvYCC_2_RGB Conversion Offset2 Register"
bitfld.long 0x18 0.--3. " OFFS2_H ,xvYCC2RGB Offset1 Coefficient uper byte" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "DCLEVEL_LOW,xvYCC_2_RGB Conversion DC Level Register"
hexmask.long.byte 0x1C 0.--7. 1. " DC_LEV_L ,xvYCC2RGB DC lelvel coefficient lower byte"
line.long 0x20 "DC_LEVEL_UP,xvYCC_2_RGB Conversion DC Level Register"
hexmask.long.byte 0x20 0.--5. 1. " DC_LEV_H ,xvYCC2RGB DC lelvel coefficient upper byte"
group.long 0x3B0++0x17
line.long 0x00 "DDC_MAN,DDC I2C Manual Register"
bitfld.long 0x00 7. " MAN_OVR ,Manual Override of SCL and SDA output" "Normal,Override"
bitfld.long 0x00 5. " MAN_SDA ,Manual SDA output" "Low,High"
textline " "
bitfld.long 0x00 4. " MAN_SCL ,Manual SCL output" "Low,High"
bitfld.long 0x00 1. " IO_SCL ,DDC SCL input state" "Low,High"
textline " "
bitfld.long 0x00 0. " IO_SDA ,DDC SDA input state" "Low,High"
line.long 0x04 "DDC_ADDR,DDC I2C Target Slave Address Register"
hexmask.long.byte 0x04 1.--7. 0x2 " DDC_ADDR ,DDC device address"
line.long 0x08 "DDC_SEGM,DDC I2C Target Segment Address Register"
hexmask.long.byte 0x08 0.--7. 1. " DDC_SEGM ,DDC segment address"
line.long 0x0C "DDC_OFFSET,DDC I2C Target Offset Address Register"
hexmask.long.byte 0x0C 0.--7. 1. " DDC_OFFSET ,DDC offset address"
line.long 0x10 "DDC_COUNT1,DDC I2C Data Count Register"
hexmask.long.byte 0x10 0.--7. 1. " DDC_COUNT ,DDC count 1"
line.long 0x14 "DDC_COUNT2,DDC I2C Data Count Register"
hexmask.long.byte 0x14 0.--7. 1. " DDC_COUNT ,DDC count 2"
rgroup.long 0x3C8++0x03
line.long 0x00 "DDC_STATUS,DDC I2C Status Register"
bitfld.long 0x00 6. " BUS_LOW ,I2C bus pulled LOW" "Not pulled,Pulled"
bitfld.long 0x00 5. " NO_ACK ,HDMI tx ack not recieved" "Recived,Not recived"
textline " "
bitfld.long 0x00 4. " IN_PROG ,DDC operation in progress" "Not in progress,In progress"
bitfld.long 0x00 3. " FIFO_FULL ,DDC FIFO Full" "Not full,Full"
textline " "
bitfld.long 0x00 2. " FIFO_EMP ,DDC FIFO Empty" "Not empty,Empty"
bitfld.long 0x00 1. " FRD_USE ,DDC FIFO Read In Use" "Not used,Used"
textline " "
bitfld.long 0x00 0. " FWT_USE ,DDC FIFO Write In Use" "Not used,Used"
group.long 0x3CC++0x03
line.long 0x00 "DDC_CMD,DDC I2C Command Register"
bitfld.long 0x00 5. " DDC_FLT_EN ,Enable the DDC delay" "Enabled,Disabled"
bitfld.long 0x00 4. " SDA_DEL_EN ,Enable 3ns glitch filtering on the DDC clock and data line" "Enabled,Disabled"
textline " "
bitfld.long 0x00 0.--3. " DDC_CMD ,DDC command" "Current Address no ACK,Reserved,Sequential Read no ACK,Reserved,Enhanced DDC Read no ACK,Reserved,Sequential Write ignoring ACK,Sequential Write requiring ACK,Reserved,Clear FIFO,Clock SCL,Reserved,Reserved,Reserved,Reserved,Abort Transaction"
hgroup.long 0x3D0++0x03
hide.long 0x00 "DDC_DATA,DDC I2C Data Register"
in
rgroup.long 0x3D4++0x03
line.long 0x00 "DDC_FIFOCNT,DDC I2C FIFO Count Register"
bitfld.long 0x00 0.--4. " DDC_FIFOCNT ,FIFO data byte count (the number of bytes in the FIFO)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E4++0x07
line.long 0x00 "EPST,ROM Status Register"
bitfld.long 0x00 6. " BIST2_ERR ,BIST self authentication test 2 error" "No error,Error"
bitfld.long 0x00 5. " BIST1_ERR ,BIST self authentication test 1 error" "No error,Error"
textline " "
bitfld.long 0x00 1. " CRC_ERR ,error" "No error,Error"
bitfld.long 0x00 0. " CMDD ,Command Done (last operation completed successfully)" "Not successfull,Successfull"
line.long 0x04 "EPCM,ROM Command Register"
bitfld.long 0x04 5. " LD_KSV ,Enable loading of KSV from OTP" "Dsiabled,Enabled"
bitfld.long 0x04 0.--4. " EPCM ,Command" "Reserved,Reserved,Reserved,All tests,CRC test,Reserved,Reserved,Reserved,BIST test 1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,BIST test 2,?..."
width 0xb
tree.end
tree "HDMI_IP_CORE_GAMUT (HDMI IP Core Gamut Registers)"
base ad:0x46C00800
width 17.
group.long 0x00++0x0B
line.long 0x00 "GAMUT_HEADER1,Gamut Metadata Registers "
hexmask.long.byte 0x00 0.--7. 1. " HEADER1 ,Gamut Metadata Header information"
line.long 0x04 "GAMUT_HEADER2,Gamut Metadata Registers "
bitfld.long 0x04 7. " NEXT_FIELD ,Indicates that the GBD will be effective on the next video field" "Low,High"
bitfld.long 0x04 4.--6. " GBD_PROFILE ,Transmission profile number. Values from 0x4 to 0x7 are reserved." "P0,P1,P2,P3,?..."
textline " "
bitfld.long 0x04 0.--3. " AFF_GAM_SEQ_NUM ,Indicates which video fields are relevant for this metadata" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "GAMUT_HEADER3,Gamut Metadata Registers "
bitfld.long 0x08 7. " NO_CRNT_GBD ,Indicates no gamut metadata available for currently transmitted video" "Low,High"
bitfld.long 0x08 4.--5. " PACKET_SEQ ,Indicates the position of current packet." "Intermediate packet,First packet,Last packet,Only sequence"
textline " "
bitfld.long 0x08 0.--3. " CUR_GAM_SEQ_NUM ,Indicates the gamut number of the currently transmitted video stream. " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
tree "GAMUT_DBYTE"
group.long 0xC++0x03
line.long 0x00 "GAMUT_DBYTE_0,Gamut Metadata Register 0"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x10++0x03
line.long 0x00 "GAMUT_DBYTE_1,Gamut Metadata Register 1"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x14++0x03
line.long 0x00 "GAMUT_DBYTE_2,Gamut Metadata Register 2"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x18++0x03
line.long 0x00 "GAMUT_DBYTE_3,Gamut Metadata Register 3"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x1C++0x03
line.long 0x00 "GAMUT_DBYTE_4,Gamut Metadata Register 4"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x20++0x03
line.long 0x00 "GAMUT_DBYTE_5,Gamut Metadata Register 5"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x24++0x03
line.long 0x00 "GAMUT_DBYTE_6,Gamut Metadata Register 6"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x28++0x03
line.long 0x00 "GAMUT_DBYTE_7,Gamut Metadata Register 7"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x2C++0x03
line.long 0x00 "GAMUT_DBYTE_8,Gamut Metadata Register 8"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x30++0x03
line.long 0x00 "GAMUT_DBYTE_9,Gamut Metadata Register 9"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x34++0x03
line.long 0x00 "GAMUT_DBYTE_10,Gamut Metadata Register 10"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x38++0x03
line.long 0x00 "GAMUT_DBYTE_11,Gamut Metadata Register 11"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x3C++0x03
line.long 0x00 "GAMUT_DBYTE_12,Gamut Metadata Register 12"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x40++0x03
line.long 0x00 "GAMUT_DBYTE_13,Gamut Metadata Register 13"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x44++0x03
line.long 0x00 "GAMUT_DBYTE_14,Gamut Metadata Register 14"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x48++0x03
line.long 0x00 "GAMUT_DBYTE_15,Gamut Metadata Register 15"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x4C++0x03
line.long 0x00 "GAMUT_DBYTE_16,Gamut Metadata Register 16"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x50++0x03
line.long 0x00 "GAMUT_DBYTE_17,Gamut Metadata Register 17"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x54++0x03
line.long 0x00 "GAMUT_DBYTE_18,Gamut Metadata Register 18"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x58++0x03
line.long 0x00 "GAMUT_DBYTE_19,Gamut Metadata Register 19"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x5C++0x03
line.long 0x00 "GAMUT_DBYTE_20,Gamut Metadata Register 20"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x60++0x03
line.long 0x00 "GAMUT_DBYTE_21,Gamut Metadata Register 21"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x64++0x03
line.long 0x00 "GAMUT_DBYTE_22,Gamut Metadata Register 22"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x68++0x03
line.long 0x00 "GAMUT_DBYTE_23,Gamut Metadata Register 23"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x6C++0x03
line.long 0x00 "GAMUT_DBYTE_24,Gamut Metadata Register 24"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x70++0x03
line.long 0x00 "GAMUT_DBYTE_25,Gamut Metadata Register 25"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x74++0x03
line.long 0x00 "GAMUT_DBYTE_26,Gamut Metadata Register 26"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
group.long 0x78++0x03
line.long 0x00 "GAMUT_DBYTE_27,Gamut Metadata Register 27"
hexmask.long.byte 0x00 0.--7. 1. " GAM_MDATA ,Gamut Metadata Data Bytes"
tree.end
width 0xb
tree.end
tree "HDMI_IP_CORE_AUDIO_VIDEO (HDMI IP Core Audio Video Registers)"
base ad:0x46C00900
width 24.
group.long 0x004++0x1F
line.long 0x00 "ACR_CTRL,ACR Control Register"
bitfld.long 0x00 1. " NCTSPKT_EN ,CTS Request Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " CTS_SEL ,CTS Source Select" "HW,SW"
line.long 0x04 "FREQ_SVAL,ACR Audio Frequency Register"
bitfld.long 0x04 0.--2. " MCLK_CONF ,MCLK input mode" "128*Fs,256*Fs,384*Fs,512*Fs,768*Fs,1024*Fs,1152*Fs,192*Fs"
line.long 0x08 "N_SVAL1,ACR N Software Value Register"
hexmask.long.byte 0x08 0.--7. 1. " N_SVAL ,N Value for audio clock regeneration method"
line.long 0x0C "N_SVAL2,ACR N Software Value Register"
hexmask.long.byte 0x0C 0.--7. 1. " N_SVAL ,N Value for audio clock regeneration method"
line.long 0x10 "N_SVAL3,ACR N Software Value Register"
bitfld.long 0x10 0.--3. " N_SVAL ,N Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "CTS_SVAL1,ACR CTS Software Value Register"
hexmask.long.byte 0x14 0.--7. 1. " CTS_SVAL ,CTS Value for audio clock regeneration method"
line.long 0x18 "CTS_SVAL2,ACR CTS Software Value Register"
hexmask.long.byte 0x18 0.--7. 1. " CTS_SVAL ,CTS Value for audio clock regeneration method"
line.long 0x1C "CTS_SVAL3,ACR CTS Software Value Register"
bitfld.long 0x1C 0.--3. " CTS_SVAL ,CTS Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x024++0x0B
line.long 0x00 "CTS_HVAL1,ACR CTS Hardware Value Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS_HVAL ,CTS Value for audio clock regeneration method"
line.long 0x04 "CTS_HVAL2,ACR CTS Hardware Value Register"
hexmask.long.byte 0x04 0.--7. 1. " CTS_HVAL ,CTS Value for audio clock regeneration method"
line.long 0x08 "CTS_HVAL3,ACR CTS Hardware Value Register"
bitfld.long 0x08 0.--3. " CTS_HVAL ,CTS Value for audio clock regeneration method" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x050++0x07
line.long 0x00 "AUD_MODE,Audio In Mode Register"
bitfld.long 0x00 7. " SD3_EN ,I2S input channel 3" "Disabled,Enabled"
bitfld.long 0x00 6. " SD2_EN ,I2S input channel 2" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " SD1_EN ,I2S input channel 1" "Disabled,Enabled"
bitfld.long 0x00 4. " SD0_EN ,I2S input channel 0" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DSD_EN ,Direct Stream Digital Audio enable" "Disabled,Enabled"
bitfld.long 0x00 2. " AUD_PAR_EN ,Parallel audio input enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " SPDIF_EN ,S/PDIF input stream enable" "Disabled,Enabled"
bitfld.long 0x00 0. " AUD_EN ,Audio input stream enable" "Disabled,Enabled"
line.long 0x04 "SPDIF_CTRL,Audio In S/PDIF Control Register"
bitfld.long 0x04 3. " NOAUDIO ,No S/PDIF audio" "Detected,Not detected"
bitfld.long 0x04 1. " FS_OVERRIDE ,S/PDIF input stream override" "S/PDIF input,S/W FS"
rgroup.long 0x060++0x03
line.long 0x00 "HW_SPDIF_FS,Audio In S/PDIF Extracted Fs and Length Register"
bitfld.long 0x00 5.--7. " HW_SPDIF_LEN ,Channel status bits" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. " HW_MAXLEN ,Maximum sample length" "20bits,24bits"
textline " "
bitfld.long 0x00 0.--3. " HW_SPDIF_FS ,Set to the FS extracted from the S/PDIF input channel status bits 24-27." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x064++0x03
line.long 0x00 "SWAP_I2S,Audio In I2S Channel Swap Register"
bitfld.long 0x00 7. " SWCH3 ,Swap left-right channels for I2S Channel 3" "Not swap,Swap"
bitfld.long 0x00 6. " SWCH2 ,Swap left-right channels for I2S Channel 2" "Not swap,Swap"
textline " "
bitfld.long 0x00 5. " SWCH1 ,Swap left-right channels for I2S Channel 1" "Not swap,Swap"
bitfld.long 0x00 4. " SWCH0 ,Swap left-right channels for I2S Channel 0" "Not swap,Swap"
group.long 0x06C++0x27
line.long 0x00 "SPDIF_ERTH,Audio Error Threshold Register"
hexmask.long.byte 0x00 0.--5. 1. " AUD_ERR_THRESH ,Specifies the error threshold level"
line.long 0x04 "I2S_IN_MAP,Audio In I2S Data In Map Register"
bitfld.long 0x04 6.--7. " FIFO3_MAP ,Channel map to FIFO 3" "SD0,SD1,SD2,SD3"
bitfld.long 0x04 4.--5. " FIFO2_MAP ,Channel map to FIFO 2" "SD0,SD1,SD2,SD3"
textline " "
bitfld.long 0x04 2.--3. " FIFO1_MAP ,Channel map to FIFO 1" "SD0,SD1,SD2,SD3"
bitfld.long 0x04 0.--1. " FIFO0_MAP ,Channel map to FIFO 0" "SD0,SD1,SD2,SD3"
line.long 0x08 "I2S_IN_CTRL,Audio In I2S Control Register"
bitfld.long 0x08 7. " HBRA_ON ,High Bit Rate Audio On" "Disabled,Enabled"
bitfld.long 0x08 6. " SCK_EDGE ,SCK sample edge" "Falling,Rising"
textline " "
bitfld.long 0x08 5. " CBIT_ORDER ,This bit should be set to 1 for High Bit Rate Audio" "Low,High"
bitfld.long 0x08 4. " VBIT ,V bit value" "PCM,Compressed"
textline " "
bitfld.long 0x08 3. " I2S_WS ,WS polarity" "Low,High"
bitfld.long 0x08 2. " I2S_JUST ,SD justify" "Left,Right"
textline " "
bitfld.long 0x08 1. " I2S_DIR ,SD direction" "MSB,LSB"
bitfld.long 0x08 0. " I2S_SHIFT ,WS to SD first bit shift" "First bit shift,No shift"
line.long 0x0C "I2S_CHST0,Audio In I2S Channel Status Registers"
hexmask.long.byte 0x0C 0.--7. 1. " I2S_CHST0 ,Channel Status Byte 0"
line.long 0x10 "I2S_CHST1,Audio In I2S Channel Status Registers"
hexmask.long.byte 0x10 0.--7. 1. " I2S_CHST1 ,Channel Status Byte 1"
line.long 0x14 "I2S_CHST2,Audio In I2S Channel Status Registers"
bitfld.long 0x14 4.--7. " I2S_CHAN_NUM ,Channel Status Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 0.--3. " I2S_SRC_NUM ,Channel Status Byte 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "I2S_CHST4,Audio In I2S Channel Status Registers"
bitfld.long 0x18 4.--7. " CLK_ACCUR ,Clock Accuracy" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. " SW_SPDIF_FS ,Sampling frequency as set by software" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "I2S_CHST5,Audio In I2S Channel Status Registers"
bitfld.long 0x1C 4.--7. " FS_ORIG ,Original Fs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 1.--3. " I2S_LEN ,Audio sample word length" "Not indicated,16 20,18 20,Reserved,19 23,20 24,17 21,?..."
textline " "
bitfld.long 0x1C 0. " I2S_MAXLEN ,Maximum audio sample word length" "20bits,24bits"
line.long 0x20 "ASRC,Audio Sample Rate Conversion Register"
bitfld.long 0x20 7. " HBR_SPR_MASK_3 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 3" "Masked,Not masked"
bitfld.long 0x20 6. " HBR_SPR_MASK_2 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 2" "Masked,Not masked"
textline " "
bitfld.long 0x20 5. " HBR_SPR_MASK_1 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 1" "Masked,Not masked"
bitfld.long 0x20 4. " HBR_SPR_MASK_0 ,Mask for the sample present and flat bit of the High Bit Rate Audio header 0" "Masked,Not masked"
textline " "
bitfld.long 0x20 1. " RATIO ,Sample rate down-conversion ratio" "2-to-1,4-to-1"
bitfld.long 0x20 0. " SRC_EN ,Audio sample rate conversion" "Disabled,Enabled"
line.long 0x24 "I2S_IN_LEN,Audio I2S Input Length Register"
bitfld.long 0x24 4.--7. " HDR_PKT_ID ,The ID of the High Bit Rate Audio packet header" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 0.--3. " IN_LENGTH ,Number of valid bits in the input I2S stream" "Reserved,Reserved,16bit,Reserved,18bit,22bit,Reserved,Reserved,19bit,23bit,20bit,24bit,17bit,21bit,?..."
group.long 0x0BC++0x07
line.long 0x00 "HDMI_CTRL,HDMI Control Register"
bitfld.long 0x00 6. " DC_EN ,Deep-color packet enable" "Not send,Send"
bitfld.long 0x00 3.--5. " PACKET_MODE ,Specifies the number of bits per pixel sent to the paketizer" "Reserved,Reserved,Reserved,Reserved,24bits,30bits,36bits,48bits"
textline " "
bitfld.long 0x00 1.--2. " LAYOUT ,Audio packet header layout indicator" "Layout 0,Layout 1,?..."
bitfld.long 0x00 0. " HDMI_MODE ,HDMI mode" "Disabled,Enabled"
line.long 0x04 "AUDO_TXSTAT,Audio Path Status Register"
bitfld.long 0x04 2. " MUTE ,General Control Packet mute status" "No packet,Packet"
bitfld.long 0x04 1. " NPACKET_EN_VS_HIGH ,Enables null packet flooding only when VSync is high" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " NPACKET_EN ,Enables null packet flooding all the time" "Disabled,Enabled"
group.long 0x0CC++0x0B
line.long 0x00 "AUD_PAR_BUSCLK_1,Audio Input Data Rate Adjustment Register "
hexmask.long.byte 0x00 0.--7. 1. " AUD_PAR_BUSCLK_1 ,Decimal part of adjusment parameter"
line.long 0x04 "AUD_PAR_BUSCLK_2,Audio Input Data Rate Adjustment Register "
hexmask.long.byte 0x04 0.--7. 1. " AUD_PAR_BUSCLK_2 ,Lower byte of integer part of parameter"
line.long 0x08 "AUD_PAR_BUSCLK_3,Audio Input Data Rate Adjustment Register "
hexmask.long.byte 0x08 0.--7. 1. " AUD_PAR_BUSCLK_3 ,Upper byte of integer part of parameter"
group.long 0x0F0++0x1F
line.long 0x00 "TEST_TXCTRL,Test Control Register"
bitfld.long 0x00 3. " DIV_ENC_BYP ,DVI encoder bypass" "Not bypassed,Bypassed"
bitfld.long 0x00 2. " CORE_ISO_EN ,TMDS Core Isolation Enable" "Normal,Mixed"
line.long 0x04 "DPD,Diagnostic Power Down Register"
bitfld.long 0x04 7. " VID_BYP_EN ,Enable bypath of the video path" "Disable,Enable"
bitfld.long 0x04 3. " TCLKPHZ ,Selects the TCLK phase" "Default phase,Invert TCLK"
textline " "
bitfld.long 0x04 2. " PDIDCK ,Power down IDCK input" "Power down,Normal operation"
bitfld.long 0x04 1. " PDOSC ,Power donw internal oscillator" "Power down,Normal operation"
textline " "
bitfld.long 0x04 0. " PDTOT ,Power down total" "Power down,Normal operation"
line.long 0x08 "PB_CTRL1,Packet Buffer Control 1 Register"
bitfld.long 0x08 7. " MPEG_EN ,Enable MPEG InfoFrame transmission" "Disabled,Enabled"
bitfld.long 0x08 6. " MPEG_RPT ,Repeat MPEG InfoFrame transmission" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " AUD_EN ,Enable Audio InfoFrame transmission" "Disabled,Enabled"
bitfld.long 0x08 4. " AUD_RPT ,Repeat Audio InfoFrame transmission" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " SPD_EN ,Enable SPD InfoFrame transmission" "Disabled,Enabled"
bitfld.long 0x08 2. " SPD_RPT ,Repeat SPD InfoFrame transmission" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " AVI_EN ,Enable AVI InfoFrame transmission" "Disabled,Enabled"
bitfld.long 0x08 0. " AVI_RPT ,Repeat AVI InfoFrame transmission" "Disabled,Enabled"
line.long 0x0C "PB_CTRL2,Packet Buffer Control 2 Register"
bitfld.long 0x0C 7. " GAM_EN ,Enable Gamut Metadata InfoFrame transmission on HDMI" "Disabled,Enabled"
bitfld.long 0x0C 6. " GAM_RPT ,Repeat Gamut Metadata InfoFrame Packet data each frame" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 5. " GEN2_EN ,Enable Generic 2 Packet transmission" "Disabled,Enabled"
bitfld.long 0x0C 4. " GEN2_RPT ,Repeat Generic 2 Packet transmission" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 3. " CP_EN ,Enable General Control Packet transmission" "Disabled,Enabled"
bitfld.long 0x0C 2. " CP_RPT ,Repeat General Control Packet transmission" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 1. " GEN_EN ,Enable Generic Packet transmission" "Disabled,Enabled"
bitfld.long 0x0C 0. " GEN_RPT ,Repeat Generic Packet transmission" "Disabled,Enabled"
line.long 0x10 "AVI_TYPE,Packet Registers"
hexmask.long.byte 0x10 0.--7. 1. " AVI_TYPE ,AVI InfoFrame Type Code"
line.long 0x14 "AVI_VERS,Packet Registers"
hexmask.long.byte 0x14 0.--7. 1. " AVI_VERS ,AVI InfoFrame Version Code"
line.long 0x18 "AVI_LEN,Packet Registers"
hexmask.long.byte 0x18 0.--7. 1. " AVI_LEN ,AVI InfoFrame Length"
line.long 0x1C "AVI_CHSUM,Packet Registers"
hexmask.long.byte 0x1C 0.--7. 1. " AVI_CHSUM ,AVI InfoFrame Checksum"
tree "AVI_DBYTE"
group.long 0x110++0x03
line.long 0x00 "AVI_DBYTE_0,Packet Register 0"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x114++0x03
line.long 0x00 "AVI_DBYTE_1,Packet Register 1"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x118++0x03
line.long 0x00 "AVI_DBYTE_2,Packet Register 2"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x11C++0x03
line.long 0x00 "AVI_DBYTE_3,Packet Register 3"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x120++0x03
line.long 0x00 "AVI_DBYTE_4,Packet Register 4"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x124++0x03
line.long 0x00 "AVI_DBYTE_5,Packet Register 5"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x128++0x03
line.long 0x00 "AVI_DBYTE_6,Packet Register 6"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x12C++0x03
line.long 0x00 "AVI_DBYTE_7,Packet Register 7"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x130++0x03
line.long 0x00 "AVI_DBYTE_8,Packet Register 8"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x134++0x03
line.long 0x00 "AVI_DBYTE_9,Packet Register 9"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x138++0x03
line.long 0x00 "AVI_DBYTE_10,Packet Register 10"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x13C++0x03
line.long 0x00 "AVI_DBYTE_11,Packet Register 11"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x140++0x03
line.long 0x00 "AVI_DBYTE_12,Packet Register 12"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x144++0x03
line.long 0x00 "AVI_DBYTE_13,Packet Register 13"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
group.long 0x148++0x03
line.long 0x00 "AVI_DBYTE_14,Packet Register 14"
hexmask.long.byte 0x00 0.--7. 1. " AVI_DATA ,AVI InfoFrame Data Bytes"
tree.end
textline " "
group.long 0x180++0x0F
line.long 0x00 "SPD_TYPE,SPD InfoFrame Registers"
hexmask.long.byte 0x00 0.--7. 1. " SPD_TYPE ,SPD InfoFrame Type Code"
line.long 0x04 "SPD_VERS,SPD InfoFrame Registers"
hexmask.long.byte 0x04 0.--7. 1. " SPD_VERS ,SPD InfoFrame Version Code"
line.long 0x08 "SPD_LEN,SPD InfoFrame Registers"
hexmask.long.byte 0x08 0.--7. 1. " SPD_LEN ,SPD InfoFrame Length"
line.long 0x0C "SPD_CHSUM,SPD InfoFrame Registers"
hexmask.long.byte 0x0C 0.--7. 1. " SPD_CHSUM ,SPD InfoFrame Checksum"
tree "SPD_DBYTE"
group.long 0x190++0x03
line.long 0x00 "SPD_DBYTE_0,SPD InfoFrame Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x194++0x03
line.long 0x00 "SPD_DBYTE_1,SPD InfoFrame Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x198++0x03
line.long 0x00 "SPD_DBYTE_2,SPD InfoFrame Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x19C++0x03
line.long 0x00 "SPD_DBYTE_3,SPD InfoFrame Register 3"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1A0++0x03
line.long 0x00 "SPD_DBYTE_4,SPD InfoFrame Register 4"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1A4++0x03
line.long 0x00 "SPD_DBYTE_5,SPD InfoFrame Register 5"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1A8++0x03
line.long 0x00 "SPD_DBYTE_6,SPD InfoFrame Register 6"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1AC++0x03
line.long 0x00 "SPD_DBYTE_7,SPD InfoFrame Register 7"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1B0++0x03
line.long 0x00 "SPD_DBYTE_8,SPD InfoFrame Register 8"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1B4++0x03
line.long 0x00 "SPD_DBYTE_9,SPD InfoFrame Register 9"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1B8++0x03
line.long 0x00 "SPD_DBYTE_10,SPD InfoFrame Register 10"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1BC++0x03
line.long 0x00 "SPD_DBYTE_11,SPD InfoFrame Register 11"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1C0++0x03
line.long 0x00 "SPD_DBYTE_12,SPD InfoFrame Register 12"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1C4++0x03
line.long 0x00 "SPD_DBYTE_13,SPD InfoFrame Register 13"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1C8++0x03
line.long 0x00 "SPD_DBYTE_14,SPD InfoFrame Register 14"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1CC++0x03
line.long 0x00 "SPD_DBYTE_15,SPD InfoFrame Register 15"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1D0++0x03
line.long 0x00 "SPD_DBYTE_16,SPD InfoFrame Register 16"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1D4++0x03
line.long 0x00 "SPD_DBYTE_17,SPD InfoFrame Register 17"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1D8++0x03
line.long 0x00 "SPD_DBYTE_18,SPD InfoFrame Register 18"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1DC++0x03
line.long 0x00 "SPD_DBYTE_19,SPD InfoFrame Register 19"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1E0++0x03
line.long 0x00 "SPD_DBYTE_20,SPD InfoFrame Register 20"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1E4++0x03
line.long 0x00 "SPD_DBYTE_21,SPD InfoFrame Register 21"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1E8++0x03
line.long 0x00 "SPD_DBYTE_22,SPD InfoFrame Register 22"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1EC++0x03
line.long 0x00 "SPD_DBYTE_23,SPD InfoFrame Register 23"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1F0++0x03
line.long 0x00 "SPD_DBYTE_24,SPD InfoFrame Register 24"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1F4++0x03
line.long 0x00 "SPD_DBYTE_25,SPD InfoFrame Register 25"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
group.long 0x1F8++0x03
line.long 0x00 "SPD_DBYTE_26,SPD InfoFrame Register 26"
hexmask.long.byte 0x00 0.--7. 1. " SPD_DATA ,SPD InfoFrame Data Bytes"
tree.end
textline " "
group.long 0x200++0x0F
line.long 0x00 "AUDIO_TYPE,Audio InfoFrame Registers"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_TYPE ,AUDIO InfoFrame Type Code"
line.long 0x04 "AUDIO_VERS,Audio InfoFrame Registers"
hexmask.long.byte 0x04 0.--7. 1. " AUDIO_VERS ,AUDIO InfoFrame Version Code"
line.long 0x08 "AUDIO_LEN,Audio InfoFrame Registers"
hexmask.long.byte 0x08 0.--7. 1. " AUDIO_LEN ,AUDIO InfoFrame Length"
line.long 0x0C "AUDIO_CHSUM,Audio InfoFrame Registers"
hexmask.long.byte 0x0C 0.--7. 1. " AUDIO_CHSUM ,AUDIO InfoFrame Checksum"
tree "AUDIO_DBYTE"
group.long 0x210++0x03
line.long 0x00 "AUDIO_DBYTE_0,Audio InfoFrame Register 0"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x214++0x03
line.long 0x00 "AUDIO_DBYTE_1,Audio InfoFrame Register 1"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x218++0x03
line.long 0x00 "AUDIO_DBYTE_2,Audio InfoFrame Register 2"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x21C++0x03
line.long 0x00 "AUDIO_DBYTE_3,Audio InfoFrame Register 3"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x220++0x03
line.long 0x00 "AUDIO_DBYTE_4,Audio InfoFrame Register 4"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x224++0x03
line.long 0x00 "AUDIO_DBYTE_5,Audio InfoFrame Register 5"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x228++0x03
line.long 0x00 "AUDIO_DBYTE_6,Audio InfoFrame Register 6"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x22C++0x03
line.long 0x00 "AUDIO_DBYTE_7,Audio InfoFrame Register 7"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x230++0x03
line.long 0x00 "AUDIO_DBYTE_8,Audio InfoFrame Register 8"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
group.long 0x234++0x03
line.long 0x00 "AUDIO_DBYTE_9,Audio InfoFrame Register 9"
hexmask.long.byte 0x00 0.--7. 1. " AUDIO_DATA ,AUDIO InfoFrame Data Bytes."
tree.end
textline " "
group.long 0x280++0x0F
line.long 0x00 "MPEG_TYPE,MPEG InfoFrame Registers"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_TYPE ,MPEG InfoFrame Type Code"
line.long 0x04 "MPEG_VERS,MPEG InfoFrame Registers"
hexmask.long.byte 0x04 0.--7. 1. " MPEG_VERS ,MPEG InfoFrame Version Code"
line.long 0x08 "MPEG_LEN,MPEG InfoFrame Registers"
hexmask.long.byte 0x08 0.--7. 1. " MPEG_LEN ,MPEG InfoFrame Length"
line.long 0x0C "MPEG_CHSUM,MPEG InfoFrame Registers"
hexmask.long.byte 0x0C 0.--7. 1. " MPEG_CHSUM ,MPEG InfoFrame Checksum"
tree "MPEG_DBYTE"
group.long 0x290++0x03
line.long 0x00 "MPEG_DBYTE_0,MPEG InfoFrame Register 0"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x294++0x03
line.long 0x00 "MPEG_DBYTE_1,MPEG InfoFrame Register 1"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x298++0x03
line.long 0x00 "MPEG_DBYTE_2,MPEG InfoFrame Register 2"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x29C++0x03
line.long 0x00 "MPEG_DBYTE_3,MPEG InfoFrame Register 3"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2A0++0x03
line.long 0x00 "MPEG_DBYTE_4,MPEG InfoFrame Register 4"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2A4++0x03
line.long 0x00 "MPEG_DBYTE_5,MPEG InfoFrame Register 5"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2A8++0x03
line.long 0x00 "MPEG_DBYTE_6,MPEG InfoFrame Register 6"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2AC++0x03
line.long 0x00 "MPEG_DBYTE_7,MPEG InfoFrame Register 7"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2B0++0x03
line.long 0x00 "MPEG_DBYTE_8,MPEG InfoFrame Register 8"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2B4++0x03
line.long 0x00 "MPEG_DBYTE_9,MPEG InfoFrame Register 9"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2B8++0x03
line.long 0x00 "MPEG_DBYTE_10,MPEG InfoFrame Register 10"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2BC++0x03
line.long 0x00 "MPEG_DBYTE_11,MPEG InfoFrame Register 11"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2C0++0x03
line.long 0x00 "MPEG_DBYTE_12,MPEG InfoFrame Register 12"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2C4++0x03
line.long 0x00 "MPEG_DBYTE_13,MPEG InfoFrame Register 13"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2C8++0x03
line.long 0x00 "MPEG_DBYTE_14,MPEG InfoFrame Register 14"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2CC++0x03
line.long 0x00 "MPEG_DBYTE_15,MPEG InfoFrame Register 15"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2D0++0x03
line.long 0x00 "MPEG_DBYTE_16,MPEG InfoFrame Register 16"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2D4++0x03
line.long 0x00 "MPEG_DBYTE_17,MPEG InfoFrame Register 17"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2D8++0x03
line.long 0x00 "MPEG_DBYTE_18,MPEG InfoFrame Register 18"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2DC++0x03
line.long 0x00 "MPEG_DBYTE_19,MPEG InfoFrame Register 19"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2E0++0x03
line.long 0x00 "MPEG_DBYTE_20,MPEG InfoFrame Register 20"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2E4++0x03
line.long 0x00 "MPEG_DBYTE_21,MPEG InfoFrame Register 21"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2E8++0x03
line.long 0x00 "MPEG_DBYTE_22,MPEG InfoFrame Register 22"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2EC++0x03
line.long 0x00 "MPEG_DBYTE_23,MPEG InfoFrame Register 23"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2F0++0x03
line.long 0x00 "MPEG_DBYTE_24,MPEG InfoFrame Register 24"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2F4++0x03
line.long 0x00 "MPEG_DBYTE_25,MPEG InfoFrame Register 25"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
group.long 0x2F8++0x03
line.long 0x00 "MPEG_DBYTE_26,MPEG InfoFrame Register 26"
hexmask.long.byte 0x00 0.--7. 1. " MPEG_DATA ,MPEG InfoFrame Data Bytes"
tree.end
tree "GEN_DBYTE"
group.long 0x300++0x03
line.long 0x00 "GEN_DBYTE_0,Generic Packet Register 0"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x304++0x03
line.long 0x00 "GEN_DBYTE_1,Generic Packet Register 1"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x308++0x03
line.long 0x00 "GEN_DBYTE_2,Generic Packet Register 2"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x30C++0x03
line.long 0x00 "GEN_DBYTE_3,Generic Packet Register 3"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x310++0x03
line.long 0x00 "GEN_DBYTE_4,Generic Packet Register 4"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x314++0x03
line.long 0x00 "GEN_DBYTE_5,Generic Packet Register 5"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x318++0x03
line.long 0x00 "GEN_DBYTE_6,Generic Packet Register 6"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x31C++0x03
line.long 0x00 "GEN_DBYTE_7,Generic Packet Register 7"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x320++0x03
line.long 0x00 "GEN_DBYTE_8,Generic Packet Register 8"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x324++0x03
line.long 0x00 "GEN_DBYTE_9,Generic Packet Register 9"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x328++0x03
line.long 0x00 "GEN_DBYTE_10,Generic Packet Register 10"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x32C++0x03
line.long 0x00 "GEN_DBYTE_11,Generic Packet Register 11"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x330++0x03
line.long 0x00 "GEN_DBYTE_12,Generic Packet Register 12"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x334++0x03
line.long 0x00 "GEN_DBYTE_13,Generic Packet Register 13"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x338++0x03
line.long 0x00 "GEN_DBYTE_14,Generic Packet Register 14"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x33C++0x03
line.long 0x00 "GEN_DBYTE_15,Generic Packet Register 15"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x340++0x03
line.long 0x00 "GEN_DBYTE_16,Generic Packet Register 16"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x344++0x03
line.long 0x00 "GEN_DBYTE_17,Generic Packet Register 17"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x348++0x03
line.long 0x00 "GEN_DBYTE_18,Generic Packet Register 18"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x34C++0x03
line.long 0x00 "GEN_DBYTE_19,Generic Packet Register 19"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x350++0x03
line.long 0x00 "GEN_DBYTE_20,Generic Packet Register 20"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x354++0x03
line.long 0x00 "GEN_DBYTE_21,Generic Packet Register 21"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x358++0x03
line.long 0x00 "GEN_DBYTE_22,Generic Packet Register 22"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x35C++0x03
line.long 0x00 "GEN_DBYTE_23,Generic Packet Register 23"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x360++0x03
line.long 0x00 "GEN_DBYTE_24,Generic Packet Register 24"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x364++0x03
line.long 0x00 "GEN_DBYTE_25,Generic Packet Register 25"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x368++0x03
line.long 0x00 "GEN_DBYTE_26,Generic Packet Register 26"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x36C++0x03
line.long 0x00 "GEN_DBYTE_27,Generic Packet Register 27"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x370++0x03
line.long 0x00 "GEN_DBYTE_28,Generic Packet Register 28"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x374++0x03
line.long 0x00 "GEN_DBYTE_29,Generic Packet Register 29"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
group.long 0x378++0x03
line.long 0x00 "GEN_DBYTE_30,Generic Packet Register 30"
hexmask.long.byte 0x00 0.--7. 1. " GEN_DATA ,Generic Packet Data Bytes"
tree.end
textline " "
group.long 0x37C++0x03
line.long 0x00 "CP_BYTE1,General Control Packet Register"
bitfld.long 0x00 4. " CLRAVM ,Clear AV Mute flag" "Low,High"
bitfld.long 0x00 0. " SETAVM ,Set AV Mute flag" "Low,High"
tree "GEN2_DBYTE"
group.long 0x380++0x03
line.long 0x00 "GEN2_DBYTE_0,Generic Packet 2 Registers 0"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x384++0x03
line.long 0x00 "GEN2_DBYTE_1,Generic Packet 2 Registers 1"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x388++0x03
line.long 0x00 "GEN2_DBYTE_2,Generic Packet 2 Registers 2"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x38C++0x03
line.long 0x00 "GEN2_DBYTE_3,Generic Packet 2 Registers 3"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x390++0x03
line.long 0x00 "GEN2_DBYTE_4,Generic Packet 2 Registers 4"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x394++0x03
line.long 0x00 "GEN2_DBYTE_5,Generic Packet 2 Registers 5"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x398++0x03
line.long 0x00 "GEN2_DBYTE_6,Generic Packet 2 Registers 6"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x39C++0x03
line.long 0x00 "GEN2_DBYTE_7,Generic Packet 2 Registers 7"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3A0++0x03
line.long 0x00 "GEN2_DBYTE_8,Generic Packet 2 Registers 8"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3A4++0x03
line.long 0x00 "GEN2_DBYTE_9,Generic Packet 2 Registers 9"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3A8++0x03
line.long 0x00 "GEN2_DBYTE_10,Generic Packet 2 Registers 10"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3AC++0x03
line.long 0x00 "GEN2_DBYTE_11,Generic Packet 2 Registers 11"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3B0++0x03
line.long 0x00 "GEN2_DBYTE_12,Generic Packet 2 Registers 12"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3B4++0x03
line.long 0x00 "GEN2_DBYTE_13,Generic Packet 2 Registers 13"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3B8++0x03
line.long 0x00 "GEN2_DBYTE_14,Generic Packet 2 Registers 14"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3BC++0x03
line.long 0x00 "GEN2_DBYTE_15,Generic Packet 2 Registers 15"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3C0++0x03
line.long 0x00 "GEN2_DBYTE_16,Generic Packet 2 Registers 16"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3C4++0x03
line.long 0x00 "GEN2_DBYTE_17,Generic Packet 2 Registers 17"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3C8++0x03
line.long 0x00 "GEN2_DBYTE_18,Generic Packet 2 Registers 18"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3CC++0x03
line.long 0x00 "GEN2_DBYTE_19,Generic Packet 2 Registers 19"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3D0++0x03
line.long 0x00 "GEN2_DBYTE_20,Generic Packet 2 Registers 20"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3D4++0x03
line.long 0x00 "GEN2_DBYTE_21,Generic Packet 2 Registers 21"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3D8++0x03
line.long 0x00 "GEN2_DBYTE_22,Generic Packet 2 Registers 22"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3DC++0x03
line.long 0x00 "GEN2_DBYTE_23,Generic Packet 2 Registers 23"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3E0++0x03
line.long 0x00 "GEN2_DBYTE_24,Generic Packet 2 Registers 24"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3E4++0x03
line.long 0x00 "GEN2_DBYTE_25,Generic Packet 2 Registers 25"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3E8++0x03
line.long 0x00 "GEN2_DBYTE_26,Generic Packet 2 Registers 26"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3EC++0x03
line.long 0x00 "GEN2_DBYTE_27,Generic Packet 2 Registers 27"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3F0++0x03
line.long 0x00 "GEN2_DBYTE_28,Generic Packet 2 Registers 28"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3F4++0x03
line.long 0x00 "GEN2_DBYTE_29,Generic Packet 2 Registers 29"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
group.long 0x3F8++0x03
line.long 0x00 "GEN2_DBYTE_30,Generic Packet 2 Registers 30"
hexmask.long.byte 0x00 0.--7. 1. " GEN2_DATA ,Generic Packet 2 Data Bytes."
tree.end
textline " "
group.long 0x3FC++0x03
line.long 0x00 "CEC_ADDR_ID,CEC Slave ID Register"
hexmask.long.byte 0x00 0.--7. 1. " CEC_ID ,CEC I2C slave address ID"
width 0xb
tree.end
tree "HDMI_IP_CORE_CEC (HDMI IP Core CEC Registers)"
base ad:0x46C00D00
width 23.
rgroup.long 0x00++0x1B
line.long 0x00 "CEC_DEV_ID,CEC Device ID Register"
hexmask.long.byte 0x00 0.--7. 1. " CEC_DEV_ID ,ID of CEC device"
line.long 0x04 "CEC_SPEC,CEC Specification Register"
bitfld.long 0x04 4.--7. " CEC_REL ,CEC Specification major release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. " CEC_REV ,CEC Specification minor release (rev. 1.2)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CEC_SUFF,CEC Specification Suffix Register"
bitfld.long 0x08 7. " SUB_SYS ,Subsytem" "Firmware,Hardware"
bitfld.long 0x08 0.--3. " CEC_SUFF ,CEC Specification Suffix" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "CEC_FW,CEC Firmware Revision Register"
bitfld.long 0x0C 4.--7. " FW_REL_ID ,Firmware Release ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. " FW_REV_ID ,Firmware Revision ID " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "CEC_DBG_0,CEC Debug Register0"
hexmask.long.byte 0x10 0.--7. 1. " STB_LOW_P ,Start Bit Low Period"
line.long 0x14 "CEC_DBG_1,CEC Debug Register1 "
hexmask.long.byte 0x14 0.--7. 1. " STB_DUR_P ,Start Bit Duration Period"
line.long 0x18 "CEC_DBG_2,CEC Debug Register2"
bitfld.long 0x18 4.--7. " CEC_SN_INI ,CEC Snoop Initiator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 0.--3. " CEC_BUS_OWN ,Current CEC bus owner" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1C++0x0B
line.long 0x00 "CEC_DBG_3,CEC Debug Register3"
bitfld.long 0x00 7. " FL_FIF ,Flush Tx FIFO" "Not flushed,Flushed"
bitfld.long 0x00 4.--6. " FR_RT_CNT ,Frame Retransmit Count Values 0 to 5," "0,1,2,3,4,5,?..."
textline " "
bitfld.long 0x00 2. " INV_ACK ,Invert ACK to Broadcast Commands" "Not inverted,Inverted"
bitfld.long 0x00 1. " ACKN_HEAD ,ACK/NACK Header Block" "ACK,NACK"
textline " "
bitfld.long 0x00 0. " CEC_SN ,CEC snoop" "Disabled,Enabled"
line.long 0x04 "CEC_TX_INIT,CEC Tx Initialization Register"
bitfld.long 0x04 0.--3. " CEC_INIT_ID ,CEC Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "CEC_TX_DEST,CEC Tx Destination Register"
bitfld.long 0x08 7. " CEC_SD_POLL ,Generate a polling message" "Not generated,Generated"
bitfld.long 0x08 0.--3. " CEC_DEST_ID ,CEC Destination ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x38++0x07
line.long 0x00 "CEC_SETUP,CEC Set Up Register"
bitfld.long 0x00 4. " CEC_PTRH ,CEC passthru register" "Low,High"
bitfld.long 0x00 2. " CEC_FORCE_NON_CALIB ,CEC force no calibration" "Not forced,Forced"
textline " "
bitfld.long 0x00 1. " CEC_CAL_EN ,CEC calibration enable register" "Disabled,Enabled"
bitfld.long 0x00 0. " CEC_CAL_SW ,CEC calibration SW" "Low,High"
line.long 0x04 "CEC_TX_COMMAND,CEC Tx Command Register"
hexmask.long.byte 0x04 0.--7. 1. " CEC_TX_COM ,CEC Tx command"
tree "CEC_TX_OPERAND"
group.long 0x40++0x03
line.long 0x00 "CEC_TX_OPERAND_0,CEC Tx Operand Register 0"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x44++0x03
line.long 0x00 "CEC_TX_OPERAND_1,CEC Tx Operand Register 1"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x48++0x03
line.long 0x00 "CEC_TX_OPERAND_2,CEC Tx Operand Register 2"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x4C++0x03
line.long 0x00 "CEC_TX_OPERAND_3,CEC Tx Operand Register 3"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x50++0x03
line.long 0x00 "CEC_TX_OPERAND_4,CEC Tx Operand Register 4"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x54++0x03
line.long 0x00 "CEC_TX_OPERAND_5,CEC Tx Operand Register 5"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x58++0x03
line.long 0x00 "CEC_TX_OPERAND_6,CEC Tx Operand Register 6"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x5C++0x03
line.long 0x00 "CEC_TX_OPERAND_7,CEC Tx Operand Register 7"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x60++0x03
line.long 0x00 "CEC_TX_OPERAND_8,CEC Tx Operand Register 8"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x64++0x03
line.long 0x00 "CEC_TX_OPERAND_9,CEC Tx Operand Register 9"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x68++0x03
line.long 0x00 "CEC_TX_OPERAND_10,CEC Tx Operand Register 10"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x6C++0x03
line.long 0x00 "CEC_TX_OPERAND_11,CEC Tx Operand Register 11"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x70++0x03
line.long 0x00 "CEC_TX_OPERAND_12,CEC Tx Operand Register 12"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x74++0x03
line.long 0x00 "CEC_TX_OPERAND_13,CEC Tx Operand Register 13"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
group.long 0x78++0x03
line.long 0x00 "CEC_TX_OPERAND_14,CEC Tx Operand Register 14"
hexmask.long.byte 0x00 0.--7. 1. " CEC_TX_OP ,CEC Tx Operand"
tree.end
textline " "
group.long 0x7C++0x03
line.long 0x00 "CEC_TRANSMIT_DATA,CEC Transmit Data Register"
bitfld.long 0x00 6. " TX_BFR_ACC ,Read back internal buffer contents from 0x8F-0x9E" "No,Yes"
bitfld.long 0x00 5. " TX_AUT_CALC ,Auto-Calculate TX_CNT and send" "No,Yes"
textline " "
bitfld.long 0x00 4. " TRA_CEC_CMD ,Send CEC Command and TX_CNT Operands" "No,Yes"
bitfld.long 0x00 0.--3. " TX_CNT ,Transmit Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x88++0x17
line.long 0x00 "CEC_CA_7_0,CEC Capture ID0 Register"
hexmask.long.byte 0x00 0.--7. 1. " CEC_CAP_ID ,The CEC Capture ID register is separate from the CEC Initiator ID"
line.long 0x04 "CEC_CA_15_8,CEC Capture ID0 Register"
hexmask.long.byte 0x04 0.--7. 1. " CEC_CAP_ID ,The CEC Capture ID register is separate from the CEC Initiator ID"
line.long 0x08 "CEC_INT_ENABLE_0,CEC Interrupt Enable Register0"
bitfld.long 0x08 5. " CEC_INTR1_MASK5 ,Tx: Transmit Buffer Full/Empty Change event" "Disabled,Enabled"
bitfld.long 0x08 2. " CEC_INTR1_MASK2 ,Transmitter FIFO Empty event" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " CEC_INTR1_MASK1 ,Receiver FIFO Not Empty event" "Disabled,Enabled"
bitfld.long 0x08 0. " CEC_INTR1_MASK0 ,Command Being Received event" "Disabled,Enabled"
line.long 0x0C "CEC_INT_ENABLE_1,CEC Interrupt Enable Register1"
bitfld.long 0x0C 3. " CEC_INTR2_MASK3 ,Rx FIFO Overrun Error event" "Disabled,Enabled"
bitfld.long 0x0C 2. " CEC_INTR2_MASK2 ,Short Pulse Detected event" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 1. " CEC_INTR2_MASK1 ,Frame Retransmit Count Exceeded event" "Disabled,Enabled"
bitfld.long 0x0C 0. " CEC_INTR2_MASK0 ,Start Bit Irregularity event" "Disabled,Enabled"
line.long 0x10 "CEC_INT_STATUS_0,CEC Interrupt Status Register0"
bitfld.long 0x10 7. " CEC_LSTAT ,CEC line current state" "Low,High"
bitfld.long 0x10 6. " TFIF_BFULL ,Tx FIFO Transmit Buffer Full" "Not full,Full"
textline " "
bitfld.long 0x10 5. " CEC_INTR1_STAT4 ,Tx: Transmit Buffer Full/Empty Change event Pending" "Not pending,Pending"
bitfld.long 0x10 2. " CEC_INTR1_STAT2 ,Transmitter FIFO Empty event pending" "Not pending,Pending"
textline " "
bitfld.long 0x10 1. " CEC_INTR1_STAT1 ,Receiver FIFO Not Empty event pending" "Not pending,Pending"
bitfld.long 0x10 0. " CEC_INTR1_STAT0 ,Command Being Received event pending" "Not pending,Pending"
line.long 0x14 "CEC_INT_STATUS_1,CEC Interrupt Status Register1"
bitfld.long 0x14 3. " CEC_INTR2_STAT3 ,Rx FIFO Overrun Error event" "Disabled,Enabled"
bitfld.long 0x14 2. " CEC_INTR2_STAT2 ,Short Pulse Detected event" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " CEC_INTR2_STAT1 ,Frame Retransmit Count Exceeded event" "Disabled,Enabled"
bitfld.long 0x14 0. " CEC_INTR2_STAT0 ,Start Bit Irregularity event" "Disabled,Enabled"
group.long 0xB0++0x03
line.long 0x00 "CEC_RX_CONTROL,CEC RX Control Register"
bitfld.long 0x00 1. " CLR_RX_FIF_ALL ,Clear All Frames from Rx FIFO" "Not cleared,Cleared"
bitfld.long 0x00 0. " CLR_RX_FIF_CUR ,Clear Current Frame from Rx FIFO" "Not cleared,Cleared"
rgroup.long 0xB4++0x07
line.long 0x00 "CEC_RX_COUNT,CEC Rx Count Register"
bitfld.long 0x00 7. " RX_ERROR ,Error associated with this message" "No error,Error"
bitfld.long 0x00 4.--6. " CEC_RX_CMD_CNT ,CEC Receive FIFO Frame Count" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 0.--3. " CEC_RX_BYTE_CNT ,CEC Receive Byte Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "CEC_RX_CMD_HEADER,CEC Rx Command Header Register"
bitfld.long 0x04 4.--7. " CEC_RX_INIT ,CEC Initiator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 0.--3. " CEC_RX_DEST ,CEC Destination ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xBC++0x03
line.long 0x00 "CEC_RX_COMMAND,CEC Rx Command Register"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_COM ,CEC Rx command"
tree "CEC_RX_OPERAND"
group.long 0xC0++0x03
line.long 0x00 "CEC_RX_OPERAND_0,CEC Rx Operand Register 0"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xC4++0x03
line.long 0x00 "CEC_RX_OPERAND_1,CEC Rx Operand Register 1"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xC8++0x03
line.long 0x00 "CEC_RX_OPERAND_2,CEC Rx Operand Register 2"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xCC++0x03
line.long 0x00 "CEC_RX_OPERAND_3,CEC Rx Operand Register 3"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xD0++0x03
line.long 0x00 "CEC_RX_OPERAND_4,CEC Rx Operand Register 4"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xD4++0x03
line.long 0x00 "CEC_RX_OPERAND_5,CEC Rx Operand Register 5"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xD8++0x03
line.long 0x00 "CEC_RX_OPERAND_6,CEC Rx Operand Register 6"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xDC++0x03
line.long 0x00 "CEC_RX_OPERAND_7,CEC Rx Operand Register 7"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xE0++0x03
line.long 0x00 "CEC_RX_OPERAND_8,CEC Rx Operand Register 8"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xE4++0x03
line.long 0x00 "CEC_RX_OPERAND_9,CEC Rx Operand Register 9"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xE8++0x03
line.long 0x00 "CEC_RX_OPERAND_10,CEC Rx Operand Register 10"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xEC++0x03
line.long 0x00 "CEC_RX_OPERAND_11,CEC Rx Operand Register 11"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xF0++0x03
line.long 0x00 "CEC_RX_OPERAND_12,CEC Rx Operand Register 12"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xF4++0x03
line.long 0x00 "CEC_RX_OPERAND_13,CEC Rx Operand Register 13"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
group.long 0xF8++0x03
line.long 0x00 "CEC_RX_OPERAND_14,CEC Rx Operand Register 14"
hexmask.long.byte 0x00 0.--7. 1. " CEC_RX_OP ,CEC Rx Operand"
tree.end
width 11.
tree.end
tree "HDMI_PHY (HDMI PHY Registers)"
base ad:0x48122000
width 26.
group.long 0x04++0x0B
line.long 0x00 "TMDS_CNTL2,TMDS Control Register"
bitfld.long 0x00 5. " OE ,Output enable control" "Disabled,Enabled"
bitfld.long 0x00 4. " TERM_EN ,Source termination enable control" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " CLKDETECT ,Clock detector output" "Clock < 2.5MHz,Clock > 2.5MHz"
bitfld.long 0x00 0. " RSEN ,Receiver sense output" "Disconnected,Connected"
line.long 0x04 "TMDS_CNTL3,TMDS Control Register"
bitfld.long 0x04 3.--4. " CLKMULT_CTL ,Clock multiplication factor control" "0.5x,1x,2x,4x"
bitfld.long 0x04 1.--2. " DPCOLOR_CTL ,Deep color mode control" "8bit,10bit,12bit,?..."
textline " "
bitfld.long 0x04 0. " PDB ,Powerdown Control" "Powered,Not powered"
line.long 0x08 "BIST_CNTL,BIST Control Register"
bitfld.long 0x08 0. " ENC_BYP ,Bypass the DVI encoder" "Not bypassed,Bypassed"
group.long 0x20++0x03
line.long 0x00 "TMDS_CNTL9,TMDS Control Register"
bitfld.long 0x00 0. " TEN_BIT_BYPASS ,TEN bit bypass" "Not bypassed,Bypassed"
width 0xb
tree.end
tree.end
endif
tree.open "I2C (Inter Integrated Circuit)"
tree "I2C 0"
base ad:0x48028000
width 22.
rgroup.long 0x00++0x07
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "I2C_SYSC,System Configuration Register"
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
textline " "
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
textline " "
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
width 22.
sif (!cpuis("AM335*"))
wgroup.long 0x20++0x03
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
endif
group.long 0x24++0x03
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
else
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
endif
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
textline " "
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
textline " "
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
textline " "
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
textline " "
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
group.long 0x28++0x0b
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
else
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
endif
textline " "
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
textline " "
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
textline " "
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
textline " "
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
else
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
endif
group.long 0x34++0x1b
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
width 22.
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
else
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
endif
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
else
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
endif
width 22.
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
group.long 0x90++0x0b
line.long 0x00 "I2C_SYSS,System Status Register"
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline " "
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "I2C_CNT,Data Counter Register"
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
hgroup.long 0x9C++0x03
hide.long 0x00 "I2C_DATA,Data Access Register"
in
width 22.
if (((d.l(ad:0x48028000+0xa4))&0x400)==0x400)
group.long 0xA4++0x03
line.long 0x00 "I2C_CON,I2C Configuration Register"
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
textline " "
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
textline " "
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
textline " "
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
textline " "
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
textline " "
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
textline " "
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
else
group.long 0xA4++0x03
line.long 0x00 "I2C_CON,I2C Configuration Register"
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
textline " "
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
textline " "
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
endif
width 22.
if (((d.l(ad:0x48028000+0xa4))&0x80)==0x80)
group.long 0xA8++0x03
line.long 0x00 "I2C_OA,I2C Own Address Register"
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
else
group.long 0xA8++0x03
line.long 0x00 "I2C_OA,I2C Own Address Register"
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
endif
if (((d.l(ad:0x48028000+0xa4))&0x100)==0x100)
group.long 0xAC++0x03
line.long 0x00 "I2C_SA,Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
else
group.long 0xAC++0x03
line.long 0x00 "I2C_SA,Slave Address Register"
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
endif
group.long 0xB0++0x03
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
if (((d.l(ad:0x48028000+0xa4))&0x400)==0x400)
group.long 0xB4++0x07
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
else
hgroup.long 0xB4++0x07
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
endif
group.long 0xBC++0x03
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
textline " "
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
textline " "
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
textline " "
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
textline " "
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
else
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
textline " "
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
textline " "
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
textline " "
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
endif
rgroup.long 0xc0++0x03
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((d.l(ad:0x48028000+0xa4))&0x40)==0x00)
group.long 0xC4++0x03
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
else
group.long 0xC4++0x03
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
endif
if (((d.l(ad:0x48028000+0xa4))&0x20)==0x00)
group.long 0xC8++0x03
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
else
group.long 0xC8++0x03
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
endif
if (((d.l(ad:0x48028000+0xa4))&0x10)==0x00)
group.long 0xCC++0x03
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
else
group.long 0xCC++0x03
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
endif
rgroup.long 0xD0++0x03
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
group.long 0xD4++0x03
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
textline " "
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
width 0xb
tree.end
tree "I2C 1"
base ad:0x4802a000
width 22.
rgroup.long 0x00++0x07
line.long 0x00 "I2C_REVNB_LO,Module Revision Register (LOW BYTES)"
bitfld.long 0x00 11.--15. " RTL ,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " MINOR ,Minor Revision"
line.long 0x04 "I2C_REVNB_HI,Module Revision Register (HIGH BYTES)"
bitfld.long 0x04 14.--15. " SCHEME ,Distinguish between old Scheme and current" "0,1,2,3"
hexmask.long.word 0x04 0.--11. 1. " FUNC ,Indicates a software compatible module family"
group.long 0x10++0x03
line.long 0x00 "I2C_SYSC,System Configuration Register"
bitfld.long 0x00 8.--9. " CLKACTIVITY ,Clock Activity selection bits" "Both off,Ocp on,Sys on,Both on"
bitfld.long 0x00 3.--4. " IDLEMODE ,Idle Mode selection bits" "Force idle,No idle,Smart idle,Smartidle_wakeup"
textline " "
bitfld.long 0x00 2. " ENAWAKEUP ,Enable Wakeup control bit" "Disabled,Enabled"
bitfld.long 0x00 1. " SRST ,SoftReset bit" "Normal,Reset"
textline " "
bitfld.long 0x00 0. " AUTOIDLE ,Autoidle bit" "Disabled,Enabled"
width 22.
sif (!cpuis("AM335*"))
wgroup.long 0x20++0x03
line.long 0x00 "I2C_EOI,I2C End of Interrupt Register"
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "Disabled,Enabled"
endif
group.long 0x24++0x03
line.long 0x00 "I2C_IRQSTATUS_RAW,I2C Status Raw Register"
bitfld.long 0x00 14. " XDR ,Transmit draining IRQ status" "Disabled,Enabled"
bitfld.long 0x00 13. " RDR ,Receive draining IRQ status" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
else
bitfld.long 0x00 12. " BB ,Bus busy status" "Not busy,Busy"
endif
bitfld.long 0x00 11. " ROVR ,Receive overrun status" "Normal,Received"
textline " "
bitfld.long 0x00 10. " XUDF ,Transmit underflow status" "No underflow,Underflow"
bitfld.long 0x00 9. " AAS ,Address recognized as slave IRQ status" "No action,Recognized"
textline " "
bitfld.long 0x00 8. " BF ,Bus Free IRQ status" "No action,Free"
bitfld.long 0x00 7. " AERR ,Access Error IRQ status" "No action,Error"
textline " "
bitfld.long 0x00 6. " STC ,Start Condition IRQ status" "No action,Detected"
eventfld.long 0x00 5. " GC ,General call IRQ status" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ status" "Not ready,Ready"
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ status" "Not ready,Ready"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ status" "Not ready,Ready"
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ status" "Normal,Detected"
textline " "
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ status" "Normal,Detected"
group.long 0x28++0x0b
line.long 0x00 "I2C_IRQSTATUS,I2C Status Register"
eventfld.long 0x00 14. " XDR ,Transmit draining IRQ enabled status" "Disabled,Enabled"
eventfld.long 0x00 13. " RDR ,Receive draining IRQ enabled status" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " BB ,Bus busy enabled status" "Not busy,Busy"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
bitfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
else
eventfld.long 0x00 11. " ROVR ,Receive overrun enabled status" "Normal,Received"
endif
textline " "
eventfld.long 0x00 10. " XUDF ,Transmit underflow enabled status" "No underflow,Underflow"
eventfld.long 0x00 9. " AAS ,Address recognized as slave IRQ enabled status" "No action,Recognized"
textline " "
eventfld.long 0x00 8. " BF ,Bus Free IRQ enabled status" "No action,Free"
eventfld.long 0x00 7. " AERR ,Access Error IRQ enabled status" "No action,Error"
textline " "
eventfld.long 0x00 6. " STC ,Start Condition IRQ enabled status" "No action,Detected"
eventfld.long 0x00 5. " GC ,General call IRQ enabled status" "Not detected,Detected"
textline " "
eventfld.long 0x00 4. " XRDY ,Transmit data ready IRQ enabled status" "Not ready,Ready"
eventfld.long 0x00 3. " RRDY ,Receive data ready IRQ enabled status" "Not ready,Ready"
textline " "
eventfld.long 0x00 2. " ARDY ,Register access ready IRQ enabled status" "Not ready,Ready"
eventfld.long 0x00 1. " NACK ,No acknowledgement IRQ enabled status" "Normal,Detected"
textline " "
eventfld.long 0x00 0. " AL ,Arbitration lost IRQ enabled status" "Normal,Detected"
line.long 0x04 "I2C_IRQENABLE_SET,I2C Interrupt Enable Set Register"
bitfld.long 0x04 14. " XDR_IE ,Transmit draining IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 13. " RDR_IE ,Receive draining IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " ROVR ,Receive overrun enable set" "Disabled,Enabled"
bitfld.long 0x04 10. " XUDF ,Transmit underflow enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " AAS_IE ,Address recognized as slave IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 8. " BF_IE ,Bus Free IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " AERR_IE ,Access Error IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 6. " STC_IE ,Start Condition IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " GC_IE ,General call IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 4. " XRDY_IE ,Transmit data ready IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RRDY_IE ,Receive data ready IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 2. " ARDY_IE ,Register access ready IRQ enable set" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " NACK_IE ,No acknowledgement IRQ enable set" "Disabled,Enabled"
bitfld.long 0x04 0. " AL_IE ,Arbitration lost IRQ enable set" "Disabled,Enabled"
line.long 0x08 "I2C_IRQENABLE_CLR,I2C Interrupt Enable Clear Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpuis("AM335*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")
bitfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
bitfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
bitfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
else
eventfld.long 0x08 14. " XDR_IE ,Transmit draining IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 13. " RDR_IE ,Receive draining IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 11. " ROVR ,Receive overrun enable clear" "Disabled,Enabled"
eventfld.long 0x08 10. " XUDF ,Transmit underflow enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 9. " AAS_IE ,Address recognized as slave IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 8. " BF_IE ,Bus Free IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 7. " AERR_IE ,Access Error IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 6. " STC_IE ,Start Condition IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 5. " GC_IE ,General call IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 4. " XRDY_IE ,Transmit data ready IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 3. " RRDY_IE ,Receive data ready IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 2. " ARDY_IE ,Register access ready IRQ enable clear" "Disabled,Enabled"
textline " "
eventfld.long 0x08 1. " NACK_IE ,No acknowledgement IRQ enable clear" "Disabled,Enabled"
eventfld.long 0x08 0. " AL_IE ,Arbitration lost IRQ enable clear" "Disabled,Enabled"
endif
group.long 0x34++0x1b
line.long 0x00 "I2C_WE,I2C Wakeup Enable Register"
bitfld.long 0x00 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x00 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x00 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x00 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
width 22.
line.long 0x04 "I2C_DMARXENABLE_SET,Receive DMA Enable Set Register"
bitfld.long 0x04 0. " DMARX_ENABLE_SET ,Receive DMA channel enable set" "Disabled,Enabled"
line.long 0x08 "I2C_DMATXENABLE_SET,Transmit DMA Enable Set Register"
bitfld.long 0x08 0. " DMATX_ENABLE_SET ,Transmit DMA channel enable set" "Disabled,Enabled"
line.long 0x0c "I2C_DMARXENABLE_CLR,Receive DMA Enable Clear Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
else
eventfld.long 0x0c 0. " DMARX_ENABLE_CLEAR ,Receive DMA channel enable clear" "No effect,Clear"
endif
line.long 0x10 "I2C_DMATXENABLE_CLR,Transmit DMA Enable Clear Register"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
else
eventfld.long 0x10 0. " DMATX_ENABLE_CLEAR ,Transmit DMA channel enable clear" "No effect,Clear"
endif
width 22.
line.long 0x14 "I2C_DMARXWAKE_EN,Receive DMA Wakeup Register"
bitfld.long 0x14 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x14 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x14 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x14 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
line.long 0x18 "I2C_DMATXWAKE_EN,Transmit DMA Wakeup Register"
bitfld.long 0x18 14. " XDR ,Transmit Draining wakeup set" "Disabled,Enabled"
bitfld.long 0x18 13. " RDR ,Receive Draining wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 11. " ROVR ,Receive overrun wakeup set" "Disabled,Enabled"
bitfld.long 0x18 10. " XUDF ,Transmit underflow wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 9. " AAS ,Address as slave IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 8. " BF ,Bus Free IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 6. " STC ,Start Condition IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 5. " GC ,General call IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 3. " DRDY ,Receive/Transmit data ready IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 2. " ARDY ,Register access ready IRQ wakeup set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 1. " NACK ,No acknowledgment IRQ wakeup set" "Disabled,Enabled"
bitfld.long 0x18 0. " AL ,Arbitration lost IRQ wakeup set" "Disabled,Enabled"
group.long 0x90++0x0b
line.long 0x00 "I2C_SYSS,System Status Register"
bitfld.long 0x00 0. " RDONE ,Reset done bit" "Ongoing,Completed"
line.long 0x04 "I2C_BUF,Buffer Configuration Register"
bitfld.long 0x04 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RXFIFO_CLR ,Receive FIFO clear" "Normal,Reset"
textline " "
hexmask.long.byte 0x04 8.--13. 1. " RXTRSH ,Threshold value for FIFO buffer in RX mode"
bitfld.long 0x04 7. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " TXFIFO_CLR ,Transmit FIFO clear" "Normal,Reset"
bitfld.long 0x04 0.--5. " TXTRSH ,Threshold value for FIFO buffer in TX mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "I2C_CNT,Data Counter Register"
hexmask.long.word 0x08 0.--15. 1. " DCOUNT ,Data count (Master mode only)"
hgroup.long 0x9C++0x03
hide.long 0x00 "I2C_DATA,Data Access Register"
in
width 22.
if (((d.l(ad:0x4802a000+0xa4))&0x400)==0x400)
group.long 0xA4++0x03
line.long 0x00 "I2C_CON,I2C Configuration Register"
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
textline " "
bitfld.long 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
textline " "
bitfld.long 0x00 9. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
textline " "
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
textline " "
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
textline " "
bitfld.long 0x00 1. " STP ,Stop condition" "No action/stop detected,Stop queried"
textline " "
bitfld.long 0x00 0. " STT ,Start condition" "No action/start detected,Start queried"
else
group.long 0xA4++0x03
line.long 0x00 "I2C_CON,I2C Configuration Register"
bitfld.long 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " OPMODE ,Operation mode selection" "Fast/Standard,?..."
textline " "
bitfld.long 0x00 10. " MST ,Master/slave mode" "Slave,Master"
bitfld.long 0x00 8. " XSA ,Expand Slave address" "7-bit,10-bit"
textline " "
bitfld.long 0x00 7. " XOA0 ,Expand Own address 0" "7-bit,10-bit"
bitfld.long 0x00 6. " XOA1 ,Expand Own address 1" "7-bit,10-bit"
textline " "
bitfld.long 0x00 5. " XOA2 ,Expand Own address 2" "7-bit,10-bit"
bitfld.long 0x00 4. " XOA3 ,Expand Own address 3" "7-bit,10-bit"
endif
width 22.
if (((d.l(ad:0x4802a000+0xa4))&0x80)==0x80)
group.long 0xA8++0x03
line.long 0x00 "I2C_OA,I2C Own Address Register"
hexmask.long.word 0x00 0.--9. 1. " OA ,Own address"
else
group.long 0xA8++0x03
line.long 0x00 "I2C_OA,I2C Own Address Register"
hexmask.long.byte 0x00 0.--6. 1. " OA ,Own address"
endif
if (((d.l(ad:0x4802a000+0xa4))&0x100)==0x100)
group.long 0xAC++0x03
line.long 0x00 "I2C_SA,Slave Address Register"
hexmask.long.word 0x00 0.--9. 1. " SA ,Slave address"
else
group.long 0xAC++0x03
line.long 0x00 "I2C_SA,Slave Address Register"
hexmask.long.byte 0x00 0.--6. 1. " SA ,Slave address"
endif
group.long 0xB0++0x03
line.long 0x00 "I2C_PSC,I2C Clock Prescaler Register"
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Fast/Standard mode prescale sampling clock divider value"
if (((d.l(ad:0x4802a000+0xa4))&0x400)==0x400)
group.long 0xB4++0x07
line.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
hexmask.long.byte 0x00 0.--7. 1. " SCLL ,Fast/Standard mode SCL low time"
line.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
hexmask.long.byte 0x04 0.--7. 1. " SCLH ,Fast/Standard mode SCL high time"
else
hgroup.long 0xB4++0x07
hide.long 0x00 "I2C_SCLL,I2C SCL Low Time Register"
hide.long 0x04 "I2C_SCLH,I2C SCL High Time Register"
endif
group.long 0xBC++0x03
line.long 0x00 "I2C_SYSTEST,I2C System Test Register"
bitfld.long 0x00 15. " ST_EN ,System test enable" "Disabled,Enabled"
bitfld.long 0x00 14. " FREE ,Free running mode" "Stop,Free"
textline " "
bitfld.long 0x00 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test,Loopback"
bitfld.long 0x00 11. " SSB ,Set status bit" "No action,Set"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
rbitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
textline " "
rbitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
rbitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
textline " "
rbitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
rbitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
textline " "
rbitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
rbitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
else
bitfld.long 0x00 8. " SCL_I_FUNC ,SCL line input value" "Low,High"
bitfld.long 0x00 7. " SCL_O_FUNC ,SCL line output value" "Low,High"
textline " "
bitfld.long 0x00 6. " SDA_I_FUNC ,SDA line input value" "Low,High"
bitfld.long 0x00 5. " SDA_O_FUNC ,SDA line output value" "Low,High"
textline " "
bitfld.long 0x00 3. " SCL_I ,SCL line sense input value" "Low,High"
bitfld.long 0x00 2. " SCL_O ,SCL line drive output value" "Low,High"
textline " "
bitfld.long 0x00 1. " SDA_I ,SDA line sense input value" "Low,High"
bitfld.long 0x00 0. " SDA_O ,SDA line drive output value" "Low,High"
endif
rgroup.long 0xc0++0x03
line.long 0x00 "I2C_BUFSTAT,I2C Buffer Status Register"
bitfld.long 0x00 14.--15. " FIFODEPTH ,Internal FIFO buffers depth" "8-bytes,16-bytes,32-bytes,64-bytes"
bitfld.long 0x00 8.--13. " RXSTAT ,RX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 0.--5. " TXSTAT ,TX Buffer Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
if (((d.l(ad:0x4802a000+0xa4))&0x40)==0x00)
group.long 0xC4++0x03
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA1 ,Own address 1"
else
group.long 0xC4++0x03
line.long 0x00 "I2C_OA1,I2C Own Address 1 Register"
hexmask.long.word 0x00 0.--9. 1. " OA1 ,Own address 1"
endif
if (((d.l(ad:0x4802a000+0xa4))&0x20)==0x00)
group.long 0xC8++0x03
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA2 ,Own address 2"
else
group.long 0xC8++0x03
line.long 0x00 "I2C_OA2,I2C Own Address 2 Register"
hexmask.long.word 0x00 0.--9. 1. " OA2 ,Own address 2"
endif
if (((d.l(ad:0x4802a000+0xa4))&0x10)==0x00)
group.long 0xCC++0x03
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.byte 0x00 0.--6. 1. " OA3 ,Own address 3"
else
group.long 0xCC++0x03
line.long 0x00 "I2C_OA3,I2C Own Address 3 Register"
hexmask.long.word 0x00 0.--9. 1. " OA3 ,Own address 3"
endif
rgroup.long 0xD0++0x03
line.long 0x00 "I2C_ACTOA,I2C Active Own Address Register"
bitfld.long 0x00 3. " OA3_ACT ,Own Address 3 active" "Inactive,Active"
bitfld.long 0x00 2. " OA2_ACT ,Own Address 2 active" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " OA1_ACT ,Own Address 1 active" "Inactive,Active"
bitfld.long 0x00 0. " OA0_ACT ,Own Address 0 active" "Inactive,Active"
group.long 0xD4++0x03
line.long 0x00 "I2C_SBLOCK,I2C Clock Blocking Enable Register"
bitfld.long 0x00 3. " OA3_EN ,Enable I2C Clock Blocking for Own Address 3" "Released,Blocked"
bitfld.long 0x00 2. " OA2_EN ,Enable I2C Clock Blocking for Own Address 2" "Released,Blocked"
textline " "
bitfld.long 0x00 1. " OA1_EN ,Enable I2C Clock Blocking for Own Address 1" "Released,Blocked"
bitfld.long 0x00 0. " OA0_EN ,Enable I2C Clock Blocking for Own Address 0" "Released,Blocked"
width 0xb
tree.end
tree.end
sif (cpu()=="AM3892"||cpu()=="AM3894"||cpu()=="C6A8167"||cpu()=="C6A8168"||cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
tree "INTC (Interrupt Controller)"
base ad:0x48200000
width 21.
rgroup.long 0x000++0x03
line.long 0x00 "INTCPS_REVISION,Revision Register"
hexmask.long.byte 0x00 4.--7. 1. " MAJOR ,Major revision"
hexmask.long.byte 0x00 0.--3. 1. " MINOR ,Manor revision"
group.long 0x010++0x03
line.long 0x00 "INTCPS_SYSCONFIG,Configuration Register"
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No effect,Reset"
bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Free-running,AutoClkGate"
rgroup.long 0x014++0x03
line.long 0x00 "INTCPS_SYSSTATUS,Status Register"
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.long 0x040++0x07
line.long 0x00 "INTCPS_SIR_IRQ,Active IRQ Interrupt Number Register"
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQ ,Spurious IRQ flag"
hexmask.long.byte 0x00 0.--6. 1. " ACTIVEIRQ ,Active IRQ number"
line.long 0x04 "INTCPS_SIR_FIQ,Active FIQ Interrupt Number Register"
hexmask.long 0x04 7.--31. 1. " SPURIOUSFIQ ,Spurious FIQ flag"
hexmask.long.byte 0x04 0.--6. 1. " ACTIVEFIQ ,Active FIQ number"
wgroup.long 0x048++0x03
line.long 0x00 "INTCPS_CONTROL,Control Register"
bitfld.long 0x00 1. " NEWFIQAGR ,Reset FIQ output and enable new FIQ generation" "No effect,Reset/new FIQ"
bitfld.long 0x00 0. " NEWIRQAGR ,New IRQ generation" "No effect,Reset/new IRQ"
group.long 0x04C++0x07
line.long 0x00 "INTCPS_PROTECTION,Protection Register"
bitfld.long 0x00 0. " PROTECTION ,Protection mode" "Disabled,Enabled"
line.long 0x04 "INTCPS_IDLE,Idle Register"
bitfld.long 0x04 1. " TURBO ,Input synchroniser clock auto-gating" "Free-running,Auto-gated"
bitfld.long 0x04 0. " FUNCIDLE ,Functional clock auto-idle mode" "Auto-gated,Free-running"
rgroup.long 0x060++0x07
line.long 0x00 "INTCPS_IRQ_PRIORITY,IRQ Priority Register"
hexmask.long 0x00 7.--31. 1. " SPURIOUSIRQFLAG ,Spurious IRQ flag"
hexmask.long.byte 0x00 0.--6. 1. " IRQPRIORITY ,Current IRQ priority"
line.long 0x04 "INTCPS_FIQ_PRIORITY,FIQ Priority Register"
hexmask.long 0x04 7.--31. 1. " SPURIOUSFIQFLAG ,Spurious FIQ flag"
hexmask.long.byte 0x04 0.--6. 1. " FIQPRIORITY ,Current FIQ priority"
group.long 0x068++0x03
line.long 0x00 "INTCPS_THRESHOLD,Priority Threshold Register"
hexmask.long.byte 0x00 0.--7. 1. " PRIORITYTHRESHOLD ,Priority threshold"
width 21.
tree "Interrupts 0-31"
rgroup.long 0x080++0x03
line.long 0x00 "INTCPS_ITR0,Raw Interrupt Input Status Register 0"
bitfld.long 0x00 19. " USBINT1 ,USB1 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " USBINT0 ,USB0 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " USBSSINT ,USB Subsystem Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " SATAINT ,SATA Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 14. " EDMAERRINT ,EDMA CC Error Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 13. " EDMAMPERR ,EDMA Memory Protection Error Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 12. " EDMACOMPINT ,EDMA CC Completion Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " L3APPINT ,L3 Interconnect Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " L3DEBUG ,L3 Interconnect Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 7. " NMI ,NMIn Pin Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " ELM_IRQ ,ELM Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 3. " BENCH ,Cortex-A8 Emulation Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 2. " COMMRX ,Cortex-A8 Emulation Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " COMMTX ,Cortex-A8 Emulation Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " EMUINT ,Cortex-A8 Emulation Raw Interrupt Status" "No interrupt,Interrupt"
group.long 0x084++0x03
line.long 0x00 "INTCPS_MIR0_set/clr,Interrupt Mask Register 0"
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " USBINT1_set/clr ,USB1 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " USBINT0_set/clr ,USB0 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " USBSSINT_set/clr ,USB Subsystem Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " SATAINT_set/clr ,SATA Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " EDMAERRINT_set/clr ,EDMA CC Error Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " EDMAMPERR_set/clr ,EDMA Memory Protection Error Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " EDMACOMPINT_set/clr ,EDMA CC Completion Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " L3APPINT_set/clr ,L3 Interconnect Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " L3DEBUG_set/clr ,L3 Interconnect Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " NMI_set/clr ,NMIn Pin Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " ELM_IRQ_set/clr ,ELM Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " BENCH_set/clr ,Cortex-A8 Emulation Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " COMMRX_set/clr ,Cortex-A8 Emulation Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " COMMTX_set/clr ,Cortex-A8 Emulation Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " EMUINT_set/clr ,Cortex-A8 Emulation Interrupt Mask" "Not masked,Masked"
group.long 0x090++0x03
line.long 0x00 "INTCPS_ISR0_set/clr,Software Interrupt Register 0"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " USBINT1_set/clr ,USB1 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " USBINT0_set/clr ,USB0 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " USBSSINT_set/clr ,USB Subsystem Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " SATAINT_set/clr ,SATA Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " EDMAERRINT_set/clr ,EDMA CC Error Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " EDMAMPERR_set/clr ,EDMA Memory Protection Error Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " EDMACOMPINT_set/clr ,EDMA CC Completion Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " L3APPINT_set/clr ,L3 Interconnect Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " L3DEBUG_set/clr ,L3 Interconnect Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " NMI_set/clr ,NMIn Pin Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " ELM_IRQ_set/clr ,ELM Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " BENCH_set/clr ,Cortex-A8 Emulation Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " COMMRX_set/clr ,Cortex-A8 Emulation Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " COMMTX_set/clr ,Cortex-A8 Emulation Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " EMUINT_set/clr ,Cortex-A8 Emulation Interrupt" "No interrupt,Interrupt"
rgroup.long 0x098++0x03
line.long 0x00 "INTCPS_PENDING0_IRQ,IRQ Status Register 0"
bitfld.long 0x00 19. " USBINT1 ,USB1 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " USBINT0 ,USB0 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " USBSSINT ,USB Subsystem IRQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " SATAINT ,SATA IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 14. " EDMAERRINT ,EDMA CC Error IRQ Status" "Not requested,Requested"
bitfld.long 0x00 13. " EDMAMPERR ,EDMA Memory Protection Error IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 12. " EDMACOMPINT ,EDMA CC Completion IRQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " L3APPINT ,L3 Interconnect IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " L3DEBUG ,L3 Interconnect IRQ Status" "Not requested,Requested"
bitfld.long 0x00 7. " NMI ,NMIn Pin IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 4. " ELM_IRQ ,ELM IRQ Status" "Not requested,Requested"
bitfld.long 0x00 3. " BENCH ,Cortex-A8 Emulation IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " COMMRX ,Cortex-A8 Emulation IRQ Status" "Not requested,Requested"
bitfld.long 0x00 1. " COMMTX ,Cortex-A8 Emulation IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 0. " EMUINT ,Cortex-A8 Emulation IRQ Status" "Not requested,Requested"
rgroup.long 0x09C++0x03
line.long 0x00 "INTCPS_PENDING0_FIQ,FIQ Status Register 0"
bitfld.long 0x00 19. " USBINT1 ,USB1 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " USBINT0 ,USB0 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " USBSSINT ,USB Subsystem FIQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " SATAINT ,SATA FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 14. " EDMAERRINT ,EDMA CC Error FIQ Status" "Not requested,Requested"
bitfld.long 0x00 13. " EDMAMPERR ,EDMA Memory Protection Error FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 12. " EDMACOMPINT ,EDMA CC Completion FIQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " L3APPINT ,L3 Interconnect FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " L3DEBUG ,L3 Interconnect FIQ Status" "Not requested,Requested"
bitfld.long 0x00 7. " NMI ,NMIn Pin FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 4. " ELM_IRQ ,ELM FIQ Status" "Not requested,Requested"
bitfld.long 0x00 3. " BENCH ,Cortex-A8 Emulation FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " COMMRX ,Cortex-A8 Emulation FIQ Status" "Not requested,Requested"
bitfld.long 0x00 1. " COMMTX ,Cortex-A8 Emulation FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 0. " EMUINT ,Cortex-A8 Emulation FIQ Status" "Not requested,Requested"
tree.end
tree "Interrupts 32-63"
rgroup.long 0x0a0++0x03
line.long 0x00 "INTCPS_ITR1,Raw Interrupt Input Status Register 1"
bitfld.long 0x00 19. " PCIINT3 ,PCIe Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " PCIINT2 ,PCIe Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " PCIINT1 ,PCIe Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " PCIINT0 ,PCIe Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " MACMISC1 ,CPGMAC1 Miscellaneous Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 14. " MACTXINT1 ,CPGMAC1 Transmit Pending Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " MACRXINT1 ,CPGMAC1 Receive Pending Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " MACRXTHR1 ,CPGMAC1 Receive Threshold Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " MACMISC0 ,CPGMAC0 Miscellaneous Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " MACTXINT0 ,CPGMAC0 Transmit Pending Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " MACRXINT0 ,CPGMAC0 Receive Pending Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " MACRXTHR0 ,CPGMAC0 Receive Threshold Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 6. " HDMIINT ,HDMIINT Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
bitfld.long 0x00 5. " GFXINT ,SGX530 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
endif
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 4. " DSSINT ,DSSINT Raw Interrupt Status" "No interrupt,Interrupt"
else
bitfld.long 0x00 4. " HDVPSSINT ,HDVPSS Raw Interrupt Status" "No interrupt,Interrupt"
endif
bitfld.long 0x00 3. " PCIEWAKEUP ,PCIe Wakeup Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 2. " USBWAKEUP ,USB Subsystem Wakeup Raw Interrupt Status" "No interrupt,Interrupt"
group.long 0x0a4++0x03
line.long 0x00 "INTCPS_MIR1_set/clr,Interrupt Mask Register 1"
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " PCIINT3_set/clr ,PCIe Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " PCIINT2_set/clr ,PCIe Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " PCIINT1_set/clr ,PCIe Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " PCIINT0_set/clr ,PCIe Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " MACMISC1_set/clr ,CPGMAC1 Miscellaneous Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " MACTXINT1_set/clr ,CPGMAC1 Transmit Pending Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " MACRXINT1_set/clr ,CPGMAC1 Receive Pending Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " MACRXTHR1_set/clr ,CPGMAC1 Receive Threshold Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " MACMISC0_set/clr ,CPGMAC0 Miscellaneous Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " MACTXINT0_set/clr ,CPGMAC0 Transmit Pending Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " MACRXINT0_set/clr ,CPGMAC0 Receive Pending Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MACRXTHR0_set/clr ,CPGMAC0 Receive Threshold Interrupt Mask" "Not masked,Masked"
textline " "
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " HDMIINT_set/clr ,HDMIINT Interrupt Mask" "Not masked,Masked"
textline " "
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " GFXINT_set/clr ,SGX530 Interrupt Mask" "Not masked,Masked"
textline " "
endif
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " DSSINT_set/clr ,DSSINT Interrupt Mask" "Not masked,Masked"
else
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " HDVPSSINT_set/clr ,HDVPSS Interrupt Mask" "Not masked,Masked"
endif
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " PCIEWAKEUP_set/clr ,PCIe Wakeup Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " USBWAKEUP_set/clr ,USB Subsystem Wakeup Interrupt Mask" "Not masked,Masked"
group.long 0x0b0++0x03
line.long 0x00 "INTCPS_ISR1_set/clr,Software Interrupt Register 1"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " PCIINT3_set/clr ,PCIe Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " PCIINT2_set/clr ,PCIe Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " PCIINT1_set/clr ,PCIe Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " PCIINT0_set/clr ,PCIe Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " MACMISC1_set/clr ,CPGMAC1 Miscellaneous Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " MACTXINT1_set/clr ,CPGMAC1 Transmit Pending Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " MACRXINT1_set/clr ,CPGMAC1 Receive Pending Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " MACRXTHR1_set/clr ,CPGMAC1 Receive Threshold Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " MACMISC0_set/clr ,CPGMAC0 Miscellaneous Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " MACTXINT0_set/clr ,CPGMAC0 Transmit Pending Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " MACRXINT0_set/clr ,CPGMAC0 Receive Pending Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " MACRXTHR0_set/clr ,CPGMAC0 Receive Threshold Interrupt" "No interrupt,Interrupt"
textline " "
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " HDMIINT_set/clr ,HDMIINT Interrupt" "No interrupt,Interrupt"
textline " "
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " GFXINT_set/clr ,SGX530 Interrupt" "No interrupt,Interrupt"
textline " "
endif
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " DSSINT_set/clr ,DSSINT Interrupt" "No interrupt,Interrupt"
else
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " HDVPSSINT_set/clr ,HDVPSS Interrupt" "No interrupt,Interrupt"
endif
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " PCIEWAKEUP_set/clr ,PCIe Wakeup Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " USBWAKEUP_set/clr ,USB Subsystem Wakeup Interrupt" "No interrupt,Interrupt"
rgroup.long 0x0b8++0x03
line.long 0x00 "INTCPS_PENDING1_IRQ,IRQ Status Register 1"
bitfld.long 0x00 19. " PCIINT3 ,PCIe IRQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " PCIINT2 ,PCIe IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " PCIINT1 ,PCIe IRQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " PCIINT0 ,PCIe IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " MACMISC1 ,CPGMAC1 Miscellaneous IRQ Status" "Not requested,Requested"
bitfld.long 0x00 14. " MACTXINT1 ,CPGMAC1 Transmit Pending IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " MACRXINT1 ,CPGMAC1 Receive Pending IRQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " MACRXTHR1 ,CPGMAC1 Receive Threshold IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " MACMISC0 ,CPGMAC0 Miscellaneous IRQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " MACTXINT0 ,CPGMAC0 Transmit Pending IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " MACRXINT0 ,CPGMAC0 Receive Pending IRQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " MACRXTHR0 ,CPGMAC0 Receive Threshold IRQ Status" "Not requested,Requested"
textline " "
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 6. " HDMIINT ,HDMIINT IRQ Status" "Not requested,Requested"
textline " "
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
bitfld.long 0x00 5. " GFXINT ,SGX530 IRQ Status" "Not requested,Requested"
textline " "
endif
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 4. " DSSINT ,DSSINT IRQ Status" "Not requested,Requested"
else
bitfld.long 0x00 4. " HDVPSSINT ,HDVPSS IRQ Status" "Not requested,Requested"
endif
bitfld.long 0x00 3. " PCIEWAKEUP ,PCIe Wakeup IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " USBWAKEUP ,USB Subsystem Wakeup IRQ Status" "Not requested,Requested"
rgroup.long 0x0bC++0x03
line.long 0x00 "INTCPS_PENDING1_FIQ,FIQ Status Register 1"
bitfld.long 0x00 19. " PCIINT3 ,PCIe FIQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " PCIINT2 ,PCIe FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " PCIINT1 ,PCIe FIQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " PCIINT0 ,PCIe FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 15. " MACMISC1 ,CPGMAC1 Miscellaneous FIQ Status" "Not requested,Requested"
bitfld.long 0x00 14. " MACTXINT1 ,CPGMAC1 Transmit Pending FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " MACRXINT1 ,CPGMAC1 Receive Pending FIQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " MACRXTHR1 ,CPGMAC1 Receive Threshold FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " MACMISC0 ,CPGMAC0 Miscellaneous FIQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " MACTXINT0 ,CPGMAC0 Transmit Pending FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " MACRXINT0 ,CPGMAC0 Receive Pending FIQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " MACRXTHR0 ,CPGMAC0 Receive Threshold FIQ Status" "Not requested,Requested"
textline " "
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 6. " HDMIINT ,HDMIINT FIQ Status" "Not requested,Requested"
textline " "
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="DM8166"||cpu()=="DM8168")
bitfld.long 0x00 5. " GFXINT ,SGX530 FIQ Status" "Not requested,Requested"
textline " "
endif
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
bitfld.long 0x00 4. " DSSINT ,DSSINT FIQ Status" "Not requested,Requested"
else
bitfld.long 0x00 4. " HDVPSSINT ,HDVPSS FIQ Status" "Not requested,Requested"
endif
bitfld.long 0x00 3. " PCIEWAKEUP ,PCIe Wakeup FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 2. " USBWAKEUP ,USB Subsystem Wakeup FIQ Status" "Not requested,Requested"
tree.end
tree "Interrupts 64-95"
rgroup.long 0x0c0++0x03
line.long 0x00 "INTCPS_ITR2,Raw Interrupt Input Status Register 2"
bitfld.long 0x00 31. " TINT7 ,TIMER7 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 30. " TINT6 ,TIMER6 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 29. " TINT5 ,TIMER5 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 28. " TINT4 ,TIMER4 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " WDTINT ,Watchdog Timer Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 22. " MCBSPINT ,McBSP Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 21. " MCARXINT2 ,McASP2 Receive Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 20. " MCATXINT2 ,McASP2 Transmit Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " MCARXINT1 ,McASP1 Receive Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " MCATXINT1 ,McASP1 Transmit Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " MCARXINT0 ,McASP0 Receive Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " MCATXINT0 ,McASP0 Transmit Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " MBINT ,Mailbox Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " RTCALARMINT ,RTC Alarm Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " RTCINT ,RTC Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " UARTINT2 ,UART2 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " UARTINT1 ,UART1 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " UARTINT0 ,UART0 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " I2CINT1 ,I2C1 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " I2CINT0 ,I2C0 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " TINT3 ,TIMER3 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " TINT2 ,TIMER2 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " TINT1 ,TIMER1 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " SPIINT0 ,SPI0 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " SDINT0 ,MMC/SD0 Raw Interrupt Status" "No interrupt,Interrupt"
group.long 0x0c4++0x03
line.long 0x00 "INTCPS_MIR2_set/clr,Interrupt Mask Register 2"
setclrfld.long 0x00 31. 0x08 31. 0x04 31. " TINT7_set/clr ,TIMER7 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 30. 0x08 30. 0x04 30. " TINT6_set/clr ,TIMER6 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 29. 0x08 29. 0x04 29. " TINT5_set/clr ,TIMER5 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " TINT4_set/clr ,TIMER4 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " WDTINT_set/clr ,Watchdog Timer Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 22. 0x08 22. 0x04 22. " MCBSPINT_set/clr ,McBSP Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 21. 0x08 21. 0x04 21. " MCARXINT2_set/clr ,McASP2 Receive Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 20. 0x08 20. 0x04 20. " MCATXINT2_set/clr ,McASP2 Transmit Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " MCARXINT1_set/clr ,McASP1 Receive Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " MCATXINT1_set/clr ,McASP1 Transmit Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " MCARXINT0_set/clr ,McASP0 Receive Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " MCATXINT0_set/clr ,McASP0 Transmit Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " MBINT_set/clr ,Mailbox Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " RTCALARMINT_set/clr ,RTC Alarm Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " RTCINT_set/clr ,RTC Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " UARTINT2_set/clr ,UART2 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " UARTINT1_set/clr ,UART1 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " UARTINT0_set/clr ,UART0 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " I2CINT1_set/clr ,I2C1 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " I2CINT0_set/clr ,I2C0 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " TINT3_set/clr ,TIMER3 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " TINT2_set/clr ,TIMER2 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " TINT1_set/clr ,TIMER1 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " SPIINT0_set/clr ,SPI0 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " SDINT0_set/clr ,MMC/SD0 Interrupt Mask" "Not masked,Masked"
group.long 0x0d0++0x03
line.long 0x00 "INTCPS_ISR2_set/clr,Software Interrupt Register 2"
setclrfld.long 0x00 31. 0x00 31. 0x04 31. " TINT7_set/clr ,TIMER7 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 30. 0x00 30. 0x04 30. " TINT6_set/clr ,TIMER6 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 29. 0x00 29. 0x04 29. " TINT5_set/clr ,TIMER5 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " TINT4_set/clr ,TIMER4 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " WDTINT_set/clr ,Watchdog Timer Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 22. 0x00 22. 0x04 22. " MCBSPINT_set/clr ,McBSP Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 21. 0x00 21. 0x04 21. " MCARXINT2_set/clr ,McASP2 Receive Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 20. 0x00 20. 0x04 20. " MCATXINT2_set/clr ,McASP2 Transmit Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " MCARXINT1_set/clr ,McASP1 Receive Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " MCATXINT1_set/clr ,McASP1 Transmit Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " MCARXINT0_set/clr ,McASP0 Receive Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " MCATXINT0_set/clr ,McASP0 Transmit Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " MBINT_set/clr ,Mailbox Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " RTCALARMINT_set/clr ,RTC Alarm Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " RTCINT_set/clr ,RTC Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " UARTINT2_set/clr ,UART2 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " UARTINT1_set/clr ,UART1 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " UARTINT0_set/clr ,UART0 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " I2CINT1_set/clr ,I2C1 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " I2CINT0_set/clr ,I2C0 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " TINT3_set/clr ,TIMER3 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " TINT2_set/clr ,TIMER2 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " TINT1_set/clr ,TIMER1 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " SPIINT0_set/clr ,SPI0 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " SDINT0_set/clr ,MMC/SD0 Interrupt" "No interrupt,Interrupt"
rgroup.long 0x0d8++0x03
line.long 0x00 "INTCPS_PENDING2_IRQ,IRQ Status Register 2"
bitfld.long 0x00 31. " TINT7 ,TIMER7 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 30. " TINT6 ,TIMER6 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 29. " TINT5 ,TIMER5 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 28. " TINT4 ,TIMER4 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " WDTINT ,Watchdog Timer IRQ Status" "Not requested,Requested"
bitfld.long 0x00 22. " MCBSPINT ,McBSP IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 21. " MCARXINT2 ,McASP2 Receive IRQ Status" "Not requested,Requested"
bitfld.long 0x00 20. " MCATXINT2 ,McASP2 Transmit IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " MCARXINT1 ,McASP1 Receive IRQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " MCATXINT1 ,McASP1 Transmit IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " MCARXINT0 ,McASP0 Receive IRQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " MCATXINT0 ,McASP0 Transmit IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " MBINT ,Mailbox IRQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " RTCALARMINT ,RTC Alarm IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " RTCINT ,RTC IRQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " UARTINT2 ,UART2 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " UARTINT1 ,UART1 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " UARTINT0 ,UART0 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " I2CINT1 ,I2C1 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 6. " I2CINT0 ,I2C0 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 5. " TINT3 ,TIMER3 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 4. " TINT2 ,TIMER2 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " TINT1 ,TIMER1 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 1. " SPIINT0 ,SPI0 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 0. " SDINT0 ,MMC/SD0 IRQ Status" "Not requested,Requested"
rgroup.long 0x0dC++0x03
line.long 0x00 "INTCPS_PENDING2_FIQ,FIQ Status Register 2"
bitfld.long 0x00 31. " TINT7 ,TIMER7 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 30. " TINT6 ,TIMER6 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 29. " TINT5 ,TIMER5 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 28. " TINT4 ,TIMER4 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 27. " WDTINT ,Watchdog Timer FIQ Status" "Not requested,Requested"
bitfld.long 0x00 22. " MCBSPINT ,McBSP FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 21. " MCARXINT2 ,McASP2 Receive FIQ Status" "Not requested,Requested"
bitfld.long 0x00 20. " MCATXINT2 ,McASP2 Transmit FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 19. " MCARXINT1 ,McASP1 Receive FIQ Status" "Not requested,Requested"
bitfld.long 0x00 18. " MCATXINT1 ,McASP1 Transmit FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 17. " MCARXINT0 ,McASP0 Receive FIQ Status" "Not requested,Requested"
bitfld.long 0x00 16. " MCATXINT0 ,McASP0 Transmit FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " MBINT ,Mailbox FIQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " RTCALARMINT ,RTC Alarm FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " RTCINT ,RTC FIQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " UARTINT2 ,UART2 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " UARTINT1 ,UART1 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " UARTINT0 ,UART0 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " I2CINT1 ,I2C1 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 6. " I2CINT0 ,I2C0 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 5. " TINT3 ,TIMER3 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 4. " TINT2 ,TIMER2 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " TINT1 ,TIMER1 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 1. " SPIINT0 ,SPI0 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 0. " SDINT0 ,MMC/SD0 FIQ Status" "Not requested,Requested"
tree.end
tree "Interrupts 96-127"
rgroup.long 0x0e0++0x03
line.long 0x00 "INTCPS_ITR3,Raw Interrupt Input Status Register 3"
bitfld.long 0x00 28. " DMMINT ,PAT Fault Raw Interrupt Status" "No interrupt,Interrupt"
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
bitfld.long 0x00 27. " MCMMUINT ,Ducati MMU Fault Raw Interrupt Status" "No interrupt,Interrupt"
endif
textline " "
bitfld.long 0x00 26. " SYSMMUINT ,Table Walk Abort Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 25. " SMRFLX1 ,HVT SmartReflex Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 24. " SMRFLX0 ,SVT SmartReflex Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 19. " TCERRINT3 ,TCERRINT3 Error Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 18. " TCERRINT2 ,TCERRINT2 Error Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 17. " TCERRINT1 ,TCERRINT1 Error Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 16. " TCERRINT0 ,TCERRINT0 Error Raw Interrupt Status" "No interrupt,Interrupt"
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
textline " "
bitfld.long 0x00 15. " HDVICP2CONT2SYNC ,HDVICP2CONT2SYNC Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 14. " HDVICP2CONT1SYNC ,HDVICP2CONT1SYNC Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " HDVICP2MBOXINT ,HDVICP2MBOXINT Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " HDVICP1MBOXINT ,HDVICP1MBOXINT Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " HDVICP0MBOXINT ,HDVICP0MBOXINT Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " HDVICP1CONT2SYNC ,HDVICP1CONT2SYNC Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " HDVICP1CONT1SYNC ,HDVICP1CONT1SYNC Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " HDVICP0CONT2SYNC ,HDVICP0CONT2SYNC Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " HDVICP0CONT1SYNC ,HDVICP0CONT1SYNC Raw Interrupt Status" "No interrupt,Interrupt"
endif
bitfld.long 0x00 6. " DDRERR1 ,DDR1 Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " DDRERR0 ,DDR0 Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " GPMCINT ,GPMC Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " GPIOINT1B ,GPIO1 B Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " GPIOINT1A ,GPIO1 A Raw Interrupt Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " GPIOINT0B ,GPIO0 B Raw Interrupt Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " GPIOINT0A ,GPIO0 A Raw Interrupt Status" "No interrupt,Interrupt"
group.long 0x0e4++0x03
line.long 0x00 "INTCPS_MIR3_set/clr,Interrupt Mask Register 3"
setclrfld.long 0x00 28. 0x08 28. 0x04 28. " DMMINT_set/clr ,PAT Fault Interrupt Mask" "Not masked,Masked"
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
setclrfld.long 0x00 27. 0x08 27. 0x04 27. " MCMMUINT_set/clr ,Ducati MMU Fault Interrupt Mask" "Not masked,Masked"
endif
textline " "
setclrfld.long 0x00 26. 0x08 26. 0x04 26. " SYSMMUINT_set/clr ,Table Walk Abort Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 25. 0x08 25. 0x04 25. " SMRFLX1_set/clr ,HVT SmartReflex Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 24. 0x08 24. 0x04 24. " SMRFLX0_set/clr ,SVT SmartReflex Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 19. 0x08 19. 0x04 19. " TCERRINT3_set/clr ,TCERRINT3 Error Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 18. 0x08 18. 0x04 18. " TCERRINT2_set/clr ,TCERRINT2 Error Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 17. 0x08 17. 0x04 17. " TCERRINT1_set/clr ,TCERRINT1 Error Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 16. 0x08 16. 0x04 16. " TCERRINT0_set/clr ,TCERRINT0 Error Interrupt Mask" "Not masked,Masked"
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
textline " "
setclrfld.long 0x00 15. 0x08 15. 0x04 15. " HDVICP2CONT2SYNC ,HDVICP2CONT2SYNC Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 14. 0x08 14. 0x04 14. " HDVICP2CONT1SYNC ,HDVICP2CONT1SYNC Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 13. 0x08 13. 0x04 13. " HDVICP2MBOXINT ,HDVICP2MBOXINT Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 12. 0x08 12. 0x04 12. " HDVICP1MBOXINT ,HDVICP1MBOXINT Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 11. 0x08 11. 0x04 11. " HDVICP0MBOXINT ,HDVICP0MBOXINT Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 10. 0x08 10. 0x04 10. " HDVICP1CONT2SYNC ,HDVICP1CONT2SYNC Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 9. 0x08 9. 0x04 9. " HDVICP1CONT1SYNC ,HDVICP1CONT1SYNC Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 8. 0x08 8. 0x04 8. " HDVICP0CONT2SYNC ,HDVICP0CONT2SYNC Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 7. 0x08 7. 0x04 7. " HDVICP0CONT1SYNC ,HDVICP0CONT1SYNC Interrupt Mask" "Not masked,Masked"
endif
setclrfld.long 0x00 6. 0x08 6. 0x04 6. " DDRERR1_set/clr ,DDR1 Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 5. 0x08 5. 0x04 5. " DDRERR0_set/clr ,DDR0 Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 4. 0x08 4. 0x04 4. " GPMCINT_set/clr ,GPMC Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 3. 0x08 3. 0x04 3. " GPIOINT1B_set/clr ,GPIO1 B Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 2. 0x08 2. 0x04 2. " GPIOINT1A_set/clr ,GPIO1 A Interrupt Mask" "Not masked,Masked"
textline " "
setclrfld.long 0x00 1. 0x08 1. 0x04 1. " GPIOINT0B_set/clr ,GPIO0 B Interrupt Mask" "Not masked,Masked"
setclrfld.long 0x00 0. 0x08 0. 0x04 0. " GPIOINT0A_set/clr ,GPIO0 A Interrupt Mask" "Not masked,Masked"
group.long 0x0f0++0x03
line.long 0x00 "INTCPS_ISR3_set/clr,Software Interrupt Register 3"
setclrfld.long 0x00 28. 0x00 28. 0x04 28. " DMMINT_set/clr ,PAT Fault Interrupt" "No interrupt,Interrupt"
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
setclrfld.long 0x00 27. 0x00 27. 0x04 27. " MCMMUINT_set/clr ,Ducati MMU Fault Interrupt" "No interrupt,Interrupt"
endif
textline " "
setclrfld.long 0x00 26. 0x00 26. 0x04 26. " SYSMMUINT_set/clr ,Table Walk Abort Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 25. 0x00 25. 0x04 25. " SMRFLX1_set/clr ,HVT SmartReflex Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 24. 0x00 24. 0x04 24. " SMRFLX0_set/clr ,SVT SmartReflex Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 19. 0x00 19. 0x04 19. " TCERRINT3_set/clr ,TCERRINT3 Error Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 18. 0x00 18. 0x04 18. " TCERRINT2_set/clr ,TCERRINT2 Error Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 17. 0x00 17. 0x04 17. " TCERRINT1_set/clr ,TCERRINT1 Error Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x04 16. " TCERRINT0_set/clr ,TCERRINT0 Error Interrupt" "No interrupt,Interrupt"
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
textline " "
setclrfld.long 0x00 15. 0x00 15. 0x04 15. " HDVICP2CONT2SYNC ,HDVICP2CONT2SYNC Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 14. 0x00 14. 0x04 14. " HDVICP2CONT1SYNC ,HDVICP2CONT1SYNC Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x04 13. " HDVICP2MBOXINT ,HDVICP2MBOXINT Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 12. 0x00 12. 0x04 12. " HDVICP1MBOXINT ,HDVICP1MBOXINT Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 11. 0x00 11. 0x04 11. " HDVICP0MBOXINT ,HDVICP0MBOXINT Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 10. 0x00 10. 0x04 10. " HDVICP1CONT2SYNC ,HDVICP1CONT2SYNC Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 9. 0x00 9. 0x04 9. " HDVICP1CONT1SYNC ,HDVICP1CONT1SYNC Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 8. 0x00 8. 0x04 8. " HDVICP0CONT2SYNC ,HDVICP0CONT2SYNC Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x04 7. " HDVICP0CONT1SYNC ,HDVICP0CONT1SYNC Interrupt" "No interrupt,Interrupt"
endif
setclrfld.long 0x00 6. 0x00 6. 0x04 6. " DDRERR1_set/clr ,DDR1 Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 5. 0x00 5. 0x04 5. " DDRERR0_set/clr ,DDR0 Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 4. 0x00 4. 0x04 4. " GPMCINT_set/clr ,GPMC Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 3. 0x00 3. 0x04 3. " GPIOINT1B_set/clr ,GPIO1 B Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 2. 0x00 2. 0x04 2. " GPIOINT1A_set/clr ,GPIO1 A Interrupt" "No interrupt,Interrupt"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x04 1. " GPIOINT0B_set/clr ,GPIO0 B Interrupt" "No interrupt,Interrupt"
setclrfld.long 0x00 0. 0x00 0. 0x04 0. " GPIOINT0A_set/clr ,GPIO0 A Interrupt" "No interrupt,Interrupt"
rgroup.long 0x0f8++0x03
line.long 0x00 "INTCPS_PENDING3_IRQ,IRQ Status Register 3"
bitfld.long 0x00 28. " DMMINT ,PAT Fault IRQ Status" "Not requested,Requested"
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
bitfld.long 0x00 27. " MCMMUINT ,Ducati MMU Fault IRQ Status" "Not requested,Requested"
endif
textline " "
bitfld.long 0x00 26. " SYSMMUINT ,Table Walk Abort IRQ Status" "Not requested,Requested"
bitfld.long 0x00 25. " SMRFLX1 ,HVT SmartReflex IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 24. " SMRFLX0 ,SVT SmartReflex IRQ Status" "Not requested,Requested"
bitfld.long 0x00 19. " TCERRINT3 ,TCERRINT3 Error IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 18. " TCERRINT2 ,TCERRINT2 Error IRQ Status" "Not requested,Requested"
bitfld.long 0x00 17. " TCERRINT1 ,TCERRINT1 Error IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 16. " TCERRINT0 ,TCERRINT0 Error IRQ Status" "Not requested,Requested"
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
textline " "
bitfld.long 0x00 15. " HDVICP2CONT2SYNC ,HDVICP2CONT2SYNC IRQ Status" "Not requested,Requested"
bitfld.long 0x00 14. " HDVICP2CONT1SYNC ,HDVICP2CONT1SYNC IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " HDVICP2MBOXINT ,HDVICP2MBOXINT IRQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " HDVICP1MBOXINT ,HDVICP1MBOXINT IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " HDVICP0MBOXINT ,HDVICP0MBOXINT IRQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " HDVICP1CONT2SYNC ,HDVICP1CONT2SYNC IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " HDVICP1CONT1SYNC ,HDVICP1CONT1SYNC IRQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " HDVICP0CONT2SYNC ,HDVICP0CONT2SYNC IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " HDVICP0CONT1SYNC ,HDVICP0CONT1SYNC IRQ Status" "Not requested,Requested"
endif
bitfld.long 0x00 6. " DDRERR1 ,DDR1 IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 5. " DDRERR0 ,DDR0 IRQ Status" "Not requested,Requested"
bitfld.long 0x00 4. " GPMCINT ,GPMC IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " GPIOINT1B ,GPIO1 B IRQ Status" "Not requested,Requested"
bitfld.long 0x00 2. " GPIOINT1A ,GPIO1 A IRQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 1. " GPIOINT0B ,GPIO0 B IRQ Status" "Not requested,Requested"
bitfld.long 0x00 0. " GPIOINT0A ,GPIO0 A IRQ Status" "Not requested,Requested"
rgroup.long 0x0fC++0x03
line.long 0x00 "INTCPS_PENDING3_FIQ,FIQ Status Register 3"
bitfld.long 0x00 28. " DMMINT ,PAT Fault FIQ Status" "Not requested,Requested"
sif (cpu()!="DM8165"&&cpu()!="DM8166"&&cpu()!="DM8167"&&cpu()!="DM8168")
bitfld.long 0x00 27. " MCMMUINT ,Ducati MMU Fault FIQ Status" "Not requested,Requested"
endif
textline " "
bitfld.long 0x00 26. " SYSMMUINT ,Table Walk Abort FIQ Status" "Not requested,Requested"
bitfld.long 0x00 25. " SMRFLX1 ,HVT SmartReflex FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 24. " SMRFLX0 ,SVT SmartReflex FIQ Status" "Not requested,Requested"
bitfld.long 0x00 19. " TCERRINT3 ,TCERRINT3 Error FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 18. " TCERRINT2 ,TCERRINT2 Error FIQ Status" "Not requested,Requested"
bitfld.long 0x00 17. " TCERRINT1 ,TCERRINT1 Error FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 16. " TCERRINT0 ,TCERRINT0 Error FIQ Status" "Not requested,Requested"
sif (cpu()=="DM8165"||cpu()=="DM8166"||cpu()=="DM8167"||cpu()=="DM8168")
textline " "
bitfld.long 0x00 15. " HDVICP2CONT2SYNC ,HDVICP2CONT2SYNC FIQ Status" "Not requested,Requested"
bitfld.long 0x00 14. " HDVICP2CONT1SYNC ,HDVICP2CONT1SYNC FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 13. " HDVICP2MBOXINT ,HDVICP2MBOXINT FIQ Status" "Not requested,Requested"
bitfld.long 0x00 12. " HDVICP1MBOXINT ,HDVICP1MBOXINT FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 11. " HDVICP0MBOXINT ,HDVICP0MBOXINT FIQ Status" "Not requested,Requested"
bitfld.long 0x00 10. " HDVICP1CONT2SYNC ,HDVICP1CONT2SYNC FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 9. " HDVICP1CONT1SYNC ,HDVICP1CONT1SYNC FIQ Status" "Not requested,Requested"
bitfld.long 0x00 8. " HDVICP0CONT2SYNC ,HDVICP0CONT2SYNC FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 7. " HDVICP0CONT1SYNC ,HDVICP0CONT1SYNC FIQ Status" "Not requested,Requested"
endif
bitfld.long 0x00 6. " DDRERR1 ,DDR1 FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 5. " DDRERR0 ,DDR0 FIQ Status" "Not requested,Requested"
bitfld.long 0x00 4. " GPMCINT ,GPMC FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 3. " GPIOINT1B ,GPIO1 B FIQ Status" "Not requested,Requested"
bitfld.long 0x00 2. " GPIOINT1A ,GPIO1 A FIQ Status" "Not requested,Requested"
textline " "
bitfld.long 0x00 1. " GPIOINT0B ,GPIO0 B FIQ Status" "Not requested,Requested"
bitfld.long 0x00 0. " GPIOINT0A ,GPIO0 A FIQ Status" "Not requested,Requested"
tree.end
tree "Interrupts Priorities / FIQ/IRQ steering"
width 15.
sif (cpu()=="AM3894"||cpu()=="C6A8168")
group.long 0x100++0x3
line.long 0x00 "INTCPS_ILR0,Interrupt 0 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x104++0x3
line.long 0x00 "INTCPS_ILR1,Interrupt 1 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x108++0x3
line.long 0x00 "INTCPS_ILR2,Interrupt 2 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x10C++0x3
line.long 0x00 "INTCPS_ILR3,Interrupt 3 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x110++0x3
line.long 0x00 "INTCPS_ILR4,Interrupt 4 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x11C++0x3
line.long 0x00 "INTCPS_ILR7,Interrupt 7 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x124++0x3
line.long 0x00 "INTCPS_ILR9,Interrupt 9 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x128++0x3
line.long 0x00 "INTCPS_ILR10,Interrupt 10 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x130++0x3
line.long 0x00 "INTCPS_ILR12,Interrupt 12 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x134++0x3
line.long 0x00 "INTCPS_ILR13,Interrupt 13 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x138++0x3
line.long 0x00 "INTCPS_ILR14,Interrupt 14 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x140++0x3
line.long 0x00 "INTCPS_ILR16,Interrupt 16 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x144++0x3
line.long 0x00 "INTCPS_ILR17,Interrupt 17 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x148++0x3
line.long 0x00 "INTCPS_ILR18,Interrupt 18 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x14C++0x3
line.long 0x00 "INTCPS_ILR19,Interrupt 19 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x188++0x3
line.long 0x00 "INTCPS_ILR34,Interrupt 34 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x18C++0x3
line.long 0x00 "INTCPS_ILR35,Interrupt 35 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x190++0x3
line.long 0x00 "INTCPS_ILR36,Interrupt 36 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x194++0x3
line.long 0x00 "INTCPS_ILR37,Interrupt 37 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A0++0x3
line.long 0x00 "INTCPS_ILR40,Interrupt 40 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A4++0x3
line.long 0x00 "INTCPS_ILR41,Interrupt 41 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A8++0x3
line.long 0x00 "INTCPS_ILR42,Interrupt 42 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1AC++0x3
line.long 0x00 "INTCPS_ILR43,Interrupt 43 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B0++0x3
line.long 0x00 "INTCPS_ILR44,Interrupt 44 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B4++0x3
line.long 0x00 "INTCPS_ILR45,Interrupt 45 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B8++0x3
line.long 0x00 "INTCPS_ILR46,Interrupt 46 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1BC++0x3
line.long 0x00 "INTCPS_ILR47,Interrupt 47 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C0++0x3
line.long 0x00 "INTCPS_ILR48,Interrupt 48 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C4++0x3
line.long 0x00 "INTCPS_ILR49,Interrupt 49 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C8++0x3
line.long 0x00 "INTCPS_ILR50,Interrupt 50 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1CC++0x3
line.long 0x00 "INTCPS_ILR51,Interrupt 51 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x200++0x3
line.long 0x00 "INTCPS_ILR64,Interrupt 64 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x204++0x3
line.long 0x00 "INTCPS_ILR65,Interrupt 65 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x20C++0x3
line.long 0x00 "INTCPS_ILR67,Interrupt 67 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x210++0x3
line.long 0x00 "INTCPS_ILR68,Interrupt 68 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x214++0x3
line.long 0x00 "INTCPS_ILR69,Interrupt 69 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x218++0x3
line.long 0x00 "INTCPS_ILR70,Interrupt 70 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x21C++0x3
line.long 0x00 "INTCPS_ILR71,Interrupt 71 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x220++0x3
line.long 0x00 "INTCPS_ILR72,Interrupt 72 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x224++0x3
line.long 0x00 "INTCPS_ILR73,Interrupt 73 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x228++0x3
line.long 0x00 "INTCPS_ILR74,Interrupt 74 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x22C++0x3
line.long 0x00 "INTCPS_ILR75,Interrupt 75 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x230++0x3
line.long 0x00 "INTCPS_ILR76,Interrupt 76 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x234++0x3
line.long 0x00 "INTCPS_ILR77,Interrupt 77 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x240++0x3
line.long 0x00 "INTCPS_ILR80,Interrupt 80 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x244++0x3
line.long 0x00 "INTCPS_ILR81,Interrupt 81 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x248++0x3
line.long 0x00 "INTCPS_ILR82,Interrupt 82 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x24C++0x3
line.long 0x00 "INTCPS_ILR83,Interrupt 83 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x250++0x3
line.long 0x00 "INTCPS_ILR84,Interrupt 84 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x254++0x3
line.long 0x00 "INTCPS_ILR85,Interrupt 85 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x258++0x3
line.long 0x00 "INTCPS_ILR86,Interrupt 86 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x26C++0x3
line.long 0x00 "INTCPS_ILR91,Interrupt 91 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x270++0x3
line.long 0x00 "INTCPS_ILR92,Interrupt 92 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x274++0x3
line.long 0x00 "INTCPS_ILR93,Interrupt 93 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x278++0x3
line.long 0x00 "INTCPS_ILR94,Interrupt 94 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x27C++0x3
line.long 0x00 "INTCPS_ILR95,Interrupt 95 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x280++0x3
line.long 0x00 "INTCPS_ILR96,Interrupt 96 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x284++0x3
line.long 0x00 "INTCPS_ILR97,Interrupt 97 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x288++0x3
line.long 0x00 "INTCPS_ILR98,Interrupt 98 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x28C++0x3
line.long 0x00 "INTCPS_ILR99,Interrupt 99 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x290++0x3
line.long 0x00 "INTCPS_ILR100,Interrupt 100 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x294++0x3
line.long 0x00 "INTCPS_ILR101,Interrupt 101 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x298++0x3
line.long 0x00 "INTCPS_ILR102,Interrupt 102 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C0++0x3
line.long 0x00 "INTCPS_ILR112,Interrupt 112 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C4++0x3
line.long 0x00 "INTCPS_ILR113,Interrupt 113 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C8++0x3
line.long 0x00 "INTCPS_ILR114,Interrupt 114 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2CC++0x3
line.long 0x00 "INTCPS_ILR115,Interrupt 115 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E0++0x3
line.long 0x00 "INTCPS_ILR120,Interrupt 120 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E4++0x3
line.long 0x00 "INTCPS_ILR121,Interrupt 121 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E8++0x3
line.long 0x00 "INTCPS_ILR122,Interrupt 122 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2EC++0x3
line.long 0x00 "INTCPS_ILR123,Interrupt 123 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2F0++0x3
line.long 0x00 "INTCPS_ILR124,Interrupt 124 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
elif (cpu()=="DM8165"||cpu()=="DM8167")
group.long 0x100++0x3
line.long 0x00 "INTCPS_ILR0,Interrupt 0 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x104++0x3
line.long 0x00 "INTCPS_ILR1,Interrupt 1 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x108++0x3
line.long 0x00 "INTCPS_ILR2,Interrupt 2 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x10C++0x3
line.long 0x00 "INTCPS_ILR3,Interrupt 3 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x110++0x3
line.long 0x00 "INTCPS_ILR4,Interrupt 4 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x11C++0x3
line.long 0x00 "INTCPS_ILR7,Interrupt 7 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x124++0x3
line.long 0x00 "INTCPS_ILR9,Interrupt 9 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x128++0x3
line.long 0x00 "INTCPS_ILR10,Interrupt 10 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x130++0x3
line.long 0x00 "INTCPS_ILR12,Interrupt 12 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x134++0x3
line.long 0x00 "INTCPS_ILR13,Interrupt 13 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x138++0x3
line.long 0x00 "INTCPS_ILR14,Interrupt 14 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x140++0x3
line.long 0x00 "INTCPS_ILR16,Interrupt 16 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x144++0x3
line.long 0x00 "INTCPS_ILR17,Interrupt 17 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x148++0x3
line.long 0x00 "INTCPS_ILR18,Interrupt 18 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x14C++0x3
line.long 0x00 "INTCPS_ILR19,Interrupt 19 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x188++0x3
line.long 0x00 "INTCPS_ILR34,Interrupt 34 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x18C++0x3
line.long 0x00 "INTCPS_ILR35,Interrupt 35 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x190++0x3
line.long 0x00 "INTCPS_ILR36,Interrupt 36 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x194++0x3
line.long 0x00 "INTCPS_ILR37,Interrupt 37 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x198++0x3
line.long 0x00 "INTCPS_ILR38,Interrupt 38 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A0++0x3
line.long 0x00 "INTCPS_ILR40,Interrupt 40 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A4++0x3
line.long 0x00 "INTCPS_ILR41,Interrupt 41 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A8++0x3
line.long 0x00 "INTCPS_ILR42,Interrupt 42 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1AC++0x3
line.long 0x00 "INTCPS_ILR43,Interrupt 43 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B0++0x3
line.long 0x00 "INTCPS_ILR44,Interrupt 44 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B4++0x3
line.long 0x00 "INTCPS_ILR45,Interrupt 45 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B8++0x3
line.long 0x00 "INTCPS_ILR46,Interrupt 46 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1BC++0x3
line.long 0x00 "INTCPS_ILR47,Interrupt 47 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C0++0x3
line.long 0x00 "INTCPS_ILR48,Interrupt 48 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C4++0x3
line.long 0x00 "INTCPS_ILR49,Interrupt 49 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C8++0x3
line.long 0x00 "INTCPS_ILR50,Interrupt 50 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1CC++0x3
line.long 0x00 "INTCPS_ILR51,Interrupt 51 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x200++0x3
line.long 0x00 "INTCPS_ILR64,Interrupt 64 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x204++0x3
line.long 0x00 "INTCPS_ILR65,Interrupt 65 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x20C++0x3
line.long 0x00 "INTCPS_ILR67,Interrupt 67 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x210++0x3
line.long 0x00 "INTCPS_ILR68,Interrupt 68 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x214++0x3
line.long 0x00 "INTCPS_ILR69,Interrupt 69 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x218++0x3
line.long 0x00 "INTCPS_ILR70,Interrupt 70 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x21C++0x3
line.long 0x00 "INTCPS_ILR71,Interrupt 71 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x220++0x3
line.long 0x00 "INTCPS_ILR72,Interrupt 72 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x224++0x3
line.long 0x00 "INTCPS_ILR73,Interrupt 73 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x228++0x3
line.long 0x00 "INTCPS_ILR74,Interrupt 74 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x22C++0x3
line.long 0x00 "INTCPS_ILR75,Interrupt 75 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x230++0x3
line.long 0x00 "INTCPS_ILR76,Interrupt 76 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x234++0x3
line.long 0x00 "INTCPS_ILR77,Interrupt 77 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x240++0x3
line.long 0x00 "INTCPS_ILR80,Interrupt 80 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x244++0x3
line.long 0x00 "INTCPS_ILR81,Interrupt 81 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x248++0x3
line.long 0x00 "INTCPS_ILR82,Interrupt 82 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x24C++0x3
line.long 0x00 "INTCPS_ILR83,Interrupt 83 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x250++0x3
line.long 0x00 "INTCPS_ILR84,Interrupt 84 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x254++0x3
line.long 0x00 "INTCPS_ILR85,Interrupt 85 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x258++0x3
line.long 0x00 "INTCPS_ILR86,Interrupt 86 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x26C++0x3
line.long 0x00 "INTCPS_ILR91,Interrupt 91 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x270++0x3
line.long 0x00 "INTCPS_ILR92,Interrupt 92 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x274++0x3
line.long 0x00 "INTCPS_ILR93,Interrupt 93 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x278++0x3
line.long 0x00 "INTCPS_ILR94,Interrupt 94 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x27C++0x3
line.long 0x00 "INTCPS_ILR95,Interrupt 95 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x280++0x3
line.long 0x00 "INTCPS_ILR96,Interrupt 96 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x284++0x3
line.long 0x00 "INTCPS_ILR97,Interrupt 97 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x288++0x3
line.long 0x00 "INTCPS_ILR98,Interrupt 98 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x28C++0x3
line.long 0x00 "INTCPS_ILR99,Interrupt 99 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x290++0x3
line.long 0x00 "INTCPS_ILR100,Interrupt 100 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x294++0x3
line.long 0x00 "INTCPS_ILR101,Interrupt 101 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x298++0x3
line.long 0x00 "INTCPS_ILR102,Interrupt 102 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x29C++0x3
line.long 0x00 "INTCPS_ILR103,Interrupt 103 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A0++0x3
line.long 0x00 "INTCPS_ILR104,Interrupt 104 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A4++0x3
line.long 0x00 "INTCPS_ILR105,Interrupt 105 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A8++0x3
line.long 0x00 "INTCPS_ILR106,Interrupt 106 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2AC++0x3
line.long 0x00 "INTCPS_ILR107,Interrupt 107 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B0++0x3
line.long 0x00 "INTCPS_ILR108,Interrupt 108 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B4++0x3
line.long 0x00 "INTCPS_ILR109,Interrupt 109 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B8++0x3
line.long 0x00 "INTCPS_ILR110,Interrupt 110 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2BC++0x3
line.long 0x00 "INTCPS_ILR111,Interrupt 111 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C0++0x3
line.long 0x00 "INTCPS_ILR112,Interrupt 112 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C4++0x3
line.long 0x00 "INTCPS_ILR113,Interrupt 113 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C8++0x3
line.long 0x00 "INTCPS_ILR114,Interrupt 114 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2CC++0x3
line.long 0x00 "INTCPS_ILR115,Interrupt 115 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E0++0x3
line.long 0x00 "INTCPS_ILR120,Interrupt 120 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E4++0x3
line.long 0x00 "INTCPS_ILR121,Interrupt 121 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E8++0x3
line.long 0x00 "INTCPS_ILR122,Interrupt 122 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2F0++0x3
line.long 0x00 "INTCPS_ILR124,Interrupt 124 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
elif (cpu()=="DM8166"||cpu()=="DM8168")
group.long 0x100++0x3
line.long 0x00 "INTCPS_ILR0,Interrupt 0 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x104++0x3
line.long 0x00 "INTCPS_ILR1,Interrupt 1 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x108++0x3
line.long 0x00 "INTCPS_ILR2,Interrupt 2 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x10C++0x3
line.long 0x00 "INTCPS_ILR3,Interrupt 3 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x110++0x3
line.long 0x00 "INTCPS_ILR4,Interrupt 4 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x11C++0x3
line.long 0x00 "INTCPS_ILR7,Interrupt 7 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x124++0x3
line.long 0x00 "INTCPS_ILR9,Interrupt 9 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x128++0x3
line.long 0x00 "INTCPS_ILR10,Interrupt 10 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x130++0x3
line.long 0x00 "INTCPS_ILR12,Interrupt 12 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x134++0x3
line.long 0x00 "INTCPS_ILR13,Interrupt 13 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x138++0x3
line.long 0x00 "INTCPS_ILR14,Interrupt 14 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x140++0x3
line.long 0x00 "INTCPS_ILR16,Interrupt 16 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x144++0x3
line.long 0x00 "INTCPS_ILR17,Interrupt 17 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x148++0x3
line.long 0x00 "INTCPS_ILR18,Interrupt 18 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x14C++0x3
line.long 0x00 "INTCPS_ILR19,Interrupt 19 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x188++0x3
line.long 0x00 "INTCPS_ILR34,Interrupt 34 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x18C++0x3
line.long 0x00 "INTCPS_ILR35,Interrupt 35 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x190++0x3
line.long 0x00 "INTCPS_ILR36,Interrupt 36 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x198++0x3
line.long 0x00 "INTCPS_ILR38,Interrupt 38 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A0++0x3
line.long 0x00 "INTCPS_ILR40,Interrupt 40 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A4++0x3
line.long 0x00 "INTCPS_ILR41,Interrupt 41 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A8++0x3
line.long 0x00 "INTCPS_ILR42,Interrupt 42 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1AC++0x3
line.long 0x00 "INTCPS_ILR43,Interrupt 43 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B0++0x3
line.long 0x00 "INTCPS_ILR44,Interrupt 44 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B4++0x3
line.long 0x00 "INTCPS_ILR45,Interrupt 45 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B8++0x3
line.long 0x00 "INTCPS_ILR46,Interrupt 46 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1BC++0x3
line.long 0x00 "INTCPS_ILR47,Interrupt 47 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C0++0x3
line.long 0x00 "INTCPS_ILR48,Interrupt 48 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C4++0x3
line.long 0x00 "INTCPS_ILR49,Interrupt 49 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C8++0x3
line.long 0x00 "INTCPS_ILR50,Interrupt 50 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1CC++0x3
line.long 0x00 "INTCPS_ILR51,Interrupt 51 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x200++0x3
line.long 0x00 "INTCPS_ILR64,Interrupt 64 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x204++0x3
line.long 0x00 "INTCPS_ILR65,Interrupt 65 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x20C++0x3
line.long 0x00 "INTCPS_ILR67,Interrupt 67 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x210++0x3
line.long 0x00 "INTCPS_ILR68,Interrupt 68 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x214++0x3
line.long 0x00 "INTCPS_ILR69,Interrupt 69 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x218++0x3
line.long 0x00 "INTCPS_ILR70,Interrupt 70 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x21C++0x3
line.long 0x00 "INTCPS_ILR71,Interrupt 71 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x220++0x3
line.long 0x00 "INTCPS_ILR72,Interrupt 72 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x224++0x3
line.long 0x00 "INTCPS_ILR73,Interrupt 73 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x228++0x3
line.long 0x00 "INTCPS_ILR74,Interrupt 74 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x22C++0x3
line.long 0x00 "INTCPS_ILR75,Interrupt 75 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x230++0x3
line.long 0x00 "INTCPS_ILR76,Interrupt 76 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x234++0x3
line.long 0x00 "INTCPS_ILR77,Interrupt 77 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x240++0x3
line.long 0x00 "INTCPS_ILR80,Interrupt 80 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x244++0x3
line.long 0x00 "INTCPS_ILR81,Interrupt 81 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x248++0x3
line.long 0x00 "INTCPS_ILR82,Interrupt 82 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x24C++0x3
line.long 0x00 "INTCPS_ILR83,Interrupt 83 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x250++0x3
line.long 0x00 "INTCPS_ILR84,Interrupt 84 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x254++0x3
line.long 0x00 "INTCPS_ILR85,Interrupt 85 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x258++0x3
line.long 0x00 "INTCPS_ILR86,Interrupt 86 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x26C++0x3
line.long 0x00 "INTCPS_ILR91,Interrupt 91 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x270++0x3
line.long 0x00 "INTCPS_ILR92,Interrupt 92 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x274++0x3
line.long 0x00 "INTCPS_ILR93,Interrupt 93 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x278++0x3
line.long 0x00 "INTCPS_ILR94,Interrupt 94 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x27C++0x3
line.long 0x00 "INTCPS_ILR95,Interrupt 95 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x280++0x3
line.long 0x00 "INTCPS_ILR96,Interrupt 96 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x284++0x3
line.long 0x00 "INTCPS_ILR97,Interrupt 97 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x288++0x3
line.long 0x00 "INTCPS_ILR98,Interrupt 98 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x28C++0x3
line.long 0x00 "INTCPS_ILR99,Interrupt 99 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x290++0x3
line.long 0x00 "INTCPS_ILR100,Interrupt 100 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x294++0x3
line.long 0x00 "INTCPS_ILR101,Interrupt 101 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x298++0x3
line.long 0x00 "INTCPS_ILR102,Interrupt 102 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x29C++0x3
line.long 0x00 "INTCPS_ILR103,Interrupt 103 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A0++0x3
line.long 0x00 "INTCPS_ILR104,Interrupt 104 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A4++0x3
line.long 0x00 "INTCPS_ILR105,Interrupt 105 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2A8++0x3
line.long 0x00 "INTCPS_ILR106,Interrupt 106 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2AC++0x3
line.long 0x00 "INTCPS_ILR107,Interrupt 107 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B0++0x3
line.long 0x00 "INTCPS_ILR108,Interrupt 108 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B4++0x3
line.long 0x00 "INTCPS_ILR109,Interrupt 109 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2B8++0x3
line.long 0x00 "INTCPS_ILR110,Interrupt 110 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2BC++0x3
line.long 0x00 "INTCPS_ILR111,Interrupt 111 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C0++0x3
line.long 0x00 "INTCPS_ILR112,Interrupt 112 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C4++0x3
line.long 0x00 "INTCPS_ILR113,Interrupt 113 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C8++0x3
line.long 0x00 "INTCPS_ILR114,Interrupt 114 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2CC++0x3
line.long 0x00 "INTCPS_ILR115,Interrupt 115 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E0++0x3
line.long 0x00 "INTCPS_ILR120,Interrupt 120 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E4++0x3
line.long 0x00 "INTCPS_ILR121,Interrupt 121 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E8++0x3
line.long 0x00 "INTCPS_ILR122,Interrupt 122 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2F0++0x3
line.long 0x00 "INTCPS_ILR124,Interrupt 124 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
else
group.long 0x100++0x3
line.long 0x00 "INTCPS_ILR0,Interrupt 0 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x104++0x3
line.long 0x00 "INTCPS_ILR1,Interrupt 1 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x108++0x3
line.long 0x00 "INTCPS_ILR2,Interrupt 2 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x10C++0x3
line.long 0x00 "INTCPS_ILR3,Interrupt 3 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x110++0x3
line.long 0x00 "INTCPS_ILR4,Interrupt 4 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x11C++0x3
line.long 0x00 "INTCPS_ILR7,Interrupt 7 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x124++0x3
line.long 0x00 "INTCPS_ILR9,Interrupt 9 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x128++0x3
line.long 0x00 "INTCPS_ILR10,Interrupt 10 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x130++0x3
line.long 0x00 "INTCPS_ILR12,Interrupt 12 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x134++0x3
line.long 0x00 "INTCPS_ILR13,Interrupt 13 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x138++0x3
line.long 0x00 "INTCPS_ILR14,Interrupt 14 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x140++0x3
line.long 0x00 "INTCPS_ILR16,Interrupt 16 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x144++0x3
line.long 0x00 "INTCPS_ILR17,Interrupt 17 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x148++0x3
line.long 0x00 "INTCPS_ILR18,Interrupt 18 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x14C++0x3
line.long 0x00 "INTCPS_ILR19,Interrupt 19 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x188++0x3
line.long 0x00 "INTCPS_ILR34,Interrupt 34 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x18C++0x3
line.long 0x00 "INTCPS_ILR35,Interrupt 35 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x190++0x3
line.long 0x00 "INTCPS_ILR36,Interrupt 36 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A0++0x3
line.long 0x00 "INTCPS_ILR40,Interrupt 40 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A4++0x3
line.long 0x00 "INTCPS_ILR41,Interrupt 41 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1A8++0x3
line.long 0x00 "INTCPS_ILR42,Interrupt 42 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1AC++0x3
line.long 0x00 "INTCPS_ILR43,Interrupt 43 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B0++0x3
line.long 0x00 "INTCPS_ILR44,Interrupt 44 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B4++0x3
line.long 0x00 "INTCPS_ILR45,Interrupt 45 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1B8++0x3
line.long 0x00 "INTCPS_ILR46,Interrupt 46 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1BC++0x3
line.long 0x00 "INTCPS_ILR47,Interrupt 47 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C0++0x3
line.long 0x00 "INTCPS_ILR48,Interrupt 48 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C4++0x3
line.long 0x00 "INTCPS_ILR49,Interrupt 49 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1C8++0x3
line.long 0x00 "INTCPS_ILR50,Interrupt 50 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x1CC++0x3
line.long 0x00 "INTCPS_ILR51,Interrupt 51 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x200++0x3
line.long 0x00 "INTCPS_ILR64,Interrupt 64 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x204++0x3
line.long 0x00 "INTCPS_ILR65,Interrupt 65 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x20C++0x3
line.long 0x00 "INTCPS_ILR67,Interrupt 67 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x210++0x3
line.long 0x00 "INTCPS_ILR68,Interrupt 68 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x214++0x3
line.long 0x00 "INTCPS_ILR69,Interrupt 69 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x218++0x3
line.long 0x00 "INTCPS_ILR70,Interrupt 70 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x21C++0x3
line.long 0x00 "INTCPS_ILR71,Interrupt 71 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x220++0x3
line.long 0x00 "INTCPS_ILR72,Interrupt 72 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x224++0x3
line.long 0x00 "INTCPS_ILR73,Interrupt 73 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x228++0x3
line.long 0x00 "INTCPS_ILR74,Interrupt 74 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x22C++0x3
line.long 0x00 "INTCPS_ILR75,Interrupt 75 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x230++0x3
line.long 0x00 "INTCPS_ILR76,Interrupt 76 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x234++0x3
line.long 0x00 "INTCPS_ILR77,Interrupt 77 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x240++0x3
line.long 0x00 "INTCPS_ILR80,Interrupt 80 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x244++0x3
line.long 0x00 "INTCPS_ILR81,Interrupt 81 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x248++0x3
line.long 0x00 "INTCPS_ILR82,Interrupt 82 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x24C++0x3
line.long 0x00 "INTCPS_ILR83,Interrupt 83 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x250++0x3
line.long 0x00 "INTCPS_ILR84,Interrupt 84 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x254++0x3
line.long 0x00 "INTCPS_ILR85,Interrupt 85 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x258++0x3
line.long 0x00 "INTCPS_ILR86,Interrupt 86 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x26C++0x3
line.long 0x00 "INTCPS_ILR91,Interrupt 91 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x270++0x3
line.long 0x00 "INTCPS_ILR92,Interrupt 92 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x274++0x3
line.long 0x00 "INTCPS_ILR93,Interrupt 93 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x278++0x3
line.long 0x00 "INTCPS_ILR94,Interrupt 94 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x27C++0x3
line.long 0x00 "INTCPS_ILR95,Interrupt 95 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x280++0x3
line.long 0x00 "INTCPS_ILR96,Interrupt 96 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x284++0x3
line.long 0x00 "INTCPS_ILR97,Interrupt 97 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x288++0x3
line.long 0x00 "INTCPS_ILR98,Interrupt 98 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x28C++0x3
line.long 0x00 "INTCPS_ILR99,Interrupt 99 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x290++0x3
line.long 0x00 "INTCPS_ILR100,Interrupt 100 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x294++0x3
line.long 0x00 "INTCPS_ILR101,Interrupt 101 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x298++0x3
line.long 0x00 "INTCPS_ILR102,Interrupt 102 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C0++0x3
line.long 0x00 "INTCPS_ILR112,Interrupt 112 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C4++0x3
line.long 0x00 "INTCPS_ILR113,Interrupt 113 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2C8++0x3
line.long 0x00 "INTCPS_ILR114,Interrupt 114 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2CC++0x3
line.long 0x00 "INTCPS_ILR115,Interrupt 115 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E0++0x3
line.long 0x00 "INTCPS_ILR120,Interrupt 120 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E4++0x3
line.long 0x00 "INTCPS_ILR121,Interrupt 121 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2E8++0x3
line.long 0x00 "INTCPS_ILR122,Interrupt 122 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2EC++0x3
line.long 0x00 "INTCPS_ILR123,Interrupt 123 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
group.long 0x2F0++0x3
line.long 0x00 "INTCPS_ILR124,Interrupt 124 Priority / FIQ/IRQ steering Register"
hexmask.long.byte 0x00 2.--8. 1. " PRIORITY ,Interrupt priority"
bitfld.long 0x00 0. " FIQNIRQ ,Interrupt IRQ/FIQ mapping" "IRQ,FIQ"
endif
tree.end
width 0xb
tree.end
endif
tree "SD/SDIO (Secure Digital/Secure Digital I/O Card Interface)"
base ad:0x48060000
width 17.
sif !(cpuis("AM335*"))
rgroup.long 0x00++0x7
line.long 0x00 "SD_HL_REV,IP Revision Identifier Register"
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
bitfld.long 0x00 11.--15. " R_RTL ,R_RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
line.long 0x04 "SD_HL_HWINFO,Hardware Configuration Register"
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x04 2.--5. " MEM_SIZE ,Memory Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x04 1. " MERGE_MEM ,Merge memory" "Low,High"
textline " "
else
bitfld.long 0x04 1. " MEM_SIZE ,Memory Size" "Low,High"
textline " "
endif
bitfld.long 0x04 0. " MADMA_EN ,MADMA Enable" "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "SD_HL_SYSCONFIG,Clock Management Configuration Register"
bitfld.long 0x00 4.--5. " STANDBYMODE ,Standby mode" "Mode0,Mode1,Mode2,Mode3"
bitfld.long 0x00 2.--3. " IDLEMODE ,Idle mode" "Mode0,Mode1,Mode2,Mode3"
bitfld.long 0x00 1. " FREEEMU ,Free EMU" "Low,High"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Soft reset" "No reset,Reset"
endif
width 17.
group.long 0x110++0x3
line.long 0x00 "SD_SYSCONFIG,System Configuration Register"
bitfld.long 0x00 12.--13. " STANDBYMODE ,Master interface power management standby/wait control (when MADMA is enabled)" "Force-standby,No standby,Smart-standby,Smart-standby wake-up-capable"
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period" "Inactive,Interface,Functional,Both"
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Force idle,No idle,Smart idle,Smart idle wake-up-capable"
textline " "
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up capability enable" "Disabled,Enabled"
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.long 0x00 0. " AUTOIDLE ,Internal clock gating strategy" "Free-running,Automatic"
rgroup.long 0x114++0x3
line.long 0x00 "SD_SYSSTATUS,System Status Register"
bitfld.long 0x00 0. " RESETDONE ,Reset status" "On-going,Done"
group.long 0x124++0x7
line.long 0x00 "SD_CSRE,Card Status Response Error Register"
width 17.
line.long 0x04 "SD_SYSTEST,System Test Register"
bitfld.long 0x04 16. " OBI ,Out of band interrupt data value input/output" "Low,High"
bitfld.long 0x04 15. " SDCD ,Card detect input/output signal data value" "Low,High"
bitfld.long 0x04 14. " SDWP ,Write protect input/output signal data value" "Low,High"
textline " "
bitfld.long 0x04 13. " WAKD ,Wake request input/output signal data value" "Low,High"
bitfld.long 0x04 12. " SSB ,Set status bit" "Clear,Force"
bitfld.long 0x04 11. " D7D ,DAT7 input/output signal data value" "Low,High"
textline " "
bitfld.long 0x04 10. " D6D ,DAT6 input/output signal data value" "Low,High"
bitfld.long 0x04 9. " D5D ,DAT5 input/output signal data value" "Low,High"
bitfld.long 0x04 8. " D4D ,DAT4 input/output signal data value" "Low,High"
textline " "
bitfld.long 0x04 7. " D3D ,DAT3 input/output signal data value" "Low,High"
bitfld.long 0x04 6. " D2D ,DAT2 input/output signal data value" "Low,High"
bitfld.long 0x04 5. " D1D ,DAT1 input/output signal data value" "Low,High"
textline " "
bitfld.long 0x04 4. " D0D ,DAT0 input/output signal data value" "Low,High"
bitfld.long 0x04 3. " DDIR ,Control of the DAT[7:0] pins direction" "Output,Input"
bitfld.long 0x04 2. " CDAT ,CMD input/output signal data value" "Low,High"
textline " "
bitfld.long 0x04 1. " CDIR ,Control of the CMD pin direction" "Output,Input"
bitfld.long 0x04 0. " MCKD ,Clock input/output signal data value" "Low,High"
width 17.
group.long 0x12c++0x7
line.long 0x00 "SD_CON,Configuration Register"
bitfld.long 0x00 21. " SDMA_LNE ,Select Slave DMA Level/Edge Request" "Edge,Level"
bitfld.long 0x00 20. " DMA_MNS ,DMA Master or Slave selection(when MADMA is enabled)" "Slave,?..."
bitfld.long 0x00 19. " DDR ,Dual data rate transmission mode" "Single edge,Both"
textline " "
bitfld.long 0x00 18. " BOOT_CF0 ,Boot Status supported" "Not forced,Forced"
bitfld.long 0x00 17. " BOOT_ACK ,Boot acknowledge receive" "NO ACK,ACK"
bitfld.long 0x00 16. " CLKEXTFREE ,External clock free running" "Cut off,Maintained"
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
textline " "
bitfld.long 0x00 15. " PADEN ,Control Power for MMC Lines" "Not forced,Forced"
bitfld.long 0x00 12. " CEATA ,CE-ATA control mode" "Standard,CE-ATA"
endif
textline " "
bitfld.long 0x00 11. " CTPL ,Control Power for SD_DAT1 line" "Disabled,Enabled"
bitfld.long 0x00 9.--10. " DVAL ,Debounce period for filter SDCD" "33 us,231 us,1 ms,8.4 ms"
bitfld.long 0x00 8. " WPP ,Write protect polarity (SD and SDIO cards only)" "Active high,Active low"
textline " "
bitfld.long 0x00 7. " CDP ,Card detect polarity (all cards)" "Active high,Active low"
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 6. " MIT ,MMC Interrupt Command" "Enabled,Disabled"
textline " "
bitfld.long 0x00 5. " DW8 ,8-bit mode select (MMC cars only)" "1-bit/4-bit,8-bit"
endif
bitfld.long 0x00 4. " MODE ,Mode select(all cards)" "Functional,SYSTEST"
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 3. " STR ,Stream command (MMC cars only)" "Block,Stream"
textline " "
bitfld.long 0x00 2. " HR ,Broadcast host response (MMC cars only)" "Disabled,Enabled"
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
else
bitfld.long 0x00 1. " INIT ,Send initialization stream(all cards)" "Not sent,Sent"
endif
sif (cpuis("AM335*"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x00 0. " OD ,Card open drain mode (MMC cars only)" "Disabled,Enabled"
endif
line.long 0x04 "SD_PWCNT,Power Counter Register"
hexmask.long.word 0x04 0.--15. 1. " PWRCNT ,Power counter"
rgroup.long 0x200++0x3
line.long 0x00 "SD_SDMASA,SDMA System Address Register"
if (((d.l(ad:0x48060000+0x20c))&0x20)==0x20)
group.long 0x204++0x3
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
hexmask.long.word 0x00 16.--31. 1. " NBLK ,Blocks count for current transfer"
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
else
group.long 0x204++0x3
line.long 0x00 "SD_BLK,Transfer Length Configuration Register"
hexmask.long.word 0x00 0.--11. 1. " BLEN ,Transfer block size"
endif
group.long 0x208++0x7
line.long 0x00 "SD_ARG,Command Argument Register"
line.long 0x04 "SD_CMD,Command and Transfer Mode Register"
bitfld.long 0x04 24.--29. " INDEX ,Command number sent to card" "Cmd0 or acmd0,Cmd1 or acmd1,Cmd2 or acmd2,Cmd3 or acmd3,Cmd4 or acmd4,Cmd5 or acmd5,Cmd6 or acmd6,Cmd7 or acmd7,Cmd8 or acmd8,Cmd9 or acmd9,Cmd10 or acmd10,Cmd11 or acmd11,Cmd12 or acmd12,Cmd13 or acmd13,Cmd14 or acmd14,Cmd15 or acmd15,Cmd16 or acmd16,Cmd17 or acmd17,Cmd18 or acmd18,Cmd19 or acmd19,Cmd20 or acmd20,Cmd21 or acmd21,Cmd22 or acmd22,Cmd23 or acmd23,Cmd24 or acmd24,Cmd25 or acmd25,Cmd26 or acmd26,Cmd27 or acmd27,Cmd28 or acmd28,Cmd29 or acmd29,Cmd30 or acmd30,Cmd31 or acmd31,Cmd32 or acmd32,Cmd33 or acmd33,Cmd34 or acmd34,Cmd35 or acmd35,Cmd36 or acmd36,Cmd37 or acmd37,Cmd38 or acmd38,Cmd39 or acmd39,Cmd40 or acmd40,Cmd41 or acmd41,Cmd42 or acmd42,Cmd43 or acmd43,Cmd44 or acmd44,Cmd45 or acmd45,Cmd46 or acmd46,Cmd47 or acmd47,Cmd48 or acmd48,Cmd49 or acmd49,Cmd50 or acmd50,Cmd51 or acmd51,Cmd52 or acmd52,Cmd53 or acmd53,Cmd54 or acmd54,Cmd55 or acmd55,Cmd56 or acmd56,Cmd57 or acmd57,Cmd58 or acmd58,Cmd59 or acmd59,Cmd60 or acmd60,Cmd61 or acmd61,Cmd62 or acmd62,Cmd63 or acmd63"
bitfld.long 0x04 22.--23. " CMD_TYPE ,Command type" "Other,Bus suspend,Function select,I/O Abort"
bitfld.long 0x04 21. " DP ,Data present select" "No data,Present"
textline " "
bitfld.long 0x04 20. " CICE ,Command index check enable" "Disabled,Enabled"
bitfld.long 0x04 19. " CCCE ,Command CRC check enable" "Disabled,Enabled"
bitfld.long 0x04 16.--17. " RSP_TYPE ,Response type" "No response,136 bits,48 bits,48 bits (busy)"
textline " "
bitfld.long 0x04 5. " MSBS ,Multi/Single block select" "Single,Multi"
bitfld.long 0x04 4. " DDIR ,Data transfer direction" "Write,Read"
bitfld.long 0x04 2. " ACEN ,Auto CMD12 Enable (SD cards only)" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " BCE ,Block Count Enable (Multiple block transfers only)" "Disabled,Enabled"
bitfld.long 0x04 0. " DE ,DMA Enable" "Disabled,Enabled"
rgroup.long 0x210++0xf
line.long 0x00 "SD_RSP10,Command Response 0 and 1 Register"
hexmask.long.word 0x00 16.--31. 1. " RSP1 ,Command Response[31:16]"
hexmask.long.word 0x00 0.--15. 1. " RSP0 ,Command Response[15:0]"
line.long 0x04 "SD_RSP32,Command Response 2 and 3 Register"
hexmask.long.word 0x04 16.--31. 1. " RSP3 ,Command Response[63:48]"
hexmask.long.word 0x04 0.--15. 1. " RSP2 ,Command Response[47:32]"
line.long 0x08 "SD_RSP54,Command Response 4 and 5 Register"
hexmask.long.word 0x08 16.--31. 1. " RSP5 ,Command Response[95:80]"
hexmask.long.word 0x08 0.--15. 1. " RSP4 ,Command Response[79:64]"
line.long 0x0c "SD_RSP76,Command Response 6 and 7 Register"
hexmask.long.word 0x0c 16.--31. 1. " RSP7 ,Command Response[127:112]"
hexmask.long.word 0x0c 0.--15. 1. " RSP6 ,Command Response[111:96]"
width 17.
group.long 0x220++0x3
line.long 0x00 "SD_DATA,Data Register"
if (((d.l(ad:0x48060000+0x12c))&0x180)==0x180)
rgroup.long 0x224++0x3
line.long 0x00 "SD_PSTATE,Present State Register"
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
textline " "
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
textline " "
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
bitfld.long 0x00 16. " CINS ,Detect card" "Detected,Not detected"
textline " "
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
textline " "
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
textline " "
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x100)
rgroup.long 0x224++0x3
line.long 0x00 "SD_PSTATE,Present State Register"
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
textline " "
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Not protected,Protected"
textline " "
bitfld.long 0x00 18. " CDPL ,Card detect pin level (SDIO cards only)" "1,0"
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
textline " "
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
textline " "
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
textline " "
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
elif (((d.l(ad:0x48060000+0x12c))&0x180)==0x80)
rgroup.long 0x224++0x3
line.long 0x00 "SD_PSTATE,Present State Register"
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
textline " "
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
textline " "
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
bitfld.long 0x00 16. " CI ,Detect card" "Detected,Not detected"
textline " "
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
textline " "
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
textline " "
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
else
rgroup.long 0x224++0x3
line.long 0x00 "SD_PSTATE,Present State Register"
bitfld.long 0x00 24. " CLEV ,SD_CMD line signal level" "0,1"
bitfld.long 0x00 23. " DLEV[3] ,SD_DAT[3] line signal level" "0,1"
bitfld.long 0x00 22. " DLEV[2] ,SD_DAT[2] line signal level" "0,1"
textline " "
bitfld.long 0x00 21. " DLEV[1] ,SD_DAT[1] line signal level" "0,1"
bitfld.long 0x00 20. " DLEV[0] ,SD_DAT[0] line signal level" "0,1"
bitfld.long 0x00 19. " WP ,Write Protect (SDIO cards only)" "Protected,Not protected"
textline " "
bitfld.long 0x00 18. " CDPL ,Card detect pin level(SDIO cards only)" "1,0"
bitfld.long 0x00 17. " CSS ,Card state stable" "Reset or debouncing,Stable"
bitfld.long 0x00 16. " CINS ,Detect card" "Not detected,Detected"
textline " "
bitfld.long 0x00 11. " BRE ,Buffer read enable" "Disabled,Enabled"
bitfld.long 0x00 10. " BWE ,Buffer write enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RTA ,Read transfer active" "No data,On-going"
textline " "
bitfld.long 0x00 8. " WTA ,Write transfer active" "No data,On-going"
bitfld.long 0x00 2. " DLA ,SD_DAT line active" "Inactive,Active"
bitfld.long 0x00 1. " DATI ,Issue a command using SD_DAT" "Allowed,Not allowed"
textline " "
bitfld.long 0x00 0. " CMDI ,Issue a command using SD_CMD" "Allowed,Not allowed"
endif
group.long 0x228++0x13
line.long 0x00 "SD_HCTL,Host Control Register"
bitfld.long 0x00 27. " OBWE ,Wake-up event enable for OBI" "Disabled,Enabled"
bitfld.long 0x00 26. " REM ,Wake-up event enable on SD card removal" "Disabled,Enabled"
bitfld.long 0x00 25. " INS ,Wake-up event enable on SD card insertion" "Disabled,Enabled"
textline " "
bitfld.long 0x00 24. " IWE ,Wake-up event enable on SD card interrupt" "Disabled,Enabled"
bitfld.long 0x00 19. " IBG ,Interrupt block at gap (in 4-bit mode only)" "Disabled,Enabled"
bitfld.long 0x00 18. " RWC ,Read wait control (SDIO cards)" "Disabled,Enabled"
textline " "
bitfld.long 0x00 17. " CR ,Transfer continue request" "No affect,Restart"
bitfld.long 0x00 16. " SBGR ,Stop at block gap request" "Transfer mode,Stopped"
bitfld.long 0x00 9.--11. " SDVS ,SD bus voltage select" "Reserved,Reserved,Reserved,Reserved,Reserved,1.8V,3.0V,3.3V"
textline " "
bitfld.long 0x00 8. " SDBP ,SD bus power" "Off,On"
bitfld.long 0x00 7. " CDSS ,Card detect signal selection" "SDCD,CDTL"
bitfld.long 0x00 6. " CDTL ,Card Detect Test Level" "Not detected,Detected"
textline " "
bitfld.long 0x00 3.--4. " DMAS ,DMA Select" "Reserved,Reserved,32-bit ADMA2,?..."
bitfld.long 0x00 2. " HSPE ,High speed enable" "Normal,High"
bitfld.long 0x00 1. " DTW ,Data transfer width" "1-bit,4-bit"
line.long 0x04 "SD_SYSCTL,SD System Control Register"
bitfld.long 0x04 26. " SRD ,Software reset for SD_DAT line" "No reset,Reset"
bitfld.long 0x04 25. " SRC ,Software reset for SD_CMD line" "No reset,Reset"
bitfld.long 0x04 24. " SRA ,Software reset for all" "No reset,Reset"
textline " "
bitfld.long 0x04 16.--19. " DTO ,Data timeout counter value and busy timeout" "TCFx2^13,TCFx2^14,TCFx2^15,TCFx2^16,TCFx2^17,TCFx2^18,TCFx2^19,TCFx2^20,TCFx2^21,TCFx2^22,TCFx2^23,TCFx2^24,TCFx2^25,TCFx2^26,TCFx2^27,?..."
hexmask.long.word 0x04 6.--15. 1. " CLKD ,Clock frequency select"
bitfld.long 0x04 2. " CEN ,Clock enable" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
else
bitfld.long 0x04 1. " ICS ,Internal clock stable status" "Not stable,Stable"
endif
bitfld.long 0x04 0. " ICE ,Internal clock enable" "Disabled,Enabled"
line.long 0x08 "SD_STAT,Interrupt Status Register"
eventfld.long 0x08 29. " BADA ,Bad access to data space interrupt" "No interrupt,Interrupt"
eventfld.long 0x08 28. " CERR ,Card error" "No interrupt,Interrupt"
eventfld.long 0x08 25. " ADMAE ,ADMA error" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 24. " ACE ,Auto CMD12 error" "No interrupt,Interrupt"
eventfld.long 0x08 22. " DEB ,Data end bit error" "No interrupt,Interrupt"
eventfld.long 0x08 21. " DCRC ,Data CRC error" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 20. " DTO ,Data timeout error" "No interrupt,Interrupt"
eventfld.long 0x08 19. " CIE ,Command index error" "No interrupt,Interrupt"
eventfld.long 0x08 18. " CEB ,Command end bit error" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 17. " CCRC ,Command CRC error" "No interrupt,Interrupt"
eventfld.long 0x08 16. " CTO ,Command timeout error" "No interrupt,Interrupt"
sif (cpuis("DRA62*")||cpuis("AM355*"))
rbitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
rbitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
else
bitfld.long 0x08 15. " ERRI ,Error interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 10. " BSR ,Boot status received interrupt" "No interrupt,Interrupt"
eventfld.long 0x08 9. " OBI ,Out of band interrupt" "No interrupt,Interrupt"
bitfld.long 0x08 8. " CIRQ ,Card interrupt" "No interrupt,Interrupt"
endif
textline " "
eventfld.long 0x08 7. " CREM ,Card removal" "No interrupt,Interrupt"
eventfld.long 0x08 6. " CINS ,Card insertion" "No interrupt,Interrupt"
eventfld.long 0x08 5. " BRR ,Buffer read ready" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 4. " BWR ,Buffer write ready" "No interrupt,Interrupt"
eventfld.long 0x08 3. " DMA ,DMA interrupt" "No interrupt,Interrupt"
eventfld.long 0x08 2. " BGE ,Block gap event" "No interrupt,Interrupt"
textline " "
eventfld.long 0x08 1. " TC ,Transfer completed" "No interrupt,Interrupt"
eventfld.long 0x08 0. " CC ,Command completed" "No interrupt,Interrupt"
width 17.
line.long 0x0c "SD_IE,Interrupt SD Enable Register"
bitfld.long 0x0c 29. " BADA_ENABLE ,Bad access to data space interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 28. " CERR_ENABLE ,Card error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 25. " ADMA_ENABLE ,ADMA error interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 24. " ACE_ENABLE ,Auto CMD12 error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 22. " DEB_ENABLE ,Data end bit error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 21. " DCRC_ENABLE ,Data CRC error interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 20. " DTO_ENABLE ,Data timeout error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 19. " CIE_ENABLE ,Command index error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 18. " CEB_ENABLE ,Command end bit error interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 17. " CCRC_ENABLE ,Command CRC error interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 16. " CTO_ENABLE ,Command timeout error interrupt enable" "Masked,Enabled"
sif (cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x0c 15. " NULL ,Null" "0,1"
else
bitfld.long 0x0c 15. " NULL ,Null" "0,1"
endif
textline " "
bitfld.long 0x0c 10. " BSR_ENABLE ,Boot status received interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 9. " OBI_ENABLE ,Out of band interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 8. " CIRQ_ENABLE ,Card interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 7. " CREM_ENABLE ,Card removal interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 6. " CINS_ENABLE ,Card insertion interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 5. " BRR_ENABLE ,Buffer read ready interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 4. " BWR_ENABLE ,Buffer write ready interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 3. " DMA_ENABLE ,DMA interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 2. " BGE_ENABLE ,Block gap event interrupt enable" "Masked,Enabled"
textline " "
bitfld.long 0x0c 1. " TC_ENABLE ,Transfer completed interrupt enable" "Masked,Enabled"
bitfld.long 0x0c 0. " CC_ENABLE ,Command completed interrupt enable" "Masked,Enabled"
line.long 0x10 "SD_ISE,Interrupt Signal Enable Register"
bitfld.long 0x10 29. " BADA_SIGEN ,Bad access to data space signal status enable" "Disabled,Enabled"
bitfld.long 0x10 28. " CERR_SIGEN ,Card error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 25. " ADMA_SIGEN ,ADMA error signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 24. " ACE_SIGEN ,Auto CMD12 error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 22. " DEB_SIGEN ,Data end bit error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 21. " DCRC_SIGEN ,Data CRC error signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 20. " DTO_SIGEN ,Data timeout error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 19. " CIE_SIGEN ,Command index error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 18. " CEB_SIGEN ,Command end bit error signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 17. " CCRC_SIGEN ,Command CRC error signal status enable" "Disabled,Enabled"
bitfld.long 0x10 16. " CTO_SIGEN ,Command timeout error signal status enable" "Disabled,Enabled"
sif (cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x10 15. " NULL ,Null" "0,1"
else
bitfld.long 0x10 15. " NULL ,Null" "0,1"
endif
textline " "
bitfld.long 0x10 10. " BSR_SIGEN ,Boot status received signal status enable" "Disabled,Enabled"
bitfld.long 0x10 9. " OBI_SIGEN ,Out of band signal status enable" "Disabled,Enabled"
bitfld.long 0x10 8. " CIRQ_SIGEN ,Card interrupt signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 7. " CREM_SIGEN ,Card removal signal status enable" "Disabled,Enabled"
bitfld.long 0x10 6. " CINS_SIGEN ,Card insertion signal status enable" "Disabled,Enabled"
bitfld.long 0x10 5. " BRR_SIGEN ,Buffer read ready signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 4. " BWR_SIGEN ,Buffer write ready signal status enable" "Disabled,Enabled"
bitfld.long 0x10 3. " DMA_SIGEN ,DMA signal status enable" "Disabled,Enabled"
bitfld.long 0x10 2. " BGE_SIGEN ,Block gap event signal status enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 1. " TC_SIGEN ,Transfer completed signal status enable" "Disabled,Enabled"
bitfld.long 0x10 0. " CC_SIGEN ,Command completed signal status enable" "Disabled,Enabled"
width 17.
if ((((d.l(ad:(ad:0x48060000+0x20c)))&0x4)==0x4)&&(((d.l(ad:(ad:0x48060000+0x230)))&0x1000000)==0x1000000))
rgroup.long 0x23c++0x3
line.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
bitfld.long 0x00 7. " CNI ,Command not issue by Auto CMD12 error" "No error,Not issued"
bitfld.long 0x00 4. " ACIE ,Auto CMD12 index error" "No error,Error"
textline " "
bitfld.long 0x00 3. " ACEB ,Auto CMD12 end bit error" "No error,Error"
bitfld.long 0x00 2. " ACCE ,Auto CMD12 CRC error" "No error,Error"
textline " "
bitfld.long 0x00 1. " ACTO ,Auto CMD12 timeout error" "No error,Error"
bitfld.long 0x00 0. " ACNE ,Auto CMD12 not executed" "Executed,Not executed"
else
hgroup.long 0x23c++0x3
hide.long 0x00 "SD_AC12,AutoCMD12 Error Status Register"
endif
group.long 0x240++0x3
line.long 0x00 "SD_CAPA,Capabilities Register"
bitfld.long 0x00 28. " 64BIT ,64 Bit System Bus Support" "32-bit,64-bit"
bitfld.long 0x00 26. " VS18 ,Voltage support 1.8 V" "Not supported,Supported"
textline " "
bitfld.long 0x00 25. " VS30 ,Voltage support 3.0 V" "Not supported,Supported"
bitfld.long 0x00 24. " VS33 ,Voltage support 3.3 V" "Not supported,Supported"
textline " "
sif (cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
rbitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
textline " "
rbitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
rbitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
textline " "
rbitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
rbitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
rbitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
rbitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
else
bitfld.long 0x00 23. " SRS ,Suspend/resume support (SDIO cards only)" "Not supported,Supported"
bitfld.long 0x00 22. " DS ,DMA support" "Not supported,Supported"
textline " "
bitfld.long 0x00 21. " HSS ,High speed support" "Not supported,Supported"
bitfld.long 0x00 19. " AD2S ,ADMA2 support" "Not supported,Supported"
textline " "
bitfld.long 0x00 16.--17. " MBL ,Maximum block length" "512 bytes,1024 bytes,2048 bytes,?..."
bitfld.long 0x00 8.--13. " BCF ,Base clock frequency for clock provided to the card" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 7. " TCU ,Timeout clock unit" "kHz,MHz"
bitfld.long 0x00 0.--5. " TCF ,Timeout clock frequency" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
endif
sif (cpuis("DRA62*"))
hgroup.long 0x248++0x3
hide.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
else
group.long 0x248++0x3
line.long 0x00 "SD_CUR_CAPA,Maximum Current Capabilities Register"
hexmask.long.byte 0x00 16.--23. 1. " CUR_1V8 ,Maximum current for 1.8 V"
hexmask.long.byte 0x00 8.--15. 1. " CUR_3V0 ,Maximum current for 3.0 V"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " CUR_3V3 ,Maximum current for 3.3 V"
endif
wgroup.long 0x250++0x3
line.long 0x00 "SD_FE,Force Event Register for Error Interrupt Status"
bitfld.long 0x00 29. " FE_BADA ,Force Event bad acces to data space interrupt" "No effect,Force"
bitfld.long 0x00 28. " FE_CERR ,Force Event card error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 25. " FE_ADMAE ,Force Event ADMA error interrupt" "No effect,Force"
bitfld.long 0x00 24. " FE_ACE ,Force Event Auto CMD12 error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 22. " FE_DEB ,Force Event Data end bit error interrupt" "No effect,Force"
bitfld.long 0x00 21. " FE_DCRC ,Force Event Data CRC error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 20. " FE_DTO ,Force Event Data timeout error interrupt" "No effect,Force"
bitfld.long 0x00 19. " FE_CIE ,Force Event Command index error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 18. " FE_CEB ,Force Event Command end bit error interrupt" "No effect,Force"
bitfld.long 0x00 17. " FE_CCRC ,Force Event Command CRC error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 16. " FE_CTO ,Force Event Command timeout error interrupt" "No effect,Force"
bitfld.long 0x00 7. " FE_CNI ,Force Event Command not issue by AUTOCMD12 index error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 4. " FE_ACIE ,Force Event AutoCMD12 index error interrupt" "No effect,Force"
bitfld.long 0x00 3. " FE_ACEB ,Force Event AutoCMD12 end bit error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 2. " FE_ACCE ,Force Event AutoCMD12 CRC error interrupt" "No effect,Force"
bitfld.long 0x00 1. " FE_ACTO ,Force Event AutoCMD12 timeout error interrupt" "No effect,Force"
textline " "
bitfld.long 0x00 0. " FE_ACNE ,Force Event AutoCMD12 not executed interrupt" "No effect,Force"
group.long 0x254++0x7
line.long 0x00 "SD_ADMAES,ADMA Error Status Register"
bitfld.long 0x00 2. " LME ,ADMA length mismatch error" "No error,Error"
bitfld.long 0x00 0.--1. " AES ,ADMA Error State" "Stop DMA,Stop DMA,Reserved,Transfer Data"
line.long 0x04 "SD_ADMASAL,ADMA System Address Low Bits Register"
sif (cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
rgroup.long 0x25C++0x03
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
else
group.long 0x25C++0x03
line.long 0x00 "SD_ADMASAH,ADMA System Address High Bits Register"
endif
rgroup.long 0x2fc++0x3
line.long 0x00 "SD_REV,Versions Register"
hexmask.long.byte 0x00 24.--31. 1. " VREV ,Vendor Version Number"
hexmask.long.byte 0x00 16.--23. 1. " SREV ,Specification Version Number"
bitfld.long 0x00 0. " SIS ,Slot Interrupt Status" "Low,High"
width 0xb
tree.end
tree.open "McASP (Multichannel Audio Serial Port)"
tree "McASP 0"
base ad:0x48038000
width 11.
tree "General Registers"
rgroup.long 0x00++0x3
line.long 0x00 "REV,Revision Identification Register"
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
width 18.
group.long 0x04++0x03
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
endif
width 11.
group.long 0x10++0x3
line.long 0x00 "PFUNC,Pin Function Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "PDIR,Pin Direction Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
group.long 0x18++0x3
line.long 0x00 "PDOUT,Pin Data Output Register"
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
textline " "
endif
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
rgroup.long 0x1c++0x3
line.long 0x00 "PDIN,Pin Data Input Register"
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
group.long 0x44++0x3
line.long 0x00 "GBLCTL,Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x48++0x3
line.long 0x00 "AMUTE,Audio Mute Control Register"
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
else
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
endif
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
group.long 0x4c++0x3
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
group.long 0x50++0x3
line.long 0x00 "DITCTL,Digital Mode Control Register"
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
tree.end
tree "Receive Registers"
group.long 0x60++0x3
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
endif
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x64++0x3
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
group.long 0x68++0x3
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0x6c++0x3
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
group.long 0x70++0x3
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x74++0x3
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
group.long 0x78++0x3
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
group.long 0x7c++0x3
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
group.long 0x80++0x3
line.long 0x00 "RXSTAT,Receiver Status Register"
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
rgroup.long 0x84++0x3
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
group.long 0x88++0x7
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
tree.end
tree "Transmit Registers"
group.long 0xa0++0x3
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
endif
group.long 0xa4++0x3
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
group.long 0xa8++0x3
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0xac++0x3
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
group.long 0xb0++0x3
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
textline " "
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0xb4++0x3
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
group.long 0xb8++0x3
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
group.long 0xbc++0x3
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
group.long 0xc0++0x3
line.long 0x00 "TXSTAT,Transmitter Status Register"
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
rgroup.long 0xc4++0x3
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
else
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
endif
group.long 0xc8++0x7
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0xD0++0x03
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
endif
tree.end
width 9.
tree "Serializer Control Registers"
group.long 0x180++0x03
line.long 0x00 "SRCTL0,Serializer Control Register 0"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x184++0x03
line.long 0x00 "SRCTL1,Serializer Control Register 1"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x188++0x03
line.long 0x00 "SRCTL2,Serializer Control Register 2"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x18C++0x03
line.long 0x00 "SRCTL3,Serializer Control Register 3"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x190++0x03
line.long 0x00 "SRCTL4,Serializer Control Register 4"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x194++0x03
line.long 0x00 "SRCTL5,Serializer Control Register 5"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
tree.end
tree "DIT Channel Registers"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
group.long 0x104++0x03
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
group.long 0x108++0x03
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
group.long 0x10C++0x03
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
group.long 0x110++0x03
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
group.long 0x114++0x03
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
group.long 0x118++0x03
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
group.long 0x11C++0x03
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
group.long 0x120++0x03
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
group.long 0x124++0x03
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
group.long 0x128++0x03
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
group.long 0x12C++0x03
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
group.long 0x130++0x03
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
group.long 0x134++0x03
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
group.long 0x138++0x03
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
group.long 0x13C++0x03
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
group.long 0x140++0x03
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
group.long 0x144++0x03
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
group.long 0x148++0x03
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
group.long 0x14C++0x03
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
group.long 0x150++0x03
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
group.long 0x154++0x03
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
group.long 0x158++0x03
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
group.long 0x15C++0x03
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
tree.end
tree "Transmit Buffer Registers"
group.long 0x200++0x03
line.long 0x00 "XBUF0,Transmit Buffer Register"
group.long 0x204++0x03
line.long 0x00 "XBUF1,Transmit Buffer Register"
group.long 0x208++0x03
line.long 0x00 "XBUF2,Transmit Buffer Register"
group.long 0x20C++0x03
line.long 0x00 "XBUF3,Transmit Buffer Register"
group.long 0x210++0x03
line.long 0x00 "XBUF4,Transmit Buffer Register"
group.long 0x214++0x03
line.long 0x00 "XBUF5,Transmit Buffer Register"
tree.end
tree "Receive Buffer Registers"
group.long 0x280++0x03
line.long 0x00 "RBUF0,Receive Buffer Register"
group.long 0x284++0x03
line.long 0x00 "RBUF1,Receive Buffer Register"
group.long 0x288++0x03
line.long 0x00 "RBUF2,Receive Buffer Register"
group.long 0x28C++0x03
line.long 0x00 "RBUF3,Receive Buffer Register"
group.long 0x290++0x03
line.long 0x00 "RBUF4,Receive Buffer Register"
group.long 0x294++0x03
line.long 0x00 "RBUF5,Receive Buffer Register"
tree.end
tree "McASP AFIFO Registers"
group.long 0x1000++0x3
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
rgroup.long 0x1004++0x3
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
group.long 0x1008++0x3
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
else
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
endif
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
rgroup.long 0x100c++0x3
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
tree.end
width 0xb
tree.end
tree "McASP 1"
base ad:0x4803c000
width 11.
tree "General Registers"
rgroup.long 0x00++0x3
line.long 0x00 "REV,Revision Identification Register"
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
width 18.
group.long 0x04++0x03
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
endif
width 11.
group.long 0x10++0x3
line.long 0x00 "PFUNC,Pin Function Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "PDIR,Pin Direction Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
group.long 0x18++0x3
line.long 0x00 "PDOUT,Pin Data Output Register"
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
textline " "
endif
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
rgroup.long 0x1c++0x3
line.long 0x00 "PDIN,Pin Data Input Register"
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
group.long 0x44++0x3
line.long 0x00 "GBLCTL,Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x48++0x3
line.long 0x00 "AMUTE,Audio Mute Control Register"
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
else
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
endif
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
group.long 0x4c++0x3
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
group.long 0x50++0x3
line.long 0x00 "DITCTL,Digital Mode Control Register"
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
tree.end
tree "Receive Registers"
group.long 0x60++0x3
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
endif
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x64++0x3
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
group.long 0x68++0x3
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0x6c++0x3
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
group.long 0x70++0x3
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x74++0x3
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
group.long 0x78++0x3
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
group.long 0x7c++0x3
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
group.long 0x80++0x3
line.long 0x00 "RXSTAT,Receiver Status Register"
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
rgroup.long 0x84++0x3
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
group.long 0x88++0x7
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
tree.end
tree "Transmit Registers"
group.long 0xa0++0x3
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
endif
group.long 0xa4++0x3
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
group.long 0xa8++0x3
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0xac++0x3
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
group.long 0xb0++0x3
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
textline " "
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0xb4++0x3
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
group.long 0xb8++0x3
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
group.long 0xbc++0x3
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
group.long 0xc0++0x3
line.long 0x00 "TXSTAT,Transmitter Status Register"
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
rgroup.long 0xc4++0x3
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
else
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
endif
group.long 0xc8++0x7
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0xD0++0x03
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
endif
tree.end
width 9.
tree "Serializer Control Registers"
group.long 0x180++0x03
line.long 0x00 "SRCTL0,Serializer Control Register 0"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x184++0x03
line.long 0x00 "SRCTL1,Serializer Control Register 1"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x188++0x03
line.long 0x00 "SRCTL2,Serializer Control Register 2"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x18C++0x03
line.long 0x00 "SRCTL3,Serializer Control Register 3"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x190++0x03
line.long 0x00 "SRCTL4,Serializer Control Register 4"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x194++0x03
line.long 0x00 "SRCTL5,Serializer Control Register 5"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
tree.end
tree "DIT Channel Registers"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
group.long 0x104++0x03
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
group.long 0x108++0x03
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
group.long 0x10C++0x03
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
group.long 0x110++0x03
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
group.long 0x114++0x03
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
group.long 0x118++0x03
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
group.long 0x11C++0x03
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
group.long 0x120++0x03
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
group.long 0x124++0x03
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
group.long 0x128++0x03
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
group.long 0x12C++0x03
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
group.long 0x130++0x03
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
group.long 0x134++0x03
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
group.long 0x138++0x03
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
group.long 0x13C++0x03
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
group.long 0x140++0x03
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
group.long 0x144++0x03
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
group.long 0x148++0x03
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
group.long 0x14C++0x03
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
group.long 0x150++0x03
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
group.long 0x154++0x03
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
group.long 0x158++0x03
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
group.long 0x15C++0x03
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
tree.end
tree "Transmit Buffer Registers"
group.long 0x200++0x03
line.long 0x00 "XBUF0,Transmit Buffer Register"
group.long 0x204++0x03
line.long 0x00 "XBUF1,Transmit Buffer Register"
group.long 0x208++0x03
line.long 0x00 "XBUF2,Transmit Buffer Register"
group.long 0x20C++0x03
line.long 0x00 "XBUF3,Transmit Buffer Register"
group.long 0x210++0x03
line.long 0x00 "XBUF4,Transmit Buffer Register"
group.long 0x214++0x03
line.long 0x00 "XBUF5,Transmit Buffer Register"
tree.end
tree "Receive Buffer Registers"
group.long 0x280++0x03
line.long 0x00 "RBUF0,Receive Buffer Register"
group.long 0x284++0x03
line.long 0x00 "RBUF1,Receive Buffer Register"
group.long 0x288++0x03
line.long 0x00 "RBUF2,Receive Buffer Register"
group.long 0x28C++0x03
line.long 0x00 "RBUF3,Receive Buffer Register"
group.long 0x290++0x03
line.long 0x00 "RBUF4,Receive Buffer Register"
group.long 0x294++0x03
line.long 0x00 "RBUF5,Receive Buffer Register"
tree.end
tree "McASP AFIFO Registers"
group.long 0x1000++0x3
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
rgroup.long 0x1004++0x3
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
group.long 0x1008++0x3
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
else
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
endif
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
rgroup.long 0x100c++0x3
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
tree.end
width 0xb
tree.end
tree "McASP 2"
base ad:0x48050000
width 11.
tree "General Registers"
rgroup.long 0x00++0x3
line.long 0x00 "REV,Revision Identification Register"
sif (!cpuis("DRA62*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
width 18.
group.long 0x04++0x03
line.long 0x00 "PWRIDLESYSCONFIG,Power Idle SYSCONFIG"
endif
width 11.
group.long 0x10++0x3
line.long 0x00 "PFUNC,Pin Function Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "McASP,GPIO"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "McASP,GPIO"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "McASP,GPIO"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "McASP,GPIO"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "McASP,GPIO"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "McASP,GPIO"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "McASP,GPIO"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "McASP,GPIO"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "McASP,GPIO"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "McASP,GPIO"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "McASP,GPIO"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "McASP,GPIO"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "McASP,GPIO"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "McASP,GPIO"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "McASP,GPIO"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "McASP,GPIO"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "McASP,GPIO"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "McASP,GPIO"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "McASP,GPIO"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "McASP,GPIO"
group.long 0x14++0x3
line.long 0x00 "PDIR,Pin Direction Register"
bitfld.long 0x00 31. " AFSR ,AFSR pin function" "Input,Output"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR pin function" "Input,Output"
bitfld.long 0x00 29. " ACLKR ,ACLKR pin function" "Input,Output"
bitfld.long 0x00 28. " AFSX ,AFSX pin function" "Input,Output"
textline " "
bitfld.long 0x00 27. " AHCLKX ,AHCLKX pin function" "Input,Output"
bitfld.long 0x00 26. " ACLKX ,ACLKX pin function" "Input,Output"
bitfld.long 0x00 25. " AMUTE ,AMUTE pin function" "Input,Output"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] pin function" "Input,Output"
bitfld.long 0x00 14. " AXR14 ,AXR[14] pin function" "Input,Output"
bitfld.long 0x00 13. " AXR13 ,AXR[13] pin function" "Input,Output"
bitfld.long 0x00 12. " AXR12 ,AXR[12] pin function" "Input,Output"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] pin function" "Input,Output"
bitfld.long 0x00 10. " AXR10 ,AXR[10] pin function" "Input,Output"
bitfld.long 0x00 9. " AXR9 ,AXR[9] pin function" "Input,Output"
bitfld.long 0x00 8. " AXR8 ,AXR[8] pin function" "Input,Output"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] pin function" "Input,Output"
bitfld.long 0x00 6. " AXR6 ,AXR[6] pin function" "Input,Output"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] pin function" "Input,Output"
bitfld.long 0x00 4. " AXR4 ,AXR[4] pin function" "Input,Output"
bitfld.long 0x00 3. " AXR3 ,AXR[3] pin function" "Input,Output"
bitfld.long 0x00 2. " AXR2 ,AXR[2] pin function" "Input,Output"
textline " "
bitfld.long 0x00 1. " AXR1 ,AXR[1] pin function" "Input,Output"
bitfld.long 0x00 0. " AXR0 ,AXR[0] pin function" "Input,Output"
group.long 0x18++0x3
line.long 0x00 "PDOUT,Pin Data Output Register"
setclrfld.long 0x00 31. 0x04 31. 0x08 31. " AFSR_set/clr ,Drive on AFSR" "Low,High"
setclrfld.long 0x00 30. 0x04 30. 0x08 30. " AHCLKR_set/clr ,Drive on AHCLKR" "Low,High"
setclrfld.long 0x00 29. 0x04 29. 0x08 29. " ACLKR_set/clr ,Drive on ACLKR" "Low,High"
setclrfld.long 0x00 28. 0x04 28. 0x08 28. " AFSX_set/clr ,Drive on AFSX" "Low,High"
textline " "
setclrfld.long 0x00 27. 0x04 27. 0x08 27. " AHCLKX_set/clr ,Drive on AHCLKX" "Low,High"
setclrfld.long 0x00 26. 0x04 26. 0x08 26. " ACLKX_set/clr ,Drive on ACLKX" "Low,High"
setclrfld.long 0x00 25. 0x04 25. 0x08 25. " AMUTE_set/clr ,Drive on AMUTE" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
setclrfld.long 0x00 15. 0x05 15. 0x08 15. " AXR15_set/clr ,Drive on AXR[15]" "Low,High"
setclrfld.long 0x00 14. 0x04 14. 0x08 14. " AXR14_set/clr ,Drive on AXR[14]" "Low,High"
setclrfld.long 0x00 13. 0x04 13. 0x08 13. " AXR13_set/clr ,Drive on AXR[13]" "Low,High"
setclrfld.long 0x00 12. 0x04 12. 0x08 12. " AXR12_set/clr ,Drive on AXR[12]" "Low,High"
textline " "
setclrfld.long 0x00 11. 0x05 11. 0x08 11. " AXR11_set/clr ,Drive on AXR[11]" "Low,High"
setclrfld.long 0x00 10. 0x04 10. 0x08 10. " AXR10_set/clr ,Drive on AXR[10]" "Low,High"
setclrfld.long 0x00 9. 0x04 9. 0x08 9. " AXR9_set/clr ,Drive on AXR[9]" "Low,High"
setclrfld.long 0x00 8. 0x04 8. 0x08 8. " AXR8_set/clr ,Drive on AXR[8]" "Low,High"
textline " "
setclrfld.long 0x00 7. 0x04 7. 0x08 7. " AXR7_set/clr ,Drive on AXR[7]" "Low,High"
setclrfld.long 0x00 6. 0x04 6. 0x08 6. " AXR6_set/clr ,Drive on AXR[6]" "Low,High"
textline " "
endif
setclrfld.long 0x00 5. 0x05 5. 0x08 5. " AXR5_set/clr ,Drive on AXR[5]" "Low,High"
setclrfld.long 0x00 4. 0x04 4. 0x08 4. " AXR4_set/clr ,Drive on AXR[4]" "Low,High"
setclrfld.long 0x00 3. 0x04 3. 0x08 3. " AXR3_set/clr ,Drive on AXR[3]" "Low,High"
setclrfld.long 0x00 2. 0x04 2. 0x08 2. " AXR2_set/clr ,Drive on AXR[2]" "Low,High"
textline " "
setclrfld.long 0x00 1. 0x04 1. 0x08 1. " AXR1_set/clr ,Drive on AXR[1]" "Low,High"
setclrfld.long 0x00 0. 0x04 0. 0x08 0. " AXR0_set/clr ,Drive on AXR[0]" "Low,High"
rgroup.long 0x1c++0x3
line.long 0x00 "PDIN,Pin Data Input Register"
bitfld.long 0x00 31. " AFSR ,AFSR logic level" "Low,High"
bitfld.long 0x00 30. " AHCLKR ,AHCLKR logic level" "Low,High"
bitfld.long 0x00 29. " ACLKR ,ACLKR logic level" "Low,High"
bitfld.long 0x00 28. " AFSX ,AFSX logic level" "Low,High"
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bitfld.long 0x00 27. " AHCLKX ,AHCLKX logic level" "Low,High"
bitfld.long 0x00 26. " ACLKX ,ACLKX logic level" "Low,High"
bitfld.long 0x00 25. " AMUTE ,AMUTE logic level" "Low,High"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 15. " AXR15 ,AXR[15] logic level" "Low,High"
bitfld.long 0x00 14. " AXR14 ,AXR[14] logic level" "Low,High"
bitfld.long 0x00 13. " AXR13 ,AXR[13] logic level" "Low,High"
bitfld.long 0x00 12. " AXR12 ,AXR[12] logic level" "Low,High"
textline " "
bitfld.long 0x00 11. " AXR11 ,AXR[11] logic level" "Low,High"
bitfld.long 0x00 10. " AXR10 ,AXR[10] logic level" "Low,High"
bitfld.long 0x00 9. " AXR9 ,AXR[9] logic level" "Low,High"
bitfld.long 0x00 8. " AXR8 ,AXR[8] logic level" "Low,High"
textline " "
bitfld.long 0x00 7. " AXR7 ,AXR[7] logic level" "Low,High"
bitfld.long 0x00 6. " AXR6 ,AXR[6] logic level" "Low,High"
textline " "
endif
bitfld.long 0x00 5. " AXR5 ,AXR[5] logic level" "Low,High"
bitfld.long 0x00 4. " AXR4 ,AXR[4] logic level" "Low,High"
bitfld.long 0x00 3. " AXR3 ,AXR[3] logic level" "Low,High"
bitfld.long 0x00 2. " AXR2 ,AXR[2] logic level" "Low,High"
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bitfld.long 0x00 1. " AXR1 ,AXR[1] logic level" "Low,High"
bitfld.long 0x00 0. " AXR0 ,AXR[0] logic level" "Low,High"
group.long 0x44++0x3
line.long 0x00 "GBLCTL,Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Held,Released"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x48++0x3
line.long 0x00 "AMUTE,Audio Mute Control Register"
bitfld.long 0x00 12. " XDMAERR ,Transmit DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 11. " RDMAERR ,Receive DMA Error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCKFAIL ,Transmit clock failure - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 9. " RCKFAIL ,Receive clock failure - AMUTE active enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " XSYNCERR ,Transmit frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 7. " RSYNCERR ,Receive frame sync error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XUNDRN ,Transmit underrun error - AMUTE active enable" "Disabled,Enabled"
bitfld.long 0x00 5. " ROVRN ,Receive underrun error - AMUTE active enable" "Disabled,Enabled"
textline " "
sif (cpuis("DRA62*")||cpuis("AN335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
else
bitfld.long 0x00 4. " INSTAT ,AMUTEIN pin is active" "Inactive,Active"
endif
bitfld.long 0x00 3. " INEN ,Drive AMUTE active when AMUTEIN error is active" "Disabled,Enabled"
bitfld.long 0x00 2. " INPOL ,Audio mute in (AMUTEIN) polarity select" "High,Low"
bitfld.long 0x00 0.--1. " MUTEN ,AMUTE pin enable" "Disabled,Driven high,Driven low,?..."
group.long 0x4c++0x3
line.long 0x00 "DLBCTL,Digital Loopback Control Register"
bitfld.long 0x00 2.--3. " MODE ,Loopback generator mode" "Default,Both sections,?..."
bitfld.long 0x00 1. " ORD ,Loopback order" "Odd,Even"
bitfld.long 0x00 0. " DLBEN ,Loopback mode enable" "Disabled,Enabled"
group.long 0x50++0x3
line.long 0x00 "DITCTL,Digital Mode Control Register"
bitfld.long 0x00 3. " VB ,Valid bit for odd time slots" "0,1"
bitfld.long 0x00 2. " VA ,Valid bit for even time slots" "0,1"
bitfld.long 0x00 0. " DITEN ,DIT mode enable" "Disabled,Enabled"
tree.end
tree "Receive Registers"
group.long 0x60++0x3
line.long 0x00 "RGBLCTLR,Receiver Global Control Register"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
rbitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
rbitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
rbitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Enabled,Disabled"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
endif
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
group.long 0x64++0x3
line.long 0x00 "RXMASK,Receive Format Unit Bit Mask Register"
bitfld.long 0x00 31. " RXMASK31 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " RXMASK30 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " RXMASK29 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " RXMASK28 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " RXMASK27 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " RXMASK26 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " RXMASK25 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " RXMASK24 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " RXMASK23 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " RXMASK22 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " RXMASK21 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " RXMASK20 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " RXMASK19 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " RXMASK18 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " RXMASK17 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " RXMASK16 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " RXMASK15 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " RXMASK14 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " RXMASK13 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " RXMASK12 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " RXMASK11 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " RXMASK10 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " RXMASK9 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " RXMASK8 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " RXMASK7 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " RXMASK6 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " RXMASK5 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " RXMASK4 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " RXMASK3 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " RXMASK2 ,Receive data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " RXMASK1 ,Receive data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " RXMASK0 ,Receive data mask enable" "Masked,Not masked"
group.long 0x68++0x3
line.long 0x00 "RXFMT,Receive Bit Stream Format Register"
bitfld.long 0x00 16.--17. " RDATDLY ,Receive bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " RRVRS ,Receive serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " RPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,RPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " RPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " RSSZ ,Receive slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " RBUSEL ,Selects reads from serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " RROT ,Right-rotation value for receive rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0x6c++0x3
line.long 0x00 "AFSRCTL,Receive Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " RMOD ,Receive frame sync mode select"
bitfld.long 0x00 4. " FRWID ,Receive frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSRM ,Receive frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSRP ,Receive frame sync polarity select" "Rising edge,Falling edge"
group.long 0x70++0x3
line.long 0x00 "ACLKRCTL,Receive Clock Control Register"
bitfld.long 0x00 7. " CLKRP ,Receive bitstream clock polarity select" "Falling edge,Rising edge"
bitfld.long 0x00 5. " CLKRM ,Receive bit clock source" "External,Internal"
bitfld.long 0x00 0.--4. " CLKRDIV ,Receive bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0x74++0x3
line.long 0x00 "AHCLKRCTL,Receive High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKRM ,Receive high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKRP ,Receive bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKRDIV ,Receive high-frequency clock divide ratio"
group.long 0x78++0x3
line.long 0x00 "RXTDM,Receive TDM Time Slot Register"
bitfld.long 0x00 31. " RXTDMS31 ,Receiver mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " RXTDMS30 ,Receiver mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " RXTDMS29 ,Receiver mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " RXTDMS28 ,Receiver mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " RXTDMS27 ,Receiver mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " RXTDMS26 ,Receiver mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " RXTDMS25 ,Receiver mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " RXTDMS24 ,Receiver mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " RXTDMS23 ,Receiver mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " RXTDMS22 ,Receiver mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " RXTDMS21 ,Receiver mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " RXTDMS20 ,Receiver mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " RXTDMS19 ,Receiver mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " RXTDMS18 ,Receiver mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " RXTDMS17 ,Receiver mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " RXTDMS16 ,Receiver mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " RXTDMS15 ,Receiver mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " RXTDMS14 ,Receiver mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " RXTDMS13 ,Receiver mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " RXTDMS12 ,Receiver mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " RXTDMS11 ,Receiver mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " RXTDMS10 ,Receiver mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " RXTDMS9 ,Receiver mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " RXTDMS8 ,Receiver mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " RXTDMS7 ,Receiver mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " RXTDMS6 ,Receiver mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " RXTDMS5 ,Receiver mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " RXTDMS4 ,Receiver mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " RXTDMS3 ,Receiver mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " RXTDMS2 ,Receiver mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " RXTDMS1 ,Receiver mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " RXTDMS0 ,Receiver mode during TDM time slot 0" "Inactive,Active"
group.long 0x7c++0x3
line.long 0x00 "RINTCTL,Receiver Interrupt Control Register"
bitfld.long 0x00 7. " RSTAFRM ,Receive start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " RDATA ,Receive data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RLAST ,Receive last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RDMAERR ,Receive DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCKFAIL ,Receive clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ROVRN ,Receiver overrun interrupt enable" "Disabled,Enabled"
group.long 0x80++0x3
line.long 0x00 "RXSTAT,Receiver Status Register"
bitfld.long 0x00 8. " RERR ,Receiver error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " RDMAERR ,Receive DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " RSTAFRM ,Receive start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " RDATA ,Receive data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " RLAST ,Receive last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " RTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " RCKFAIL ,Receive clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " RSYNCERR ,Unexpected receive frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " ROVRN ,Receiver overrun" "Not occurred,Occurred"
rgroup.long 0x84++0x3
line.long 0x00 "RSLOT,Current Receive TDM Time Slot Register"
hexmask.long.word 0x00 0.--8. 1. " RSLOTCNT ,Current receive time slot count"
group.long 0x88++0x7
line.long 0x00 "RXCLKCHK,Receive Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " RCNT ,Receive clock count value"
hexmask.long.byte 0x00 16.--23. 1. " RMAX ,Receive clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " RMIN ,Receive clock minimum boundary"
bitfld.long 0x00 0.--3. " RPS ,Receive clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "REVTCTL,Receiver DMA Event Control Register"
bitfld.long 0x04 0. " RDATDMA ,Receive data DMA request enable" "Enabled,?..."
tree.end
tree "Transmit Registers"
group.long 0xa0++0x3
line.long 0x00 "XGBLCTL,Transmitter Global Control Register"
bitfld.long 0x00 12. " XFRST ,Transmit frame sync generator reset enable" "Reset,Active"
bitfld.long 0x00 11. " XSMRST ,Transmit state machine reset enable" "Held,Released"
bitfld.long 0x00 10. " XSRCLR ,Transmit serializer clear enable" "Cleared,Active"
textline " "
bitfld.long 0x00 9. " XHCLKRST ,Transmit high-frequency clock divider reset enable" "Reset,Running"
bitfld.long 0x00 8. " XCLKRST ,Transmit clock divider reset enable" "Reset,Running"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
rbitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
rbitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
rbitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
rbitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
else
bitfld.long 0x00 4. " RFRST ,Receive frame sync generator reset enable" "Reset,Active"
textline " "
bitfld.long 0x00 3. " RSMRST ,Receive state machine reset enable" "Enabled,Disabled"
bitfld.long 0x00 2. " RSRCLR ,Receive serializer clear enable" "Cleared,Active"
bitfld.long 0x00 1. " RHCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
textline " "
bitfld.long 0x00 0. " RCLKRST ,Receive high-frequency clock divider reset enable" "Reset,Running"
endif
group.long 0xa4++0x3
line.long 0x00 "TXMASK,Transmit Format Unit Bit Mask Register"
bitfld.long 0x00 31. " TXMASK31 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 30. " TXMASK30 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 29. " TXMASK29 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 28. " TXMASK28 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 27. " TXMASK27 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 26. " TXMASK26 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 25. " TXMASK25 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 24. " TXMASK24 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 23. " TXMASK23 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 22. " TXMASK22 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 21. " TXMASK21 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 20. " TXMASK20 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 19. " TXMASK19 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 18. " TXMASK18 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 17. " TXMASK17 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 16. " TXMASK16 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 15. " TXMASK15 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 14. " TXMASK14 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 13. " TXMASK13 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 12. " TXMASK12 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 11. " TXMASK11 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 10. " TXMASK10 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 9. " TXMASK9 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 8. " TXMASK8 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 7. " TXMASK7 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 6. " TXMASK6 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 5. " TXMASK5 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 4. " TXMASK4 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 3. " TXMASK3 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 2. " TXMASK2 ,Transmit data mask enable" "Masked,Not masked"
textline " "
bitfld.long 0x00 1. " TXMASK1 ,Transmit data mask enable" "Masked,Not masked"
bitfld.long 0x00 0. " TXMASK0 ,Transmit data mask enable" "Masked,Not masked"
group.long 0xa8++0x3
line.long 0x00 "TXFMT,Transmit Bit Stream Format Register"
bitfld.long 0x00 16.--17. " XDATDLY ,Transmit bit delay" "0-bit,1-bit,2-bit,?..."
bitfld.long 0x00 15. " XRVRS ,Transmit serial bitstream order" "LSB first,MSB first"
bitfld.long 0x00 13.--14. " XPAD ,Pad value for extra bits in slot not belonging to the word" "0,1,XPBIT,?..."
textline " "
bitfld.long 0x00 8.--12. " XPBIT ,Extra bit value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 4.--7. " XSSZ ,Transmit slot size" "Reserved,Reserved,Reserved,8-bits,Reserved,12-bits,Reserved,16-bits,Reserved,20-bits,Reserved,24-bits,Reserved,28-bits,Reserved,32-bits"
bitfld.long 0x00 3. " XBUSEL ,Selects writes to serializer buffer XRBUF[n] origins" "DATA port,CFG bus"
textline " "
bitfld.long 0x00 0.--2. " XROT ,Right-rotation value for transmit rotate right format unit" "0 bit,4 bit,8 bit,12 bit,16 bit,20 bit,24 bit,28 bit"
group.long 0xac++0x3
line.long 0x00 "AFSXCTL,Transmit Frame Sync Control Register"
hexmask.long.word 0x00 7.--15. 1. " XMOD ,Transmit frame sync mode select"
bitfld.long 0x00 4. " FXWID ,Transmit frame sync width select" "Bit,Word"
bitfld.long 0x00 1. " FSXM ,Transmit frame sync generation select" "Externally,Internally"
textline " "
bitfld.long 0x00 0. " FSXP ,Transmit frame sync polarity select" "Rising edge,Falling edge"
group.long 0xb0++0x3
line.long 0x00 "ACLKXCTL,Transmit Clock Control Register"
bitfld.long 0x00 7. " CLKXP ,Transmit bitstream clock polarity select" "Rising edge,Falling edge"
bitfld.long 0x00 6. " ASYNC ,Transmit/receive operation asynchronous enable" "Synchronous,Asynchronous"
bitfld.long 0x00 5. " CLKXM ,Transmit bit clock source" "External,Internal"
textline " "
bitfld.long 0x00 0.--4. " CLKXDIV ,Transmit bit clock divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
group.long 0xb4++0x3
line.long 0x00 "AHCLKXCTL,Transmit High-Frequency Clock Control Register"
bitfld.long 0x00 15. " HCLKXM ,Transmit high-frequency clock source" "External,Internal"
bitfld.long 0x00 14. " HCLKXP ,Transmit bitstream high-frequency clock polarity select" "Not inverted,Inverted"
hexmask.long.word 0x00 0.--11. 1. " HCLKXDIV ,Transmit high-frequency clock divide ratio"
group.long 0xb8++0x3
line.long 0x00 "TXTDM,Transmit TDM Time Slot Register"
bitfld.long 0x00 31. " TXTDMS31 ,Transmitter mode during TDM time slot 31" "Inactive,Active"
bitfld.long 0x00 30. " TXTDMS30 ,Transmitter mode during TDM time slot 30" "Inactive,Active"
bitfld.long 0x00 29. " TXTDMS29 ,Transmitter mode during TDM time slot 29" "Inactive,Active"
textline " "
bitfld.long 0x00 28. " TXTDMS28 ,Transmitter mode during TDM time slot 28" "Inactive,Active"
bitfld.long 0x00 27. " TXTDMS27 ,Transmitter mode during TDM time slot 27" "Inactive,Active"
bitfld.long 0x00 26. " TXTDMS26 ,Transmitter mode during TDM time slot 26" "Inactive,Active"
textline " "
bitfld.long 0x00 25. " TXTDMS25 ,Transmitter mode during TDM time slot 25" "Inactive,Active"
bitfld.long 0x00 24. " TXTDMS24 ,Transmitter mode during TDM time slot 24" "Inactive,Active"
bitfld.long 0x00 23. " TXTDMS23 ,Transmitter mode during TDM time slot 23" "Inactive,Active"
textline " "
bitfld.long 0x00 22. " TXTDMS22 ,Transmitter mode during TDM time slot 22" "Inactive,Active"
bitfld.long 0x00 21. " TXTDMS21 ,Transmitter mode during TDM time slot 21" "Inactive,Active"
bitfld.long 0x00 20. " TXTDMS20 ,Transmitter mode during TDM time slot 20" "Inactive,Active"
textline " "
bitfld.long 0x00 19. " TXTDMS19 ,Transmitter mode during TDM time slot 19" "Inactive,Active"
bitfld.long 0x00 18. " TXTDMS18 ,Transmitter mode during TDM time slot 18" "Inactive,Active"
bitfld.long 0x00 17. " TXTDMS17 ,Transmitter mode during TDM time slot 17" "Inactive,Active"
textline " "
bitfld.long 0x00 16. " TXTDMS16 ,Transmitter mode during TDM time slot 16" "Inactive,Active"
bitfld.long 0x00 15. " TXTDMS15 ,Transmitter mode during TDM time slot 15" "Inactive,Active"
bitfld.long 0x00 14. " TXTDMS14 ,Transmitter mode during TDM time slot 14" "Inactive,Active"
textline " "
bitfld.long 0x00 13. " TXTDMS13 ,Transmitter mode during TDM time slot 13" "Inactive,Active"
bitfld.long 0x00 12. " TXTDMS12 ,Transmitter mode during TDM time slot 12" "Inactive,Active"
bitfld.long 0x00 11. " TXTDMS11 ,Transmitter mode during TDM time slot 11" "Inactive,Active"
textline " "
bitfld.long 0x00 10. " TXTDMS10 ,Transmitter mode during TDM time slot 10" "Inactive,Active"
bitfld.long 0x00 9. " TXTDMS9 ,Transmitter mode during TDM time slot 9" "Inactive,Active"
bitfld.long 0x00 8. " TXTDMS8 ,Transmitter mode during TDM time slot 8" "Inactive,Active"
textline " "
bitfld.long 0x00 7. " TXTDMS7 ,Transmitter mode during TDM time slot 7" "Inactive,Active"
bitfld.long 0x00 6. " TXTDMS6 ,Transmitter mode during TDM time slot 6" "Inactive,Active"
bitfld.long 0x00 5. " TXTDMS5 ,Transmitter mode during TDM time slot 5" "Inactive,Active"
textline " "
bitfld.long 0x00 4. " TXTDMS4 ,Transmitter mode during TDM time slot 4" "Inactive,Active"
bitfld.long 0x00 3. " TXTDMS3 ,Transmitter mode during TDM time slot 3" "Inactive,Active"
bitfld.long 0x00 2. " TXTDMS2 ,Transmitter mode during TDM time slot 2" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " TXTDMS1 ,Transmitter mode during TDM time slot 1" "Inactive,Active"
bitfld.long 0x00 0. " TXTDMS0 ,Transmitter mode during TDM time slot 0" "Inactive,Active"
group.long 0xbc++0x3
line.long 0x00 "XINTCTL,Transmitter Interrupt Control Register"
bitfld.long 0x00 7. " XSTAFRM ,Transmit start of frame interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 5. " XDATA ,Transmit data ready interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XLAST ,Transmit last slot interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XDMAERR ,Transmit DMA error interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCKFAIL ,Transmit clock failure interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " XUNDRN ,Transmitter underrun interrupt enable" "Disabled,Enabled"
group.long 0xc0++0x3
line.long 0x00 "TXSTAT,Transmitter Status Register"
eventfld.long 0x00 8. " XERR ,Transmitter error interrupt has occurred" "Not occurred,Occurred"
eventfld.long 0x00 7. " XDMAERR ,Transmit DMA error" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 6. " XSTAFRM ,Transmit start of frame flag" "Not detected,Detected"
eventfld.long 0x00 5. " XDATA ,Transmit data ready flag" "No data,Transferred"
textline " "
eventfld.long 0x00 4. " XLAST ,Transmit last slot flag" "Not last,Last"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
else
bitfld.long 0x00 3. " XTDMSLOT ,Current TDM time slot even/odd" "Odd,Even"
endif
textline " "
eventfld.long 0x00 2. " XCKFAIL ,Transmit clock failure" "Not occurred,Occurred"
eventfld.long 0x00 1. " XSYNCERR ,Unexpected transmit frame sync" "Not occurred,Occurred"
textline " "
eventfld.long 0x00 0. " XUNDRN ,Transmitter underrun" "Not occurred,Occurred"
rgroup.long 0xc4++0x3
line.long 0x00 "XSLOT,Current Transmit TDM Time Slot Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*"))||(cpuis("AM335*")))
hexmask.long.word 0x00 0.--9. 1. " XSLOTCNT ,Current transmit time slot count"
else
hexmask.long.word 0x00 0.--8. 1. " XSLOTCNT ,Current transmit time slot count"
endif
group.long 0xc8++0x7
line.long 0x00 "TXCLKCHK,Transmit Clock Check Control Register"
hexmask.long.byte 0x00 24.--31. 1. " XCNT ,Transmit clock count value"
hexmask.long.byte 0x00 16.--23. 1. " XMAX ,Transmit clock maximum boundary"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " XMIN ,Transmit clock minimum boundary"
bitfld.long 0x00 0.--3. " XPS ,Transmit clock check prescaler value" "1,2,4,8,16,32,64,128,256,?..."
line.long 0x04 "XEVTCTL,Transmitter DMA Event Control Register"
bitfld.long 0x04 0. " XDATDMA ,Transmit data DMA request enable" "Enabled,?..."
sif (!cpuis("AM335*")&&(cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0xD0++0x03
line.long 0x00 "CLKADJEN,One-shot Clock Adjust Enable"
endif
tree.end
width 9.
tree "Serializer Control Registers"
group.long 0x180++0x03
line.long 0x00 "SRCTL0,Serializer Control Register 0"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x184++0x03
line.long 0x00 "SRCTL1,Serializer Control Register 1"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x188++0x03
line.long 0x00 "SRCTL2,Serializer Control Register 2"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x18C++0x03
line.long 0x00 "SRCTL3,Serializer Control Register 3"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x190++0x03
line.long 0x00 "SRCTL4,Serializer Control Register 4"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
group.long 0x194++0x03
line.long 0x00 "SRCTL5,Serializer Control Register 5"
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
rbitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
else
bitfld.long 0x00 5. " RRDY ,Receive buffer ready" "Empty,Not empty"
bitfld.long 0x00 4. " XRDY ,Transmit buffer ready" "Not empty,Empty"
endif
bitfld.long 0x00 2.--3. " DISMOD ,Serializer pin drive mode" "Tri-state,Reserved,Low,High"
bitfld.long 0x00 0.--1. " SRMOD ,Serializer mode" "Inactive,Transmitter,Receiver,?..."
tree.end
tree "DIT Channel Registers"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,DIT Left Channel Status Register 0"
group.long 0x104++0x03
line.long 0x00 "DITCSRA1,DIT Left Channel Status Register 1"
group.long 0x108++0x03
line.long 0x00 "DITCSRA2,DIT Left Channel Status Register 2"
group.long 0x10C++0x03
line.long 0x00 "DITCSRA3,DIT Left Channel Status Register 3"
group.long 0x110++0x03
line.long 0x00 "DITCSRA4,DIT Left Channel Status Register 4"
group.long 0x114++0x03
line.long 0x00 "DITCSRA5,DIT Left Channel Status Register 5"
group.long 0x118++0x03
line.long 0x00 "DITCSRB0,DIT Right Channel Status Register 0"
group.long 0x11C++0x03
line.long 0x00 "DITCSRB1,DIT Right Channel Status Register 1"
group.long 0x120++0x03
line.long 0x00 "DITCSRB2,DIT Right Channel Status Register 2"
group.long 0x124++0x03
line.long 0x00 "DITCSRB3,DIT Right Channel Status Register 3"
group.long 0x128++0x03
line.long 0x00 "DITCSRB4,DIT Right Channel Status Register 4"
group.long 0x12C++0x03
line.long 0x00 "DITCSRB5,DIT Right Channel Status Register 5"
group.long 0x130++0x03
line.long 0x00 "DITUDRA0,DIT Left Channel User Data Register 0"
group.long 0x134++0x03
line.long 0x00 "DITUDRA1,DIT Left Channel User Data Register 1"
group.long 0x138++0x03
line.long 0x00 "DITUDRA2,DIT Left Channel User Data Register 2"
group.long 0x13C++0x03
line.long 0x00 "DITUDRA3,DIT Left Channel User Data Register 3"
group.long 0x140++0x03
line.long 0x00 "DITUDRA4,DIT Left Channel User Data Register 4"
group.long 0x144++0x03
line.long 0x00 "DITUDRA5,DIT Left Channel User Data Register 5"
group.long 0x148++0x03
line.long 0x00 "DITUDRB0,DIT Right Channel User Data Register 0"
group.long 0x14C++0x03
line.long 0x00 "DITUDRB1,DIT Right Channel User Data Register 1"
group.long 0x150++0x03
line.long 0x00 "DITUDRB2,DIT Right Channel User Data Register 2"
group.long 0x154++0x03
line.long 0x00 "DITUDRB3,DIT Right Channel User Data Register 3"
group.long 0x158++0x03
line.long 0x00 "DITUDRB4,DIT Right Channel User Data Register 4"
group.long 0x15C++0x03
line.long 0x00 "DITUDRB5,DIT Right Channel User Data Register 5"
tree.end
tree "Transmit Buffer Registers"
group.long 0x200++0x03
line.long 0x00 "XBUF0,Transmit Buffer Register"
group.long 0x204++0x03
line.long 0x00 "XBUF1,Transmit Buffer Register"
group.long 0x208++0x03
line.long 0x00 "XBUF2,Transmit Buffer Register"
group.long 0x20C++0x03
line.long 0x00 "XBUF3,Transmit Buffer Register"
group.long 0x210++0x03
line.long 0x00 "XBUF4,Transmit Buffer Register"
group.long 0x214++0x03
line.long 0x00 "XBUF5,Transmit Buffer Register"
tree.end
tree "Receive Buffer Registers"
group.long 0x280++0x03
line.long 0x00 "RBUF0,Receive Buffer Register"
group.long 0x284++0x03
line.long 0x00 "RBUF1,Receive Buffer Register"
group.long 0x288++0x03
line.long 0x00 "RBUF2,Receive Buffer Register"
group.long 0x28C++0x03
line.long 0x00 "RBUF3,Receive Buffer Register"
group.long 0x290++0x03
line.long 0x00 "RBUF4,Receive Buffer Register"
group.long 0x294++0x03
line.long 0x00 "RBUF5,Receive Buffer Register"
tree.end
tree "McASP AFIFO Registers"
group.long 0x1000++0x3
line.long 0x00 "WFIFOCTL,Write FIFO Control Register"
bitfld.long 0x00 16. " WENA ,Write FIFO enable bit" "Disabled,Enabled"
hexmask.long.byte 0x00 8.--15. 1. " WNUMEVT ,Write word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " WNUMDMA ,Write word count per transfer (32-bit)"
rgroup.long 0x1004++0x3
line.long 0x00 "WFIFOSTS,Write FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " WLVL ,Write level"
group.long 0x1008++0x3
line.long 0x00 "RFIFOCTL,Read FIFO Control Register"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpuis("AM387*")))
bitfld.long 0x00 16. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
else
bitfld.long 0x00 18. " RENA ,Read FIFO enable bit" "Disabled,Enabled"
endif
hexmask.long.byte 0x00 8.--15. 1. " RNUMEVT ,Read word count per DMA event (32-bit)"
hexmask.long.byte 0x00 0.--7. 1. " RNUMDMA ,Read word count per transfer (32-bit)"
rgroup.long 0x100c++0x3
line.long 0x00 "RFIFOSTS,Read FIFO Status Register"
hexmask.long.byte 0x00 0.--7. 1. " RLVL ,Read level"
tree.end
width 0xb
tree.end
tree.end
tree "McBSP (Multichannel Buffered Serial Port)"
base ad:0x47000000
width 17.
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
base ad:0x47000000-0x100
rgroup.long 0x00++0x3
line.long 0x00 "REVNB,Revision Number Register"
bitfld.long 0x00 30.--31. " SCHEME ,Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " RTL ,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Special version for a particular device" "0,1,2,3"
bitfld.long 0x00 0.--5. " MINOR ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x3
line.long 0x00 "SYSCONFIG_REG,System Configuration Register"
bitfld.long 0x00 9. " CLOCKACTIVITY[9] ,Functional clock" "Switched off,Maintained"
bitfld.long 0x00 8. " CLOCKACTIVITY[8] ,OCP interface clock" "Switched off,Maintained"
textline " "
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,Smart-idle Wakeup"
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
else
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
wgroup.long 0x20++0x3
line.long 0x00 "EOI,End of Interrupt Register"
bitfld.long 0x00 0. " LINE_NUMBER ,Software End Of Interrupt (EOI) control" "0,1"
group.long 0x24++0xB
line.long 0x00 "IRQSTATUS_RAW,Interrupt Status Raw Register"
bitfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
textline " "
bitfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
textline " "
bitfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
textline " "
bitfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
textline " "
bitfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
textline " "
bitfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
textline " "
bitfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
textline " "
bitfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
textline " "
bitfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
textline " "
bitfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
textline " "
bitfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
textline " "
bitfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
textline " "
bitfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
line.long 0x04 "IRQSTATUS,Interrupt Status Register"
eventfld.long 0x04 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
textline " "
eventfld.long 0x04 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
textline " "
eventfld.long 0x04 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
textline " "
eventfld.long 0x04 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
textline " "
eventfld.long 0x04 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
textline " "
eventfld.long 0x04 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
textline " "
eventfld.long 0x04 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
textline " "
eventfld.long 0x04 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
textline " "
eventfld.long 0x04 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
textline " "
eventfld.long 0x04 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
textline " "
eventfld.long 0x04 2. " REOF ,Receive end of frame" "Not received,Received"
textline " "
eventfld.long 0x04 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
textline " "
eventfld.long 0x04 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
line.long 0x08 "IRQENABLE_SET,Interrupt Enable Set Register"
setclrfld.long 0x08 14. 0x08 14. 0x0C 14. " XEMPTYEOF_set/clr ,Transmit buffer empty at end of frame interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 12. 0x08 12. 0x0C 12. " XOVFLSTAT_set/clr ,Transmit buffer overflow interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 11. 0x08 11. 0x0C 11. " XUNDFLSTAT_set/clr ,Transmit buffer underflow interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 10. 0x08 10. 0x0C 10. " XRDY_set/clr ,Transmit buffer threshold reached interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 9. 0x08 9. 0x0C 9. " XEOF_set/clr ,Transmit end of frame interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 8. 0x08 8. 0x0C 8. " XFSX_set/clr ,Transmit frame synchronization interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 7. 0x08 7. 0x0C 7. " XSYNCERR_set/clr ,Transmit frame synchronization error interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 5. 0x08 5. 0x0C 5. " ROVFLSTAT_set/clr ,Receive buffer overflow interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 4. 0x08 4. 0x0C 4. " RUNDFLSTAT_set/clr ,Receive buffer underflow interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 3. 0x08 3. 0x0C 3. " RRDY_set/clr ,Receive buffer threshold reached interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 2. 0x08 2. 0x0C 2. " REOF_set/clr ,Receive end of frame interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 1. 0x08 1. 0x0C 1. " RFSR_set/clr ,Receive frame synchronization interrupt enable" "Disabled,Enabled"
textline " "
setclrfld.long 0x08 0. 0x08 0. 0x0C 0. " RSYNCERR_set/clr ,Receive frame synchronization error interrupt enable" "Disabled,Enabled"
group.long 0x34++0x7
line.long 0x00 "DMARXENABLE_SET,DMA Rx Enable Set Register"
setclrfld.long 0x00 0. 0x00 0. 0x08 0. " DMARX_ENABLE_SET_set/clr ,Receive DMA channel enable" "Disabled,Enabled"
line.long 0x04 "DMATXENABLE_SET,DMA Tx Enable Set Register"
setclrfld.long 0x04 0. 0x04 0. 0x0C 0. " DMATX_ENABLE_SET_set/clr ,Transmit DMA channel enable" "Disabled,Enabled"
group.long 0x48++0x7
line.long 0x00 "DMARXWAKE_EN,DMA Rx Wake Enable Register"
bitfld.long 0x00 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
line.long 0x04 "DMATXWAKE_EN,DMA Tx Wake Enable Register"
bitfld.long 0x04 14. " XEMPTYEOF_EN ,Transmit buffer empty at end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " XRDY_EN ,Transmit buffer threshold reached WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " XEOF_EN ,Transmit end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 8. " XFSX_EN ,Transmit frame synchronization WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " XSYNCERR_EN ,Transmit frame synchronization error WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RRDY_EN ,Receive buffer threshold reached WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 2. " REOF_EN ,Receive end of frame WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " RFSR_EN ,Receive frame synchronization WK enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " RSYNCERR_EN ,Receive frame synchronization error WK enable" "Disabled,Enabled"
base ad:0x47000000
endif
hgroup.long 0x00++0x3
hide.long 0x00 "DRR_REG,McBSP Data Receive Register"
in
wgroup.long 0x08++0x3
line.long 0x00 "DXR_REG,McBSP Data Transmit Register"
group.long 0x10++0x17
line.long 0x00 "SPCR2_REG,McBSP Serial Port Control Register 2"
bitfld.long 0x00 9. " FREE ,Free running mode" "Disabled,Enabled"
bitfld.long 0x00 8. " SOFT ,Soft Mode" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " FRST ,Frame-sync generator reset" "Reset,No reset"
bitfld.long 0x00 6. " GRST ,Sample-rate generator reset" "Reset,No reset"
textline " "
bitfld.long 0x00 4.--5. " XINTM ,Transmit interrupt mode" "XRDY,End-of-frame,New frame,XSYNCERR"
bitfld.long 0x00 3. " XSYNCERR ,Transmit synchronization error" "No error,Error"
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
rbitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
else
bitfld.long 0x00 2. " XEMPTY ,Transmit shift register XSR empty" "Empty,Not empty"
bitfld.long 0x00 1. " XRDY ,Transmitter ready" "Not ready,Ready"
endif
textline " "
bitfld.long 0x00 0. " XRST ,Transmitter reset" "Reset,Enabled"
line.long 0x04 "SPCR1_REG,McBSP Serial Port Control Register 1"
bitfld.long 0x04 15. " ALB ,Analog loopback mode" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right-justify and zero-fill MSBs,Right-justify and sign-extend MSBs,Left-justify and zero-fill LSBs,?..."
textline " "
bitfld.long 0x04 7. " DXENA ,DX enabler" "Off,On"
textline " "
bitfld.long 0x04 4.--5. " RINTM ,Receive interrupt mode" "RRDY,End-of-block/End-of-frame,New frame,RSYNCERR"
textline " "
bitfld.long 0x04 3. " RSYNCERR ,Receive synchronization error" "No error,Error"
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
textline " "
rbitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
else
bitfld.long 0x04 2. " RFULL ,Receive shift register full" "Full,Not full"
textline " "
bitfld.long 0x04 1. " RRDY ,Receiver ready" "Not ready,Ready"
endif
bitfld.long 0x04 0. " RRST ,Receiver reset" "Reset,Enabled"
line.long 0x08 "RCR2_REG,McBSP Receive Control Register 2"
bitfld.long 0x08 15. " RPHASE ,Receive phases" "Single,Dual"
hexmask.long.byte 0x08 8.--14. 1. " RFRLEN2 ,Receive frame length 2"
textline " "
bitfld.long 0x08 5.--7. " RWDLEN2 ,Receive word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
bitfld.long 0x08 3.--4. " RREVERSE ,Receive reverse mode" "MSB first,LSB first,?..."
textline " "
bitfld.long 0x08 0.--1. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
line.long 0x0c "RCR1_REG,McBSP Receive Control Register 1"
hexmask.long.byte 0x0C 8.--14. 1. " RFRLEN1 ,Receive frame length 1"
bitfld.long 0x0C 5.--7. " RWDLEN1 ,Receive word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
line.long 0x10 "XCR2_REG,McBSP Transmit Control Register 2"
bitfld.long 0x10 15. " XPHASE ,Transmit phases" "Single,Dual"
hexmask.long.byte 0x10 8.--14. 1. " XFRLEN2 ,Transmit frame length 2"
textline " "
bitfld.long 0x10 5.--7. " XWDLEN2 ,Transmit word length 2" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
bitfld.long 0x10 3.--4. " XREVERSE ,Transmit reverse mode" "MSB first,LSB first,?..."
textline " "
bitfld.long 0x10 0.--1. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
line.long 0x14 "XCR1_REG,McBSP Transmit Control Register 1"
hexmask.long.byte 0x14 8.--14. 1. " XFRLEN1 ,Transmit frame length 1"
bitfld.long 0x14 5.--7. " XWDLEN1 ,Transmit word length 1" "8 bits,12 bits,16 bits,20 bits,24 bits,32 bits,?..."
if ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x0)))
;CLKSM==0 && SCKLME==0 && FSXM==0
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
else
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
endif
textline " "
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
textline " "
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x800)))
;CLKSM==0 && SCKLME==0 && FSXM==1
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
else
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
endif
textline " "
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
textline " "
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
textline " "
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x880)))
;CLKSM==0 && SCKLME==1 && FSXM==1
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
textline " "
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
textline " "
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
textline " "
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x0)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x80)))
;CLKSM==0 && SCKLME==1 && FSXM==0
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
textline " "
bitfld.long 0x00 15. " GSYNC ,Sample rate generator synchronization" "Free-running,Running"
textline " "
bitfld.long 0x00 14. " CLKSP ,CLKS polarity clock edge select" "Rising,Falling"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x0)))
;CLKSM==1 && SCKLME==0 && FSXM==0
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
else
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
endif
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x80)))
;CLKSM==1 && SCKLME==1 && FSXM==0
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
elif ((((d.l((ad:0x47000000+0x28)))&0x2000)==0x2000)&&((((d.l((ad:0x47000000+0x48)))&0x880)==0x800)))
;CLKSM==1 && SCKLME==0 && FSXM==1
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,OCP clock"
else
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKS pin,McBSPi_ICLK clock"
endif
textline " "
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
else
;CLKSM==1 && SCKLME==1 && FSXM==1
group.long 0x28++0x3
line.long 0x00 "SRGR2_REG,McBSP SRG Register 2"
bitfld.long 0x00 13. " CLKSM ,McBSP SRG clock mode" "CLKR input pin,CLKX input pin"
textline " "
bitfld.long 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "Buffer not empty,SRG"
textline " "
hexmask.long.word 0x00 0.--11. 1. " FPER ,Frame period"
endif
group.long 0x2c++0x3
line.long 0x00 "SRGR1_REG,McBSP SRG Register 1"
hexmask.long.byte 0x00 8.--15. 1. " FWID ,Frame width"
hexmask.long.byte 0x00 0.--7. 1. " CLKGDV ,Sample rate generator clock divider"
if (((d.l((ad:0x47000000+0x30)))&0x3)==0x0)
group.long 0x30++0x3
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
else
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
endif
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
else
group.long 0x30++0x3
line.long 0x00 "MCR2_REG,McBSP Multi Channel Register 2"
bitfld.long 0x00 9. " XMCME ,Transmit multichannel partition mode" "2-partition,8-partition"
bitfld.long 0x00 7.--8. " XPBBLK ,Transmit partition B block" "Block 1,Block 3,Block 5,Block 7"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 6"
else
bitfld.long 0x00 5.--6. " XPABLK ,Transmit partition A block" "Block 0,Block 2,Block 4,Block 8"
endif
bitfld.long 0x00 0.--1. " XMCM ,Transmit multichannel selection enable" "No multi-sel,Disabled,Enabled,Symmetric"
endif
if (((d.l((ad:0x47000000+0x34)))&0x1)==0x0)
group.long 0x34++0x3
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
else
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
endif
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "Disabled,Enabled"
else
group.long 0x34++0x3
line.long 0x00 "MCR1_REG,McBSP Multi Channel Register 1"
bitfld.long 0x00 9. " RMCME ,Receive multichannel partition mode" "2-partition,8-partition"
bitfld.long 0x00 7.--8. " RPBBLK ,Receive partition B block" "Block 1,Block 3,Block 5,Block 7"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168"))
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 6"
else
bitfld.long 0x00 5.--6. " RPABLK ,Receive partition A block" "Block 0,Block 2,Block 4,Block 8"
endif
bitfld.long 0x00 0. " RMCM ,Receive multichannel selection enable" "128-channel,Multichannel"
endif
if (d.l((ad:0x47000000+0x34))&0x01)==0x00
hgroup.long 0x38++0x3
hide.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
elif (d.l((ad:0x47000000+0x34))&0x261)==0x021
group.long 0x38++0x3
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
bitfld.long 0x00 15. " RCERA[47] ,Receive channel 47 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERA[46] ,Receive channel 46 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERA[45] ,Receive channel 45 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERA[44] ,Receive channel 44 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERA[43] ,Receive channel 43 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERA[42] ,Receive channel 42 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERA[41] ,Receive channel 41 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERA[40] ,Receive channel 40 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERA[39] ,Receive channel 39 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERA[38] ,Receive channel 38 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERA[37] ,Receive channel 37 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERA[36] ,Receive channel 36 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERA[35] ,Receive channel 35 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERA[34] ,Receive channel 34 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERA[33] ,Receive channel 33 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERA[32] ,Receive channel 32 enable" "Disabled,Enabled"
elif (d.l((ad:0x47000000+0x34))&0x261)==0x041
group.long 0x38++0x3
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
bitfld.long 0x00 15. " RCERA[79] ,Receive channel 79 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERA[78] ,Receive channel 78 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERA[77] ,Receive channel 77 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERA[76] ,Receive channel 76 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERA[75] ,Receive channel 75 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERA[74] ,Receive channel 74 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERA[73] ,Receive channel 73 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERA[72] ,Receive channel 72 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERA[71] ,Receive channel 71 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERA[70] ,Receive channel 70 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERA[69] ,Receive channel 69 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERA[68] ,Receive channel 68 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERA[67] ,Receive channel 67 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERA[66] ,Receive channel 66 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERA[65] ,Receive channel 65 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERA[64] ,Receive channel 64 enable" "Disabled,Enabled"
elif (d.l((ad:0x47000000+0x34))&0x261)==0x061
group.long 0x38++0x3
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
bitfld.long 0x00 15. " RCERA[111] ,Receive channel 111 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERA[110] ,Receive channel 110 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERA[109] ,Receive channel 109 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERA[108] ,Receive channel 108 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERA[107] ,Receive channel 107 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERA[106] ,Receive channel 106 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERA[105] ,Receive channel 105 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERA[104] ,Receive channel 014 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERA[103] ,Receive channel 103 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERA[102] ,Receive channel 102 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERA[101] ,Receive channel 101 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERA[100] ,Receive channel 100 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERA[99] ,Receive channel 99 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERA[98] ,Receive channel 98 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERA[97] ,Receive channel 97 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERA[96] ,Receive channel 96 enable" "Disabled,Enabled"
else
group.long 0x38++0x3
line.long 0x00 "RCERA_REG,McBSP Receive Channel Enable Register Partition A"
bitfld.long 0x00 15. " RCERA[15] ,Receive channel 15 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERA[14] ,Receive channel 14 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERA[13] ,Receive channel 13 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERA[12] ,Receive channel 12 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERA[11] ,Receive channel 11 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERA[10] ,Receive channel 10 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERA[9] ,Receive channel 9 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERA[8] ,Receive channel 8 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERA[7] ,Receive channel 7 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERA[6] ,Receive channel 6 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERA[5] ,Receive channel 5 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERA[4] ,Receive channel 4 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERA[3] ,Receive channel 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERA[2] ,Receive channel 2 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERA[1] ,Receive channel 1 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERA[0] ,Receive channel 0 enable" "Disabled,Enabled"
endif
if (d.l(ad:0x47000000+0x34)&0x01)==0x00
hgroup.long 0x3C++0x03
hide.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
elif (d.l((ad:0x47000000+0x34))&0x381)==0x081
group.long 0x3C++0x03
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
bitfld.long 0x00 15. " RCERB[63] ,Receive channel 63 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERB[62] ,Receive channel 62 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERB[61] ,Receive channel 61 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERB[60] ,Receive channel 60 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERB[59] ,Receive channel 59 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERB[58] ,Receive channel 58 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERB[57] ,Receive channel 57 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERB[56] ,Receive channel 56 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERB[55] ,Receive channel 55 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERB[54] ,Receive channel 54 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERB[53] ,Receive channel 53 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERB[52] ,Receive channel 52 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERB[51] ,Receive channel 51 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERB[50] ,Receive channel 50 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERB[49] ,Receive channel 49 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERB[48] ,Receive channel 48 enable" "Disabled,Enabled"
elif (d.l((ad:0x47000000+0x34))&0x381)==0x101
group.long 0x3C++0x03
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
bitfld.long 0x00 15. " RCERB[95] ,Receive channel 95 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERB[94] ,Receive channel 94 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERB[93] ,Receive channel 93 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERB[92] ,Receive channel 92 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERB[91] ,Receive channel 91 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERB[90] ,Receive channel 90 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERB[89] ,Receive channel 89 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERB[88] ,Receive channel 88 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERB[87] ,Receive channel 87 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERB[86] ,Receive channel 86 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERB[85] ,Receive channel 85 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERB[84] ,Receive channel 84 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERB[83] ,Receive channel 83 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERB[82] ,Receive channel 82 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERB[81] ,Receive channel 81 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERB[80] ,Receive channel 80 enable" "Disabled,Enabled"
elif (d.l((ad:0x47000000+0x34))&0x381)==0x181
group.long 0x3C++0x03
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
bitfld.long 0x00 15. " RCERB[127] ,Receive channel 127 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERB[126] ,Receive channel 126 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERB[125] ,Receive channel 125 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERB[124] ,Receive channel 124 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERB[123] ,Receive channel 123 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERB[122] ,Receive channel 122 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERB[121] ,Receive channel 121 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERB[120] ,Receive channel 120 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERB[119] ,Receive channel 119 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERB[118] ,Receive channel 118 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERB[117] ,Receive channel 117 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERB[116] ,Receive channel 116 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERB[115] ,Receive channel 115 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERB[114] ,Receive channel 114 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERB[113] ,Receive channel 113 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERB[112] ,Receive channel 112 enable" "Disabled,Enabled"
else
group.long 0x3C++0x03
line.long 0x00 "RCERB_REG,McBSP Receive Channel Enable Register Partition B"
bitfld.long 0x00 15. " RCERB[31] ,Receive channel 31 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERB[30] ,Receive channel 30 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERB[29] ,Receive channel 29 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERB[28] ,Receive channel 28 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERB[27] ,Receive channel 27 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERB[26] ,Receive channel 26 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERB[25] ,Receive channel 25 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERB[24] ,Receive channel 24 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERB[23] ,Receive channel 23 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERB[22] ,Receive channel 22 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERB[21] ,Receive channel 21 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERB[20] ,Receive channel 20 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERB[19] ,Receive channel 19 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERB[18] ,Receive channel 18 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERB[17] ,Receive channel 17 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERB[16] ,Receive channel 16 enable" "Disabled,Enabled"
endif
if (d.l((ad:0x47000000+0x30))&0x03)==0x00
hgroup.long 0x40++0x03
hide.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x021||0x022))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x020))
group.long 0x40++0x3
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
bitfld.long 0x00 15. " XCERA[47] ,Transmit channel 47 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERA[46] ,Transmit channel 46 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERA[45] ,Transmit channel 45 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERA[44] ,Transmit channel 44 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERA[43] ,Transmit channel 43 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERA[42] ,Transmit channel 42 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERA[41] ,Transmit channel 41 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERA[40] ,Transmit channel 40 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERA[39] ,Transmit channel 39 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERA[38] ,Transmit channel 38 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERA[37] ,Transmit channel 37 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERA[36] ,Transmit channel 36 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERA[35] ,Transmit channel 35 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERA[34] ,Transmit channel 34 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERA[33] ,Transmit channel 33 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERA[32] ,Transmit channel 32 enable" "Disabled,Enabled"
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x041||0x042))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x040))
group.long 0x40++0x3
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
bitfld.long 0x00 15. " XCERA[79] ,Transmit channel 79 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERA[78] ,Transmit channel 78 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERA[77] ,Transmit channel 77 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERA[76] ,Transmit channel 76 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERA[75] ,Transmit channel 75 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERA[74] ,Transmit channel 74 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERA[73] ,Transmit channel 73 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERA[72] ,Transmit channel 72 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERA[71] ,Transmit channel 71 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERA[70] ,Transmit channel 70 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERA[69] ,Transmit channel 69 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERA[68] ,Transmit channel 68 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERA[67] ,Transmit channel 67 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERA[66] ,Transmit channel 66 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERA[65] ,Transmit channel 65 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERA[64] ,Transmit channel 64 enable" "Disabled,Enabled"
elif ((d.l((ad:0x47000000+0x30))&0x263)==(0x061||0x062))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x060)==0x060))
group.long 0x40++0x3
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
bitfld.long 0x00 15. " XCERA[111] ,Transmit channel 111 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERA[110] ,Transmit channel 110 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERA[109] ,Transmit channel 109 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERA[108] ,Transmit channel 108 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERA[107] ,Transmit channel 107 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERA[106] ,Transmit channel 106 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERA[105] ,Transmit channel 105 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERA[104] ,Transmit channel 104 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERA[103] ,Transmit channel 103 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERA[102] ,Transmit channel 102 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERA[101] ,Transmit channel 101 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERA[100] ,Transmit channel 100 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERA[99] ,Transmit channel 99 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERA[98] ,Transmit channel 98 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERA[97] ,Transmit channel 97 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERA[96] ,Transmit channel 96 enable" "Disabled,Enabled"
else
group.long 0x40++0x03
line.long 0x00 "XCERA_REG,McBSP Transmit Channel Enable Register Partition A"
bitfld.long 0x00 15. " XCERA[15] ,Transmit channel 15 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERA[14] ,Transmit channel 14 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERA[13] ,Transmit channel 13 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERA[12] ,Transmit channel 12 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERA[11] ,Transmit channel 11 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERA[10] ,Transmit channel 10 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERA[9] ,Transmit channel 9 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERA[8] ,Transmit channel 8 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERA[7] ,Transmit channel 7 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERA[6] ,Transmit channel 6 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERA[5] ,Transmit channel 5 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERA[4] ,Transmit channel 4 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERA[3] ,Transmit channel 3 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERA[2] ,Transmit channel 2 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERA[1] ,Transmit channel 1 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERA[0] ,Transmit channel 0 enable" "Disabled,Enabled"
endif
if (d.l((ad:0x47000000+0x30))&0x03)==0x00
hgroup.long 0x44++0x3
hide.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition A"
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x081||0x082))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x080))
group.long 0x44++0x03
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
bitfld.long 0x00 15. " XCERB[63] ,Transmit channel 63 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERB[62] ,Transmit channel 62 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERB[61] ,Transmit channel 61 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERB[60] ,Transmit channel 60 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERB[59] ,Transmit channel 59 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERB[58] ,Transmit channel 58 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERB[57] ,Transmit channel 57 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERB[56] ,Transmit channel 56 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERB[55] ,Transmit channel 55 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERB[54] ,Transmit channel 54 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERB[53] ,Transmit channel 53 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERB[52] ,Transmit channel 52 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERB[51] ,Transmit channel 51 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERB[50] ,Transmit channel 50 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERB[49] ,Transmit channel 49 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERB[48] ,Transmit channel 48 enable" "Disabled,Enabled"
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x101||0x102))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x100))
group.long 0x44++0x03
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
bitfld.long 0x00 15. " XCERB[95] ,Transmit channel 95 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERB[94] ,Transmit channel 94 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERB[93] ,Transmit channel 93 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERB[92] ,Transmit channel 92 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERB[91] ,Transmit channel 91 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERB[90] ,Transmit channel 90 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERB[89] ,Transmit channel 89 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERB[88] ,Transmit channel 88 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERB[87] ,Transmit channel 87 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERB[86] ,Transmit channel 86 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERB[85] ,Transmit channel 85 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERB[84] ,Transmit channel 84 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERB[83] ,Transmit channel 83 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERB[82] ,Transmit channel 82 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERB[81] ,Transmit channel 81 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERB[80] ,Transmit channel 80 enable" "Disabled,Enabled"
elif ((d.l((ad:0x47000000+0x30))&0x383)==(0x181||0x182))||(((d.l((ad:0x47000000+0x30))&0x3)==0x3)&&((d.l((ad:0x47000000+0x34))&0x180)==0x180))
group.long 0x44++0x03
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
bitfld.long 0x00 15. " XCERB[127] ,Transmit channel 127 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERB[126] ,Transmit channel 126 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERB[125] ,Transmit channel 125 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERB[124] ,Transmit channel 124 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERB[123] ,Transmit channel 123 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERB[122] ,Transmit channel 122 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERB[121] ,Transmit channel 121 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERB[120] ,Transmit channel 120 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERB[119] ,Transmit channel 119 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERB[118] ,Transmit channel 118 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERB[117] ,Transmit channel 117 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERB[116] ,Transmit channel 116 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERB[115] ,Transmit channel 115 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERB[114] ,Transmit channel 114 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERB[113] ,Transmit channel 113 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERB[112] ,Transmit channel 1126 enable" "Disabled,Enabled"
else
group.long 0x44++0x03
line.long 0x00 "XCERB_REG,McBSP Transmit Channel Enable Register Partition B"
bitfld.long 0x00 15. " XCERB[31] ,Transmit channel 31 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERB[30] ,Transmit channel 30 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERB[29] ,Transmit channel 29 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERB[28] ,Transmit channel 28 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERB[27] ,Transmit channel 27 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERB[26] ,Transmit channel 26 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERB[25] ,Transmit channel 25 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERB[24] ,Transmit channel 24 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERB[23] ,Transmit channel 23 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERB[22] ,Transmit channel 22 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERB[21] ,Transmit channel 21 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERB[20] ,Transmit channel 20 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERB[19] ,Transmit channel 19 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERB[18] ,Transmit channel 18 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERB[17] ,Transmit channel 17 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERB[16] ,Transmit channel 16 enable" "Disabled,Enabled"
endif
if ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
;xrst==0 && rrst==0 && DLB==0
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
textline " "
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
;xrst==0 && rrst==0 && DLB==1
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
textline " "
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
;xrst==0 && rrst==1 && DLB==0
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
textline " "
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
;xrst==0 && rrst==1 && DLB==1
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XIOEN ,Transmit general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
textline " "
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
;xrst==1 && rrst==0 && DLB==0
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
textline " "
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x0)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x20))
;xrst==1 && rrst==0 && DLB==1
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " RIOEN ,Receive general purpose I/O mode" "Serial port,GPIO"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
textline " "
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
elif ((((d.l((ad:0x47000000+0x10)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0x14)))&0x1)==0x1)&&(((d.l((ad:0x47000000+0xac)))&0x20)==0x0))
;xrst==1 && rrst==1 && DLB==0
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 9. " CLKXM ,Transmitter clock mode" "External,SRG"
textline " "
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSP_OCP clock,CLKR pin/CLKX pin"
else
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
endif
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
else
;xrst==1 && rrst==1 && DLB==1
group.long 0x48++0x3
line.long 0x00 "PCR_REG,McBSP Pin Control Register"
bitfld.long 0x00 14. " IDLE_EN ,Idle enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,SRG"
textline " "
bitfld.long 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,SRG"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 8. " CLKRM ,Receiver clock mode" "CLKXM,CLKRM"
textline " "
endif
bitfld.long 0x00 7. " SCLKME ,The frequency of CLKG" "CLKS pin/McBSPi_ICLK clock,CLKR pin/CLKX pin"
textline " "
sif (cpuis("DRA62*"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
rbitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
elif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
rbitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
else
bitfld.long 0x00 6. " CLKS_STAT ,CLKS pin status" "Low,High"
bitfld.long 0x00 5. " DX_STAT ,DX pin status" "Low,High"
textline " "
bitfld.long 0x00 4. " DR_STAT ,DR pin status" "Low,High"
endif
bitfld.long 0x00 3. " FSXP ,Transmit frame-synchronization polarity" "High,Low"
textline " "
bitfld.long 0x00 2. " FSRP ,Receive frame-synchronization polarity" "High,Low"
bitfld.long 0x00 1. " CLKXP ,Transmit clock polarity" "Rising,Falling"
textline " "
bitfld.long 0x00 0. " CLKRP ,Receive clock polarity" "Falling,Rising"
endif
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
group.long 0x4c++0x7
line.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
bitfld.long 0x00 15. " RCERC[47] ,Receive channel 47 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERC[46] ,Receive channel 46 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERC[45] ,Receive channel 45 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERC[44] ,Receive channel 44 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERC[43] ,Receive channel 43 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERC[42] ,Receive channel 42 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERC[41] ,Receive channel 41 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERC[40] ,Receive channel 40 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERC[39] ,Receive channel 39 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERC[38] ,Receive channel 38 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERC[37] ,Receive channel 37 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERC[36] ,Receive channel 36 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERC[35] ,Receive channel 35 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERC[34] ,Receive channel 34 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERC[33] ,Receive channel 33 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERC[32] ,Receive channel 32 enable" "Disabled,Enabled"
line.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
bitfld.long 0x04 15. " RCERD[63] ,Receive channel 63 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RCERD[62] ,Receive channel 62 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " RCERD[61] ,Receive channel 61 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " RCERD[60] ,Receive channel 60 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " RCERD[59] ,Receive channel 59 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " RCERD[58] ,Receive channel 58 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " RCERD[57] ,Receive channel 57 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " RCERD[56] ,Receive channel 56 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " RCERD[55] ,Receive channel 55 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " RCERD[54] ,Receive channel 54 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " RCERD[53] ,Receive channel 53 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " RCERD[52] ,Receive channel 52 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RCERD[51] ,Receive channel 51 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RCERD[50] ,Receive channel 50 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " RCERD[49] ,Receive channel 49 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RCERD[48] ,Receive channel 48 enable" "Disabled,Enabled"
else
hgroup.long 0x4c++0x7
hide.long 0x00 "RCERC_REG,McBSP Receive Channel Enable Register Partition C"
hide.long 0x04 "RCERD_REG,McBSP Receive Channel Enable Register Partition D"
endif
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
group.long 0x54++0x7
line.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
bitfld.long 0x00 15. " XCERC[47] ,Transmit channel 47 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERC[46] ,Transmit channel 46 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERC[45] ,Transmit channel 45 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERC[44] ,Transmit channel 44 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERC[43] ,Transmit channel 43 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERC[42] ,Transmit channel 42 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERC[41] ,Transmit channel 41 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERC[40] ,Transmit channel 40 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERC[39] ,Transmit channel 39 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERC[38] ,Transmit channel 38 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERC[37] ,Transmit channel 37 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERC[36] ,Transmit channel 36 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERC[35] ,Transmit channel 35 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERC[34] ,Transmit channel 34 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERC[33] ,Transmit channel 33 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERC[32] ,Transmit channel 32 enable" "Disabled,Enabled"
line.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
bitfld.long 0x04 15. " XCERD[63] ,Transmit channel 63 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " XCERD[62] ,Transmit channel 62 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " XCERD[61] ,Transmit channel 61 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " XCERD[60] ,Transmit channel 60 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " XCERD[59] ,Transmit channel 59 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " XCERD[58] ,Transmit channel 58 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " XCERD[57] ,Transmit channel 57 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " XCERD[56] ,Transmit channel 56 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " XCERD[55] ,Transmit channel 55 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " XCERD[54] ,Transmit channel 54 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " XCERD[53] ,Transmit channel 53 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " XCERD[52] ,Transmit channel 52 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " XCERD[51] ,Transmit channel 51 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " XCERD[50] ,Transmit channel 50 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " XCERD[49] ,Transmit channel 49 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " XCERD[48] ,Transmit channel 48 enable" "Disabled,Enabled"
else
hgroup.long 0x54++0x7
hide.long 0x00 "XCERC_REG,McBSP Transmit Channel Enable Register Partition C"
hide.long 0x04 "XCERD_REG,McBSP Transmit Channel Enable Register Partition D"
endif
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
group.long 0x5c++0x7
line.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
bitfld.long 0x00 15. " RCERE[79] ,Receive channel 79 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERE[78] ,Receive channel 78 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERE[77] ,Receive channel 77 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERE[76] ,Receive channel 76 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERE[75] ,Receive channel 75 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERE[74] ,Receive channel 74 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERE[73] ,Receive channel 73 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERE[72] ,Receive channel 72 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERE[71] ,Receive channel 71 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERE[70] ,Receive channel 70 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERE[69] ,Receive channel 69 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERE[68] ,Receive channel 68 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERE[67] ,Receive channel 67 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERE[66] ,Receive channel 66 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERE[65] ,Receive channel 65 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERE[64] ,Receive channel 64 enable" "Disabled,Enabled"
line.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
bitfld.long 0x04 15. " RCERF[95] ,Receive channel 95 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RCERF[94] ,Receive channel 94 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " RCERF[93] ,Receive channel 93 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " RCERF[92] ,Receive channel 92 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " RCERF[91] ,Receive channel 91 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " RCERF[90] ,Receive channel 90 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " RCERF[89] ,Receive channel 89 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " RCERF[88] ,Receive channel 88 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " RCERF[87] ,Receive channel 87 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " RCERF[86] ,Receive channel 86 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " RCERF[85] ,Receive channel 85 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " RCERF[84] ,Receive channel 84 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RCERF[83] ,Receive channel 83 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RCERF[82] ,Receive channel 82 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " RCERF[81] ,Receive channel 81 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RCERF[80] ,Receive channel 80 enable" "Disabled,Enabled"
else
hgroup.long 0x5c++0x7
hide.long 0x00 "RCERE_REG,McBSP Receive Channel Enable Register Partition E"
hide.long 0x04 "RCERF_REG,McBSP Receive Channel Enable Register Partition F"
endif
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
group.long 0x64++0x7
line.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
bitfld.long 0x00 15. " XCERE[79] ,Transmit channel 79 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERE[78] ,Transmit channel 78 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERE[77] ,Transmit channel 77 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERE[76] ,Transmit channel 76 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERE[75] ,Transmit channel 75 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERE[74] ,Transmit channel 74 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERE[73] ,Transmit channel 73 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERE[72] ,Transmit channel 72 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERE[71] ,Transmit channel 71 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERE[70] ,Transmit channel 70 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERE[69] ,Transmit channel 69 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERE[68] ,Transmit channel 68 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERE[67] ,Transmit channel 67 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERE[66] ,Transmit channel 66 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERE[65] ,Transmit channel 65 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERE[64] ,Transmit channel 64 enable" "Disabled,Enabled"
line.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
bitfld.long 0x04 15. " XCERF[95] ,Transmit channel 95 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " XCERF[94] ,Transmit channel 94 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " XCERF[93] ,Transmit channel 93 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " XCERF[92] ,Transmit channel 92 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " XCERF[91] ,Transmit channel 91 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " XCERF[90] ,Transmit channel 90 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " XCERF[89] ,Transmit channel 89 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " XCERF[88] ,Transmit channel 88 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " XCERF[87] ,Transmit channel 87 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " XCERF[86] ,Transmit channel 86 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " XCERF[85] ,Transmit channel 85 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " XCERF[84] ,Transmit channel 84 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " XCERF[83] ,Transmit channel 83 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " XCERF[82] ,Transmit channel 82 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " XCERF[81] ,Transmit channel 81 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " XCERF[80] ,Transmit channel 80 enable" "Disabled,Enabled"
else
hgroup.long 0x64++0x7
hide.long 0x00 "XCERE_REG,McBSP Transmit Channel Enable Register Partition E"
hide.long 0x04 "XCERF_REG,McBSP Transmit Channel Enable Register Partition F"
endif
if ((((d.l((ad:0x47000000+0x34)))&0x201)==0x201))
group.long 0x6c++0x7
line.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
bitfld.long 0x00 15. " RCERG[111] ,Receive channel 111 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " RCERG[110] ,Receive channel 110 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RCERG[109] ,Receive channel 109 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " RCERG[108] ,Receive channel 108 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " RCERG[107] ,Receive channel 107 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " RCERG[106] ,Receive channel 106 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " RCERG[105] ,Receive channel 105 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " RCERG[104] ,Receive channel 104 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " RCERG[103] ,Receive channel 103 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " RCERG[102] ,Receive channel 102 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " RCERG[101] ,Receive channel 101 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " RCERG[100] ,Receive channel 100 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " RCERG[99] ,Receive channel 99 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " RCERG[98] ,Receive channel 98 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " RCERG[97] ,Receive channel 97 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " RCERG[96] ,Receive channel 96 enable" "Disabled,Enabled"
line.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
bitfld.long 0x04 15. " RCERH[127] ,Receive channel 127 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RCERH[126] ,Receive channel 126 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " RCERH[125] ,Receive channel 125 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " RCERH[124] ,Receive channel 124 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " RCERH[123] ,Receive channel 123 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " RCERH[122] ,Receive channel 122 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " RCERH[121] ,Receive channel 121 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " RCERH[120] ,Receive channel 120 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " RCERH[119] ,Receive channel 119 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " RCERH[118] ,Receive channel 118 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " RCERH[117] ,Receive channel 117 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " RCERH[116] ,Receive channel 116 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RCERH[115] ,Receive channel 115 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RCERH[114] ,Receive channel 114 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " RCERH[113] ,Receive channel 113 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RCERH[112] ,Receive channel 112 enable" "Disabled,Enabled"
else
hgroup.long 0x6c++0x7
hide.long 0x00 "RCERG_REG,McBSP Receive Channel Enable Register Partition G"
hide.long 0x04 "RCERH_REG,McBSP Receive Channel Enable Register Partition H"
endif
if ((((d.l((ad:0x47000000+0x30)))&0x200)==0x200)&&(((d.l((ad:0x47000000+0x30)))&0x3)!=0x0))
group.long 0x74++0x7
line.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
bitfld.long 0x00 15. " XCERG[111] ,Transmit channel 111 enable" "Disabled,Enabled"
bitfld.long 0x00 14. " XCERG[110] ,Transmit channel 110 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " XCERG[109] ,Transmit channel 109 enable" "Disabled,Enabled"
bitfld.long 0x00 12. " XCERG[108] ,Transmit channel 108 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 11. " XCERG[107] ,Transmit channel 107 enable" "Disabled,Enabled"
bitfld.long 0x00 10. " XCERG[106] ,Transmit channel 106 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 9. " XCERG[105] ,Transmit channel 105 enable" "Disabled,Enabled"
bitfld.long 0x00 8. " XCERG[104] ,Transmit channel 104 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 7. " XCERG[103] ,Transmit channel 103 enable" "Disabled,Enabled"
bitfld.long 0x00 6. " XCERG[102] ,Transmit channel 102 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " XCERG[101] ,Transmit channel 101 enable" "Disabled,Enabled"
bitfld.long 0x00 4. " XCERG[100] ,Transmit channel 100 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " XCERG[99] ,Transmit channel 99 enable" "Disabled,Enabled"
bitfld.long 0x00 2. " XCERG[98] ,Transmit channel 98 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " XCERG[97] ,Transmit channel 97 enable" "Disabled,Enabled"
bitfld.long 0x00 0. " XCERG[96] ,Transmit channel 96 enable" "Disabled,Enabled"
line.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
bitfld.long 0x04 15. " XCERH[127] ,Transmit channel 127 enable" "Disabled,Enabled"
bitfld.long 0x04 14. " XCERH[126] ,Transmit channel 126 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " XCERH[125] ,Transmit channel 125 enable" "Disabled,Enabled"
bitfld.long 0x04 12. " XCERH[124] ,Transmit channel 124 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 11. " XCERH[123] ,Transmit channel 123 enable" "Disabled,Enabled"
bitfld.long 0x04 10. " XCERH[122] ,Transmit channel 122 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " XCERH[121] ,Transmit channel 121 enable" "Disabled,Enabled"
bitfld.long 0x04 8. " XCERH[120] ,Transmit channel 120 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " XCERH[119] ,Transmit channel 119 enable" "Disabled,Enabled"
bitfld.long 0x04 6. " XCERH[118] ,Transmit channel 118 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " XCERH[117] ,Transmit channel 117 enable" "Disabled,Enabled"
bitfld.long 0x04 4. " XCERH[116] ,Transmit channel 116 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " XCERH[115] ,Transmit channel 115 enable" "Disabled,Enabled"
bitfld.long 0x04 2. " XCERH[114] ,Transmit channel 114 enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " XCERH[113] ,Transmit channel 113 enable" "Disabled,Enabled"
bitfld.long 0x04 0. " XCERH[112] ,Transmit channel 112 enable" "Disabled,Enabled"
else
hgroup.long 0x74++0x7
hide.long 0x00 "XCERG_REG,McBSP Transmit Channel Enable Register Partition G"
hide.long 0x04 "XCERH_REG,McBSP Transmit Channel Enable Register Partition H"
endif
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.long 0x90++0x07
line.long 0x00 "THRSH2_REG,McBSP Transmit Buffer Threshold"
hexmask.long.word 0x00 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
line.long 0x04 "THRSH1_REG,McBSP Receive Buffer Threshold"
hexmask.long.word 0x04 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
else
rgroup.long 0x7c++0x03
line.long 0x00 "REV_REG,McBSP Revision Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REV ,Revision number"
hgroup.long 0x80++0x3
hide.long 0x00 "RINTCLR_REG,McBSP Receive Interrupt Clear"
in
hgroup.long 0x84++0x3
hide.long 0x00 "XINTCLR_REG,McBSP Transmit Interrupt Clear"
in
hgroup.long 0x88++0x3
hide.long 0x00 "ROVFLCLR_REG,McBSP Receive Overflow Interrupt Clear"
in
group.long 0x8c++0xb
line.long 0x00 "SYSCONFIG_REG,McBSP System Configuration Register"
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clock activity (McBSPi_ICLK/PRCM)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
textline " "
bitfld.long 0x00 3.--4. " SIDLEMODE ,Slave interface power management" "Force-idle,No-idle,Smart-idle,?..."
bitfld.long 0x00 2. " ENAWAKEUP ,Wakeup feature control" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " SOFTRESET ,McBSP global software reset" "No reset,Reset"
line.long 0x04 "THRSH2_REG,McBSP Transmit Buffer Threshold"
hexmask.long.word 0x04 0.--11. 1. " XTHRESHOLD ,Transmit buffer threshold value"
line.long 0x08 "THRSH1_REG,McBSP Receive Buffer Threshold"
hexmask.long.word 0x08 0.--11. 1. " RTHRESHOLD ,Receive buffer threshold value"
endif
group.long 0xa0++0x13
line.long 0x00 "IRQSTATUS_REG,McBSP Interrupt Status Register"
eventfld.long 0x00 14. " XEMPTYEOF ,Transmit buffer empty at end of frame" "Not empty,Empty"
textline " "
eventfld.long 0x00 12. " XOVFLSTAT ,Transmit buffer overflow" "No overflow,Overflow"
textline " "
eventfld.long 0x00 11. " XUNDFLSTAT ,Transmit buffer underflow" "Not empty,Empty"
textline " "
eventfld.long 0x00 10. " XRDY ,Transmit buffer threshold reached" "Below THRSH2_REG value,Equal or above THRSH2_REG value"
textline " "
eventfld.long 0x00 9. " XEOF ,Transmit end of frame" "Not transmitted,Transmitted"
textline " "
eventfld.long 0x00 8. " XFSX ,Transmit frame synchronization" "No synchronization,Synchronization"
textline " "
eventfld.long 0x00 7. " XSYNCERR ,Transmit frame synchronization error" "No error,Error"
textline " "
eventfld.long 0x00 5. " ROVFLSTAT ,Receive buffer overflow" "No overflow,Overflow"
textline " "
eventfld.long 0x00 4. " RUNDFLSTAT ,Receive buffer underflow" "Not empty,Empty"
textline " "
eventfld.long 0x00 3. " RRDY ,Receive buffer threshold reached" "Below THRSH1_REG value,Equal or above THRSH1_REG value"
textline " "
eventfld.long 0x00 2. " REOF ,Receive end of frame" "Not received,Received"
textline " "
eventfld.long 0x00 1. " RFSR ,Receive frame synchronization" "No synchronization,Synchronization"
textline " "
eventfld.long 0x00 0. " RSYNCERR ,Receive frame synchronization error" "No error,Error"
line.long 0x04 "IRQENABLE_REG,McBSP Interrupt Enable Register"
bitfld.long 0x04 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 12. " XOVFLEN ,Transmit buffer overflow enable" "Disabled,Enabled"
bitfld.long 0x04 11. " XUNDFLEN ,Transmit buffer underflow enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " XRDYEN ,Transmit buffer threshold reached enable" "Disabled,Enabled"
bitfld.long 0x04 9. " XEOFEN ,Transmit end of frame enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 8. " XFSXEN ,Transmit frame synchronization enable" "Disabled,Enabled"
bitfld.long 0x04 7. " XSYNCERREN ,Transmit frame synchronization error enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " ROVFLEN ,Receive buffer overflow enable" "Disabled,Enabled"
bitfld.long 0x04 4. " RUNDFLEN ,Receive buffer underflow enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RRDYEN ,Receive buffer threshold enable" "Disabled,Enabled"
bitfld.long 0x04 2. " REOFEN ,Receive end of frame enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " RFSREN ,Receive frame synchronization enable" "Disabled,Enabled"
bitfld.long 0x04 0. " RSYNCERREN ,Receive frame synchronization error enable" "Disabled,Enabled"
line.long 0x08 "WAKEUPEN_REG,McBSP Wakeup Enable Register"
bitfld.long 0x08 14. " XEMPTYEOFEN ,Transmit buffer empty at end of frame WK enable" "Not active,Active"
textline " "
bitfld.long 0x08 10. " XRDYEN ,Transmit buffer threshold reached WK enable" "Not active,Active"
bitfld.long 0x08 9. " XEOFEN ,Transmit end of frame WK enable" "Not active,Active"
textline " "
bitfld.long 0x08 8. " XFSXEN ,Transmit frame synchronization WK enable" "Not active,Active"
bitfld.long 0x08 7. " XSYNCERREN ,Transmit frame synchronization error WK enable" "Not active,Active"
textline " "
bitfld.long 0x08 3. " RRDYEN ,Receive buffer threshold wakeup enable" "Not active,Active"
bitfld.long 0x08 2. " REOFEN ,Receive end of frame WK enable" "Not active,Active"
textline " "
bitfld.long 0x08 1. " RFSREN ,Receive frame synchronization WK enable" "Not active,Active"
bitfld.long 0x08 0. " RSYNCERREN ,Receive frame synchronization error WK enable" "Not active,Active"
line.long 0x0c "XCCR_REG,McBSP Transmit Configuration Control Register"
bitfld.long 0x0C 15. " EXTCLKGATE ,External clock gating enable" "Disabled,Enabled"
bitfld.long 0x0C 14. " PPCONNECT ,Pair to pair connection" "No connection,Connection"
textline " "
sif (((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpuis("AM387*"))||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "8 ns,14 ns,20 ns,28 ns"
else
bitfld.long 0x0C 12.--13. " DXENDLY ,Added delay" "18 ns,26 ns,35 ns,42 ns"
endif
bitfld.long 0x0C 11. " XFULL_CYCLE ,Transmit full cycle mode" "Half-cycle,Full-cycle"
textline " "
bitfld.long 0x0C 5. " DLB ,Digital loop-back" "No DLB,DLB"
bitfld.long 0x0C 3. " XDMAEN ,Transmit DMA enable" "Disabled,Enabled"
textline " "
bitfld.long 0x0C 0. " XDISABLE ,Transmit disable" "Not stopped,Stopped"
line.long 0x10 "RCCR_REG,McBSP Receive Configuration Control Register"
bitfld.long 0x10 11. " RFULL_CYCLE ,Receive full cycle mode" "Half-cycle,Full-cycle"
bitfld.long 0x10 3. " RDMAEN ,Receive DMA enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 0. " RDISABLE ,Receive disable" "Not stopped,Stopped"
sif (cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")
rgroup.long 0xb4++0x7
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
hexmask.long.byte 0x00 0.--7. 1. " XBUFFSTAT ,Transmit buffer status"
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
hexmask.long.byte 0x04 0.--7. 1. " RBUFFSTAT ,Receive buffer status"
else
rgroup.long 0xb4++0x7
line.long 0x00 "XBUFFSTAT_REG,McBSP Transmit Buffer Status"
hexmask.long.word 0x00 0.--10. 1. " XBUFFSTAT ,Transmit buffer status"
line.long 0x04 "RBUFFSTAT_REG,McBSP Receive Buffer Status"
hexmask.long.word 0x04 0.--10. 1. " RBUFFSTAT ,Receive buffer status"
endif
rgroup.long 0xc0++0x3
line.long 0x00 "STATUS_REG,McBSP Status Register"
bitfld.long 0x00 0. " CLKMUXSTATUS ,Response to a different register access delayed" "Not delayed,Delayed"
width 11.
tree.end
tree "McSPI (Multichannel Serial Port Interface)"
base ad:0x48030000
width 20.
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rgroup.long 0x00++0x7
line.long 0x00 "MCSPI_HL_REV,MCSPI IP Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Identifies scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL version (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision (X)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision (Y)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MCSPI_HL_HWINFO,MCSPI IP hardware information register"
bitfld.long 0x04 1.--5. " FFNBYTE ,FIFO number of byte generic parameter" "Reserved,16 bytes,32 bytes,Reserved,64 bytes,Reserved,Reserved,Reserved,128 bytes,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,256 bytes,?..."
bitfld.long 0x04 0. " USEFIFO ,Use of a FIFO enable" "Disabled,Enabled"
group.long 0x10++0x3
line.long 0x00 "MCSPI_HL_SYSCONFIG,MCSPI IP system configuration register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x100++0x3
line.long 0x00 "MCSPI_REVISION,MCSPI revision register"
hexmask.long.byte 0x00 0.--7. 1. " REV ,Identifies revision of peripheral"
endif
group.long 0x110++0x3
line.long 0x00 "MCSPI_SYSCONFIG,MCSPI System Configuration Register"
bitfld.long 0x00 8.--9. " CLOCKACTIVITY ,Clocks activity during wake up mode period (interface/functional)" "Switched off,Maintained/Switched off,Switched off/Maintained,Maintained"
bitfld.long 0x00 3.--4. " SIDLEMODE ,Power management" "Inactive,Normal,Wake up,?..."
textline " "
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 2. " ENAWAKEUP ,Software reset" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
bitfld.long 0x00 0. " AUTOIDLE ,Internal interface clock gating strategy" "Free-running,Automatic"
rgroup.long 0x114++0x3
line.long 0x00 "MCSPI_SYSSTATUS,MCSPI System Status Register"
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
group.long 0x118++0x7
line.long 0x00 "MCSPI_IRQSTATUS,MCSPI Interrupt Status Register"
eventfld.long 0x00 17. " EOW ,End of word count event" "False,Pending"
eventfld.long 0x00 14. " RX3_FULL ,Receiver register full" "False,Pending"
textline " "
eventfld.long 0x00 13. " TX3_UNDERFLOW ,Transmitter register underflow" "False,Pending"
eventfld.long 0x00 12. " TX3_EMPTY ,Transmitter register empty" "False,Pending"
textline " "
eventfld.long 0x00 10. " RX2_FULL ,Receiver register full" "False,Pending"
eventfld.long 0x00 9. " TX2_UNDERFLOW ,Transmitter register underflow" "False,Pending"
textline " "
eventfld.long 0x00 8. " TX2_EMPTY ,Transmitter register empty" "False,Pending"
eventfld.long 0x00 6. " RX1_FULL ,Receiver register full" "False,Pending"
textline " "
eventfld.long 0x00 5. " TX1_UNDERFLOW ,Transmitter register underflow" "False,Pending"
eventfld.long 0x00 4. " TX1_EMPTY ,Transmitter register empty" "False,Pending"
textline " "
eventfld.long 0x00 3. " RX0_OVERFLOW ,Receiver register overflow" "False,Pending"
eventfld.long 0x00 2. " RX0_FULL ,Receiver register full" "False,Pending"
textline " "
eventfld.long 0x00 1. " TX0_UNDERFLOW ,Transmitter register underflow" "False,Pending"
eventfld.long 0x00 0. " TX0_EMPTY ,Transmitter register empty" "False,Pending"
line.long 0x04 "MCSPI_IRQENABLE,MCSPI Interrupt Enable/Disable Register"
bitfld.long 0x04 17. " EOWKE ,End of word count interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 14. " RX3_FULL_ENABLE ,Receiver register full Interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " TX3_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 12. " TX3_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " RX2_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 9. " TX2_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 8. " TX2_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 6. " RX1_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " TX1_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 4. " TX1_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " RX0_OVERFLOW_ENABLE ,Receiver register overflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 2. " RX0_FULL_ENABLE ,Receiver register full interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " TX0_UNDERFLOW_ENABLE ,Transmitter register underflow interrupt enable" "Disabled,Enabled"
bitfld.long 0x04 0. " TX0_EMPTY_ENABLE ,Transmitter register empty interrupt enable" "Disabled,Enabled"
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.long 0x120++0x3
line.long 0x00 "MCSPI_WAKEUPENABLE,MCSPI Wakeup Enable Register"
bitfld.long 0x00 0. " WKEN ,Wakeup functionality in slave mode" "Disabled,Enabled"
endif
group.long 0x124++0x03
line.long 0x00 "MCSPI_SYST,MCSPI System Test Register"
bitfld.long 0x00 11. " SSB ,Set status" "No action,Set"
bitfld.long 0x00 10. " SPIENDIR ,Set the direction of the SPIEN[3:0] lines and SPICLK line" "Output,Input"
textline " "
bitfld.long 0x00 9. " SPIDATDIR1 ,Set the direction of the SPIDAT[1]" "Output,Input"
bitfld.long 0x00 8. " SPIDATDIR0 ,Set the direction of the SPIDAT[0]" "Output,Input"
textline " "
bitfld.long 0x00 6. " SPICLK ,SPICLK line" "Low,High"
bitfld.long 0x00 5. " SPIDAT_1 ,SPIDAT[1] line" "Low,High"
textline " "
bitfld.long 0x00 4. " SPIDAT_0 ,SPIDAT[0] line" "Low,High"
bitfld.long 0x00 3. " SPIEN_3 ,SPIEN[3] line" "Low,High"
textline " "
bitfld.long 0x00 2. " SPIEN_2 ,SPIEN[2] line" "Low,High"
bitfld.long 0x00 1. " SPIEN_1 ,SPIEN[1] line" "Low,High"
textline " "
bitfld.long 0x00 0. " SPIEN_0 ,SPIEN[0] line" "Low,High"
if (((d.l((ad:0x48030000+0x128)))&0x4)==0x4)
;slave
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4.--6. " INITDLY ,>Initial SPI delay for first transfer (SPI bus clocks)" "No delay,4,8,16,32,?..."
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
textline " "
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
else
;master
group.long 0x128++0x3
line.long 0x00 "MCSPI_MODULCTRL,MCSPI Module Control Register"
bitfld.long 0x00 8. " FDAA ,FIFO DMA Address 256-bit aligned" "MCSPI_TX(i)/MCSPI_RX(i),MCSPI_DAFTX/MCSPI_DAFRX"
bitfld.long 0x00 7. " MOA ,Multiple word ocp access" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4.--6. " INITDLY ,Initial SPI delay for first transfer" "No delay,1,2,3,4,5,6,7"
bitfld.long 0x00 3. " SYSTEM_TEST ,System test mode enable" "Functional,System test"
textline " "
bitfld.long 0x00 2. " MS ,Master / Slave" "Master,Slave"
bitfld.long 0x00 1. " PIN34 ,Pin mode selection (SPIEN)" "Chip select,Unused"
textline " "
bitfld.long 0x00 0. " SINGLE ,Single channel / Multi Channel" "Multi,Single"
endif
group.long 0x12C++0x3 "Channel 0"
line.long 0x00 "MCSPI_CH0CONF,MCSPI Channel 0 Configuration Register"
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
textline " "
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
textline " "
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
textline " "
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
textline " "
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
textline " "
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
textline " "
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
textline " "
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 0" "High,Low"
textline " "
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
textline " "
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
rgroup.long (0x12C+0x04)++0x3
line.long 0x00 "MCSPI_CH0STAT,MCSPI Channel 0 Status Register"
bitfld.long 0x00 6. " RXFFF ,Channel 0 FIFO Receive Buffer Full Status" "Not full,Full"
bitfld.long 0x00 5. " RXFFE ,Channel 0 FIFO Receive Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 4. " TXFFF ,Channel 0 FIFO Transmit Buffer Full Status" "Not full,Full"
bitfld.long 0x00 3. " TXFFE ,Channel 0 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 2. " EOT ,Channel 0 end of transfer status" "Not ended,Ended"
bitfld.long 0x00 1. " TXS ,Channel 0 transmitter register status" "Full,Empty"
textline " "
bitfld.long 0x00 0. " RXS ,Channel 0 receiver register status" "Empty,Full"
group.long (0x12C+0x08)++0x7
line.long 0x00 "MCSPI_CH0CTRL,MCSPI Channel 0 Control Register"
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
textline " "
bitfld.long 0x00 0. " EN ,Channel 0 enable" "Disabled,Enabled"
line.long 0x04 "MCSPI_TX0,MCSPI Channel 0 Transmit Register"
hgroup.long (0x12C+0x10)++0x3
hide.long 0x00 "MCSPI_RX0,MCSPI Channel 0 Receive Register"
in
group.long 0x140++0x3 "Channel 1"
line.long 0x00 "MCSPI_CH1CONF,MCSPI Channel 1 Configuration Register"
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
textline " "
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
textline " "
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
textline " "
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
textline " "
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
textline " "
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
textline " "
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
textline " "
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 1" "High,Low"
textline " "
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
textline " "
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
rgroup.long (0x140+0x04)++0x3
line.long 0x00 "MCSPI_CH1STAT,MCSPI Channel 1 Status Register"
bitfld.long 0x00 6. " RXFFF ,Channel 1 FIFO Receive Buffer Full Status" "Not full,Full"
bitfld.long 0x00 5. " RXFFE ,Channel 1 FIFO Receive Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 4. " TXFFF ,Channel 1 FIFO Transmit Buffer Full Status" "Not full,Full"
bitfld.long 0x00 3. " TXFFE ,Channel 1 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 2. " EOT ,Channel 1 end of transfer status" "Not ended,Ended"
bitfld.long 0x00 1. " TXS ,Channel 1 transmitter register status" "Full,Empty"
textline " "
bitfld.long 0x00 0. " RXS ,Channel 1 receiver register status" "Empty,Full"
group.long (0x140+0x08)++0x7
line.long 0x00 "MCSPI_CH1CTRL,MCSPI Channel 1 Control Register"
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
textline " "
bitfld.long 0x00 0. " EN ,Channel 1 enable" "Disabled,Enabled"
line.long 0x04 "MCSPI_TX1,MCSPI Channel 1 Transmit Register"
hgroup.long (0x140+0x10)++0x3
hide.long 0x00 "MCSPI_RX1,MCSPI Channel 1 Receive Register"
in
group.long 0x154++0x3 "Channel 2"
line.long 0x00 "MCSPI_CH2CONF,MCSPI Channel 2 Configuration Register"
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
textline " "
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
textline " "
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
textline " "
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
textline " "
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
textline " "
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
textline " "
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
textline " "
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 2" "High,Low"
textline " "
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
textline " "
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
rgroup.long (0x154+0x04)++0x3
line.long 0x00 "MCSPI_CH2STAT,MCSPI Channel 2 Status Register"
bitfld.long 0x00 6. " RXFFF ,Channel 2 FIFO Receive Buffer Full Status" "Not full,Full"
bitfld.long 0x00 5. " RXFFE ,Channel 2 FIFO Receive Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 4. " TXFFF ,Channel 2 FIFO Transmit Buffer Full Status" "Not full,Full"
bitfld.long 0x00 3. " TXFFE ,Channel 2 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 2. " EOT ,Channel 2 end of transfer status" "Not ended,Ended"
bitfld.long 0x00 1. " TXS ,Channel 2 transmitter register status" "Full,Empty"
textline " "
bitfld.long 0x00 0. " RXS ,Channel 2 receiver register status" "Empty,Full"
group.long (0x154+0x08)++0x7
line.long 0x00 "MCSPI_CH2CTRL,MCSPI Channel 2 Control Register"
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
textline " "
bitfld.long 0x00 0. " EN ,Channel 2 enable" "Disabled,Enabled"
line.long 0x04 "MCSPI_TX2,MCSPI Channel 2 Transmit Register"
hgroup.long (0x154+0x10)++0x3
hide.long 0x00 "MCSPI_RX2,MCSPI Channel 2 Receive Register"
in
group.long 0x168++0x3 "Channel 3"
line.long 0x00 "MCSPI_CH3CONF,MCSPI Channel 3 Configuration Register"
bitfld.long 0x00 29. " CLKG ,Clock divider granularity" "Power of two,One clock cycle"
textline " "
bitfld.long 0x00 28. " FFER ,FIFO enabled for Receive" "Not used,Used"
bitfld.long 0x00 27. " FFEW ,FIFO enabled for Transmit" "Not used,Used"
textline " "
bitfld.long 0x00 25.--26. " TCS ,Chip select time control" "0.5 cycle,1.5 cycle,2.5 cycle,3.5 cycle"
bitfld.long 0x00 24. " SBPOL ,Start bit polarity" "0,1"
textline " "
bitfld.long 0x00 23. " SBE ,Start bit enable for SPI transfer" "Default,D/CX added"
bitfld.long 0x00 21.--22. " SPIENSLV ,SPI slave select signal detection" "SPIEN[0],SPIEN[1],SPIEN[2],SPIEN[3]"
textline " "
bitfld.long 0x00 20. " FORCE ,Manual SPIEN assertion (single channel master mode only)" "Not asserted,Asserted"
bitfld.long 0x00 19. " TURBO ,Turbo mode" "Deactivated,Activated"
textline " "
bitfld.long 0x00 18. " IS ,Input select" "Data line 0,Data line 1"
bitfld.long 0x00 17. " DPE1 ,Transmission enable for data line 1" "Enabled,Disabled"
textline " "
bitfld.long 0x00 16. " DPE0 ,Transmission enable for data line 0" "Enabled,Disabled"
bitfld.long 0x00 15. " DMAR ,DMA read request" "Disabled,Enabled"
textline " "
bitfld.long 0x00 14. " DMAW ,DMA write request" "Disabled,Enabled"
bitfld.long 0x00 12.--13. " TRM ,Transmit / receive modes" "Transmit and receive,Receive only,Transmit only,?..."
textline " "
bitfld.long 0x00 7.--11. " WL ,SPI word length" "Reserved,Reserved,Reserved,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,25-bit,26-bit,27-bit,28-bit,29-bit,30-bit,31-bit,32-bit"
bitfld.long 0x00 6. " EPOL ,SPIEN polarity for channel 3" "High,Low"
textline " "
bitfld.long 0x00 2.--5. " CLKD ,Frequency divider for SPICLK (Master SPI device)" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768"
bitfld.long 0x00 1. " POL ,SPICLK polarity" "High,Low"
textline " "
bitfld.long 0x00 0. " PHA ,SPICLK phase" "Odd,Even"
rgroup.long (0x168+0x04)++0x3
line.long 0x00 "MCSPI_CH3STAT,MCSPI Channel 3 Status Register"
bitfld.long 0x00 6. " RXFFF ,Channel 3 FIFO Receive Buffer Full Status" "Not full,Full"
bitfld.long 0x00 5. " RXFFE ,Channel 3 FIFO Receive Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 4. " TXFFF ,Channel 3 FIFO Transmit Buffer Full Status" "Not full,Full"
bitfld.long 0x00 3. " TXFFE ,Channel 3 FIFO Transmit Buffer Empty Status" "Not empty,Empty"
textline " "
bitfld.long 0x00 2. " EOT ,Channel 3 end of transfer status" "Not ended,Ended"
bitfld.long 0x00 1. " TXS ,Channel 3 transmitter register status" "Full,Empty"
textline " "
bitfld.long 0x00 0. " RXS ,Channel 3 receiver register status" "Empty,Full"
group.long (0x168+0x08)++0x7
line.long 0x00 "MCSPI_CH3CTRL,MCSPI Channel 3 Control Register"
hexmask.long.byte 0x00 8.--15. 1. " EXTCLK ,Clock ratio extension"
textline " "
bitfld.long 0x00 0. " EN ,Channel 3 enable" "Disabled,Enabled"
line.long 0x04 "MCSPI_TX3,MCSPI Channel 3 Transmit Register"
hgroup.long (0x168+0x10)++0x3
hide.long 0x00 "MCSPI_RX3,MCSPI Channel 3 Receive Register"
in
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.long 0x17C++0x3 ""
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
group.long 0x180++0x3
line.long 0x00 "MCSPI_DAFTX,DMA Address Aligned FIFO Transmitter Register"
hgroup.long 0x1A0++0x3
hide.long 0x00 "MCSPI_DAFRX,DMA Address Aligned FIFO Receiver Register"
in
else
group.long 0x7C++0x3 ""
line.long 0x00 "MCSPI_XFERLEVEL,McSPI Transfer Levels Register"
hexmask.long.word 0x00 16.--31. 1. " WCNT ,Spi word counter"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " AFL ,Buffer Almost Full"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " AEL ,Buffer Almost Empty"
endif
width 11.
tree.end
tree "PCIe (Peripheral Component Interconnect Express)"
base ad:0x51000000
width 21.
rgroup.long 0x00++0x03
line.long 0x00 "PID,Peripheral Version and ID"
bitfld.long 0x00 30.--31. " SCHEME ,PID Register Format Scheme" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function code of the peripheral"
textline " "
bitfld.long 0x00 11.--15. " RTL ,RTL version number (R)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " MAJOR ,Major revision code (X)" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Custom code" "0,1,2,3"
bitfld.long 0x00 0.--5. " MINOR ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x04++0x13
line.long 0x00 "CMD_STATUS,Command Status"
bitfld.long 0x00 10.--11. " OCP_STANDBY ,OCP standby mode" "0,1,2,3"
bitfld.long 0x00 8.--9. " OCP_IDLE ,OCP idle mode" "0,1,2,3"
textline " "
bitfld.long 0x00 5. " DBI_CS2 ,Enable writing to BAR mask registers" "Disabled,Enabled"
bitfld.long 0x00 4. " APP_RETRY_EN ,Application Request Retry Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 3. " POSTED_WR_EN ,Posted Write Enable" "Disabled,Enabled"
bitfld.long 0x00 2. " IB_XLT_EN ,Inbound Address Translation Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 1. " OB_XLT_EN ,Outbound Address Translation Enable" "Disabled,Enabled"
bitfld.long 0x00 0. " LTSSM_EN ,Link Transitioning Enable" "Disabled,Enabled"
line.long 0x04 "CFG_SETUP,Config Transaction Setup"
bitfld.long 0x04 24. " CFG_TYPE ,Configuration Type for outbound configuration accesses" "Type 0,Type 1"
hexmask.long.byte 0x04 16.--23. 1. " CFG_BUS ,PCIe Bus number for outbound configuration accesses"
textline " "
bitfld.long 0x04 8.--12. " CFG_DEVICE ,PCIe Device number for outbound configuration accesses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 0.--2. " CFG_FUNC ,PCIe Function number for outbound configuration accesses" "0,1,2,3,4,5,6,7"
line.long 0x08 "IOBASE,IO TLP Base"
hexmask.long.tbyte 0x08 12.--31. 1. " IOBASE ,Outgoing IO"
line.long 0x0C "TLPCFG,TLP Attribute Configuration"
bitfld.long 0x0C 1. " RELAXED ,Relaxed Ordering" "Disabled,Enabled"
bitfld.long 0x0C 0. " NO_SNOOP ,No Snoop Attribute" "Disabled,Enabled"
line.long 0x10 "RSTCMD,Reset Command and Status"
bitfld.long 0x10 16. " FLUSH_N ,Bridge Flush Status" "Not pending,Pending"
bitfld.long 0x10 0. " INIT_RST ,Downstream hot reset sequence" "No effect,Reset"
wgroup.long 0x20++0x03
line.long 0x00 "PMCMD,Power Management Command"
bitfld.long 0x00 1. " PM_XMT_TURNOFF ,PM_TURNOFF message transmit (RC mode)" "No effect,Transmit"
bitfld.long 0x00 0. " PM_XMT_PME ,PM_PME message transmit (EP mode)" "No effect,Transmit"
group.long 0x24++0x03
line.long 0x00 "PMCFG,Power Management Configuration"
sif (cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
rbitfld.long 0x00 2. " RDY_ENTR_L23 ,Read L2/L3 entry readiness" "Not ready,Ready"
else
bitfld.long 0x00 2. " RDY_ENTR_L23 ,Read L2/L3 entry readiness" "Not ready,Ready"
endif
bitfld.long 0x00 0. " ENTR_L23 ,L2/L3 ready state entry enable" "Disabled,Enabled"
rgroup.long 0x28++0x03
line.long 0x00 "ACT_STATUS,Activity Status"
bitfld.long 0x00 1. " OB_NOT_EMPTY ,Outbound buffers not empty" "Empty,Not Empty"
bitfld.long 0x00 0. " IB_NOT_EMPTY ,Inbound buffers not empty" "Empty,Not Empty"
group.long 0x30++0x0F
line.long 0x00 "OB_SIZE,Outbound Size"
bitfld.long 0x00 0.--2. " OB_SIZE ,Outbound translation window size" "1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB"
line.long 0x04 "DIAG_CTRL,Diagnostic Control"
bitfld.long 0x04 1. " INV_ECRC ,Inversion of LSB of ECRC for next one packet" "Not forced,Forced"
bitfld.long 0x04 0. " INV_LCRC ,Inversion of LSB of LCRC for next one packet" "Not forced,Forced"
line.long 0x08 "ENDIAN,Endian Mode"
bitfld.long 0x08 0.--1. " ENDIAN ,Endian" "0,1,2,3"
line.long 0x0C "PRIORITY,CBA Transaction Priority"
bitfld.long 0x0C 16. " MST_PRIV ,Value on master transactions" "0,1"
bitfld.long 0x0C 8.--11. " MST_PRIVID ,Value on master transactions" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
sif (cpuis("DRA6*")&&!cpuis("DRA62*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
bitfld.long 0x0C 0.--2. " MST_PRIORITY ,Priority level for each inbound transaction on the CBA master port" "0,1,2,3,4,5,6,7"
else
bitfld.long 0x0C 0.--1. " MST_PRIORITY ,Priority level for each inbound transaction on the CBA master port" "0,1,2,3"
endif
group.long 0x50++0x07
line.long 0x00 "IRQ_EOI,End of Interrupt"
bitfld.long 0x00 0.--1. " EOI ,End of interrupt for each interrupt" "0,1,2,3"
line.long 0x04 "MSI_IRQ,MSI Interrupt IRQ"
bitfld.long 0x04 31. " MSI_IRQ[31] ,MSI Interrupt Request [31]" "No interrupt,Interrupt"
bitfld.long 0x04 30. " MSI_IRQ[30] ,MSI Interrupt Request [30]" "No interrupt,Interrupt"
bitfld.long 0x04 29. " MSI_IRQ[29] ,MSI Interrupt Request [29]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 28. " MSI_IRQ[28] ,MSI Interrupt Request [28]" "No interrupt,Interrupt"
bitfld.long 0x04 27. " MSI_IRQ[27] ,MSI Interrupt Request [27]" "No interrupt,Interrupt"
bitfld.long 0x04 26. " MSI_IRQ[26] ,MSI Interrupt Request [26]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 25. " MSI_IRQ[25] ,MSI Interrupt Request [25]" "No interrupt,Interrupt"
bitfld.long 0x04 24. " MSI_IRQ[24] ,MSI Interrupt Request [24]" "No interrupt,Interrupt"
bitfld.long 0x04 23. " MSI_IRQ[23] ,MSI Interrupt Request [23]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 22. " MSI_IRQ[22] ,MSI Interrupt Request [22]" "No interrupt,Interrupt"
bitfld.long 0x04 21. " MSI_IRQ[21] ,MSI Interrupt Request [21]" "No interrupt,Interrupt"
bitfld.long 0x04 20. " MSI_IRQ[20] ,MSI Interrupt Request [20]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 19. " MSI_IRQ[19] ,MSI Interrupt Request [19]" "No interrupt,Interrupt"
bitfld.long 0x04 18. " MSI_IRQ[18] ,MSI Interrupt Request [18]" "No interrupt,Interrupt"
bitfld.long 0x04 17. " MSI_IRQ[17] ,MSI Interrupt Request [17]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 16. " MSI_IRQ[16] ,MSI Interrupt Request [16]" "No interrupt,Interrupt"
bitfld.long 0x04 15. " MSI_IRQ[15] ,MSI Interrupt Request [15]" "No interrupt,Interrupt"
bitfld.long 0x04 14. " MSI_IRQ[14] ,MSI Interrupt Request [14]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 13. " MSI_IRQ[13] ,MSI Interrupt Request [13]" "No interrupt,Interrupt"
bitfld.long 0x04 12. " MSI_IRQ[12] ,MSI Interrupt Request [12]" "No interrupt,Interrupt"
bitfld.long 0x04 11. " MSI_IRQ[11] ,MSI Interrupt Request [11]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 10. " MSI_IRQ[10] ,MSI Interrupt Request [10]" "No interrupt,Interrupt"
bitfld.long 0x04 9. " MSI_IRQ[9] ,MSI Interrupt Request [9]" "No interrupt,Interrupt"
bitfld.long 0x04 8. " MSI_IRQ[8] ,MSI Interrupt Request [8]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " MSI_IRQ[7] ,MSI Interrupt Request [7]" "No interrupt,Interrupt"
bitfld.long 0x04 6. " MSI_IRQ[6] ,MSI Interrupt Request [6]" "No interrupt,Interrupt"
bitfld.long 0x04 5. " MSI_IRQ[5] ,MSI Interrupt Request [5]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 4. " MSI_IRQ[4] ,MSI Interrupt Request [4]" "No interrupt,Interrupt"
bitfld.long 0x04 3. " MSI_IRQ[3] ,MSI Interrupt Request [3]" "No interrupt,Interrupt"
bitfld.long 0x04 2. " MSI_IRQ[2] ,MSI Interrupt Request [2]" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " MSI_IRQ[1] ,MSI Interrupt Request [1]" "No interrupt,Interrupt"
bitfld.long 0x04 0. " MSI_IRQ[0] ,MSI Interrupt Request [0]" "No interrupt,Interrupt"
group.long 0x6C++0x03
line.long 0x00 "EP_IRQ_STATUS,Endpoint Interrupt Request Set"
setclrfld.long 0x00 0. -0x08 0. -0x04 0. " EP_IRQ_STATUS_set/clr ,EP Interrupt Request Status set/clr" "Not asserted,Asserted"
group.long 0x70++0xF
line.long 0x0 "GPR0,General Purpose 0"
group.long 0x70++0xF
line.long 0x4 "GPR1,General Purpose 1"
group.long 0x70++0xF
line.long 0x8 "GPR2,General Purpose 2"
group.long 0x70++0xF
line.long 0xC "GPR3,General Purpose 3"
group.long 0x100++0xF
line.long 0x00 "MSI0_STATUS_RAW,MSI 0 Interrupt Raw Status"
bitfld.long 0x00 31. " MSI0_RAW_STATUS[31] ,MSI Interrupt 31 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 30. " MSI0_RAW_STATUS[30] ,MSI Interrupt 30 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 29. " MSI0_RAW_STATUS[29] ,MSI Interrupt 29 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 28. " MSI0_RAW_STATUS[28] ,MSI Interrupt 28 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 27. " MSI0_RAW_STATUS[27] ,MSI Interrupt 27 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 26. " MSI0_RAW_STATUS[26] ,MSI Interrupt 26 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 25. " MSI0_RAW_STATUS[25] ,MSI Interrupt 25 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 24. " MSI0_RAW_STATUS[24] ,MSI Interrupt 24 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 23. " MSI0_RAW_STATUS[23] ,MSI Interrupt 23 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 22. " MSI0_RAW_STATUS[22] ,MSI Interrupt 22 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 21. " MSI0_RAW_STATUS[21] ,MSI Interrupt 21 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 20. " MSI0_RAW_STATUS[20] ,MSI Interrupt 20 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 19. " MSI0_RAW_STATUS[19] ,MSI Interrupt 19 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 18. " MSI0_RAW_STATUS[18] ,MSI Interrupt 18 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 17. " MSI0_RAW_STATUS[17] ,MSI Interrupt 17 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 16. " MSI0_RAW_STATUS[16] ,MSI Interrupt 16 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 15. " MSI0_RAW_STATUS[15] ,MSI Interrupt 15 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 14. " MSI0_RAW_STATUS[14] ,MSI Interrupt 14 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 13. " MSI0_RAW_STATUS[13] ,MSI Interrupt 13 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 12. " MSI0_RAW_STATUS[12] ,MSI Interrupt 12 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 11. " MSI0_RAW_STATUS[11] ,MSI Interrupt 11 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " MSI0_RAW_STATUS[10] ,MSI Interrupt 10 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " MSI0_RAW_STATUS[9] ,MSI Interrupt 9 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " MSI0_RAW_STATUS[8] ,MSI Interrupt 8 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 7. " MSI0_RAW_STATUS[7] ,MSI Interrupt 7 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 6. " MSI0_RAW_STATUS[6] ,MSI Interrupt 6 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 5. " MSI0_RAW_STATUS[5] ,MSI Interrupt 5 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 4. " MSI0_RAW_STATUS[4] ,MSI Interrupt 4 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 3. " MSI0_RAW_STATUS[3] ,MSI Interrupt 3 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 2. " MSI0_RAW_STATUS[2] ,MSI Interrupt 2 Raw Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 1. " MSI0_RAW_STATUS[1] ,MSI Interrupt 1 Raw Status" "No interrupt,Interrupt"
bitfld.long 0x00 0. " MSI0_RAW_STATUS[0] ,MSI Interrupt 0 Raw Status" "No interrupt,Interrupt"
line.long 0x04 "MSI0_IRQ_STATUS,MSI 0 Interrupt Enabled Status"
bitfld.long 0x04 31. " MSI0_IRQ_STATUS[31] ,MSI Interrupt 31 Status" "No interrupt,Interrupt"
bitfld.long 0x04 30. " MSI0_IRQ_STATUS[30] ,MSI Interrupt 30 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 29. " MSI0_IRQ_STATUS[29] ,MSI Interrupt 29 Status" "No interrupt,Interrupt"
bitfld.long 0x04 28. " MSI0_IRQ_STATUS[28] ,MSI Interrupt 28 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 27. " MSI0_IRQ_STATUS[27] ,MSI Interrupt 27 Status" "No interrupt,Interrupt"
bitfld.long 0x04 26. " MSI0_IRQ_STATUS[26] ,MSI Interrupt 26 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 25. " MSI0_IRQ_STATUS[25] ,MSI Interrupt 25 Status" "No interrupt,Interrupt"
bitfld.long 0x04 24. " MSI0_IRQ_STATUS[24] ,MSI Interrupt 24 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 23. " MSI0_IRQ_STATUS[23] ,MSI Interrupt 23 Status" "No interrupt,Interrupt"
bitfld.long 0x04 22. " MSI0_IRQ_STATUS[22] ,MSI Interrupt 22 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 21. " MSI0_IRQ_STATUS[21] ,MSI Interrupt 21 Status" "No interrupt,Interrupt"
bitfld.long 0x04 20. " MSI0_IRQ_STATUS[20] ,MSI Interrupt 20 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 19. " MSI0_IRQ_STATUS[19] ,MSI Interrupt 19 Status" "No interrupt,Interrupt"
bitfld.long 0x04 18. " MSI0_IRQ_STATUS[18] ,MSI Interrupt 18 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 17. " MSI0_IRQ_STATUS[17] ,MSI Interrupt 17 Status" "No interrupt,Interrupt"
bitfld.long 0x04 16. " MSI0_IRQ_STATUS[16] ,MSI Interrupt 16 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 15. " MSI0_IRQ_STATUS[15] ,MSI Interrupt 15 Status" "No interrupt,Interrupt"
bitfld.long 0x04 14. " MSI0_IRQ_STATUS[14] ,MSI Interrupt 14 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 13. " MSI0_IRQ_STATUS[13] ,MSI Interrupt 13 Status" "No interrupt,Interrupt"
bitfld.long 0x04 12. " MSI0_IRQ_STATUS[12] ,MSI Interrupt 12 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 11. " MSI0_IRQ_STATUS[11] ,MSI Interrupt 11 Status" "No interrupt,Interrupt"
bitfld.long 0x04 10. " MSI0_IRQ_STATUS[10] ,MSI Interrupt 10 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 9. " MSI0_IRQ_STATUS[9] ,MSI Interrupt 9 Status" "No interrupt,Interrupt"
bitfld.long 0x04 8. " MSI0_IRQ_STATUS[8] ,MSI Interrupt 8 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 7. " MSI0_IRQ_STATUS[7] ,MSI Interrupt 7 Status" "No interrupt,Interrupt"
bitfld.long 0x04 6. " MSI0_IRQ_STATUS[6] ,MSI Interrupt 6 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 5. " MSI0_IRQ_STATUS[5] ,MSI Interrupt 5 Status" "No interrupt,Interrupt"
bitfld.long 0x04 4. " MSI0_IRQ_STATUS[4] ,MSI Interrupt 4 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 3. " MSI0_IRQ_STATUS[3] ,MSI Interrupt 3 Status" "No interrupt,Interrupt"
bitfld.long 0x04 2. " MSI0_IRQ_STATUS[2] ,MSI Interrupt 2 Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 1. " MSI0_IRQ_STATUS[1] ,MSI Interrupt 1 Status" "No interrupt,Interrupt"
bitfld.long 0x04 0. " MSI0_IRQ_STATUS[0] ,MSI Interrupt 0 Status" "No interrupt,Interrupt"
line.long 0x08 "MSI0_IRQ_ENABLE_SET,MSI 0 Interrupt Enable Set"
bitfld.long 0x08 31. " MSI0_IRQ_ENABLE_SET[31] ,MSI Interrupt 31 Set" "Disabled,Enabled"
bitfld.long 0x08 30. " MSI0_IRQ_ENABLE_SET[30] ,MSI Interrupt 30 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 29. " MSI0_IRQ_ENABLE_SET[29] ,MSI Interrupt 29 Set" "Disabled,Enabled"
bitfld.long 0x08 28. " MSI0_IRQ_ENABLE_SET[28] ,MSI Interrupt 28 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 27. " MSI0_IRQ_ENABLE_SET[27] ,MSI Interrupt 27 Set" "Disabled,Enabled"
bitfld.long 0x08 26. " MSI0_IRQ_ENABLE_SET[26] ,MSI Interrupt 26 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 25. " MSI0_IRQ_ENABLE_SET[25] ,MSI Interrupt 25 Set" "Disabled,Enabled"
bitfld.long 0x08 24. " MSI0_IRQ_ENABLE_SET[24] ,MSI Interrupt 24 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 23. " MSI0_IRQ_ENABLE_SET[23] ,MSI Interrupt 23 Set" "Disabled,Enabled"
bitfld.long 0x08 22. " MSI0_IRQ_ENABLE_SET[22] ,MSI Interrupt 22 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " MSI0_IRQ_ENABLE_SET[21] ,MSI Interrupt 21 Set" "Disabled,Enabled"
bitfld.long 0x08 20. " MSI0_IRQ_ENABLE_SET[20] ,MSI Interrupt 20 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " MSI0_IRQ_ENABLE_SET[19] ,MSI Interrupt 19 Set" "Disabled,Enabled"
bitfld.long 0x08 18. " MSI0_IRQ_ENABLE_SET[18] ,MSI Interrupt 18 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " MSI0_IRQ_ENABLE_SET[17] ,MSI Interrupt 17 Set" "Disabled,Enabled"
bitfld.long 0x08 16. " MSI0_IRQ_ENABLE_SET[16] ,MSI Interrupt 16 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " MSI0_IRQ_ENABLE_SET[15] ,MSI Interrupt 15 Set" "Disabled,Enabled"
bitfld.long 0x08 14. " MSI0_IRQ_ENABLE_SET[14] ,MSI Interrupt 14 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 13. " MSI0_IRQ_ENABLE_SET[13] ,MSI Interrupt 13 Set" "Disabled,Enabled"
bitfld.long 0x08 12. " MSI0_IRQ_ENABLE_SET[12] ,MSI Interrupt 12 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 11. " MSI0_IRQ_ENABLE_SET[11] ,MSI Interrupt 11 Set" "Disabled,Enabled"
bitfld.long 0x08 10. " MSI0_IRQ_ENABLE_SET[10] ,MSI Interrupt 10 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " MSI0_IRQ_ENABLE_SET[9] ,MSI Interrupt 9 Set" "Disabled,Enabled"
bitfld.long 0x08 8. " MSI0_IRQ_ENABLE_SET[8] ,MSI Interrupt 8 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 7. " MSI0_IRQ_ENABLE_SET[7] ,MSI Interrupt 7 Set" "Disabled,Enabled"
bitfld.long 0x08 6. " MSI0_IRQ_ENABLE_SET[6] ,MSI Interrupt 6 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 5. " MSI0_IRQ_ENABLE_SET[5] ,MSI Interrupt 5 Set" "Disabled,Enabled"
bitfld.long 0x08 4. " MSI0_IRQ_ENABLE_SET[4] ,MSI Interrupt 4 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " MSI0_IRQ_ENABLE_SET[3] ,MSI Interrupt 3 Set" "Disabled,Enabled"
bitfld.long 0x08 2. " MSI0_IRQ_ENABLE_SET[2] ,MSI Interrupt 2 Set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " MSI0_IRQ_ENABLE_SET[1] ,MSI Interrupt 1 Set" "Disabled,Enabled"
bitfld.long 0x08 0. " MSI0_IRQ_ENABLE_SET[0] ,MSI Interrupt 0 Set" "Disabled,Enabled"
line.long 0x0C "MSI0_IRQ_ENABLE_CLR,MSI 0 Interrupt Enable Clear"
eventfld.long 0x0C 31. " MSI0_IRQ_ENABLE_CLR[31] ,MSI Interrupt 31 Clear" "Disabled,Enabled"
eventfld.long 0x0C 30. " MSI0_IRQ_ENABLE_CLR[30] ,MSI Interrupt 30 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 29. " MSI0_IRQ_ENABLE_CLR[29] ,MSI Interrupt 29 Clear" "Disabled,Enabled"
eventfld.long 0x0C 28. " MSI0_IRQ_ENABLE_CLR[28] ,MSI Interrupt 28 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 27. " MSI0_IRQ_ENABLE_CLR[27] ,MSI Interrupt 27 Clear" "Disabled,Enabled"
eventfld.long 0x0C 26. " MSI0_IRQ_ENABLE_CLR[26] ,MSI Interrupt 26 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 25. " MSI0_IRQ_ENABLE_CLR[25] ,MSI Interrupt 25 Clear" "Disabled,Enabled"
eventfld.long 0x0C 24. " MSI0_IRQ_ENABLE_CLR[24] ,MSI Interrupt 24 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 23. " MSI0_IRQ_ENABLE_CLR[23] ,MSI Interrupt 23 Clear" "Disabled,Enabled"
eventfld.long 0x0C 22. " MSI0_IRQ_ENABLE_CLR[22] ,MSI Interrupt 22 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 21. " MSI0_IRQ_ENABLE_CLR[21] ,MSI Interrupt 21 Clear" "Disabled,Enabled"
eventfld.long 0x0C 20. " MSI0_IRQ_ENABLE_CLR[20] ,MSI Interrupt 20 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 19. " MSI0_IRQ_ENABLE_CLR[19] ,MSI Interrupt 19 Clear" "Disabled,Enabled"
eventfld.long 0x0C 18. " MSI0_IRQ_ENABLE_CLR[18] ,MSI Interrupt 18 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 17. " MSI0_IRQ_ENABLE_CLR[17] ,MSI Interrupt 17 Clear" "Disabled,Enabled"
eventfld.long 0x0C 16. " MSI0_IRQ_ENABLE_CLR[16] ,MSI Interrupt 16 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 15. " MSI0_IRQ_ENABLE_CLR[15] ,MSI Interrupt 15 Clear" "Disabled,Enabled"
eventfld.long 0x0C 14. " MSI0_IRQ_ENABLE_CLR[14] ,MSI Interrupt 14 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 13. " MSI0_IRQ_ENABLE_CLR[13] ,MSI Interrupt 13 Clear" "Disabled,Enabled"
eventfld.long 0x0C 12. " MSI0_IRQ_ENABLE_CLR[12] ,MSI Interrupt 12 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 11. " MSI0_IRQ_ENABLE_CLR[11] ,MSI Interrupt 11 Clear" "Disabled,Enabled"
eventfld.long 0x0C 10. " MSI0_IRQ_ENABLE_CLR[10] ,MSI Interrupt 10 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 9. " MSI0_IRQ_ENABLE_CLR[9] ,MSI Interrupt 9 Clear" "Disabled,Enabled"
eventfld.long 0x0C 8. " MSI0_IRQ_ENABLE_CLR[8] ,MSI Interrupt 8 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 7. " MSI0_IRQ_ENABLE_CLR[7] ,MSI Interrupt 7 Clear" "Disabled,Enabled"
eventfld.long 0x0C 6. " MSI0_IRQ_ENABLE_CLR[6] ,MSI Interrupt 6 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 5. " MSI0_IRQ_ENABLE_CLR[5] ,MSI Interrupt 5 Clear" "Disabled,Enabled"
eventfld.long 0x0C 4. " MSI0_IRQ_ENABLE_CLR[4] ,MSI Interrupt 4 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 3. " MSI0_IRQ_ENABLE_CLR[3] ,MSI Interrupt 3 Clear" "Disabled,Enabled"
eventfld.long 0x0C 2. " MSI0_IRQ_ENABLE_CLR[2] ,MSI Interrupt 2 Clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 1. " MSI0_IRQ_ENABLE_CLR[1] ,MSI Interrupt 1 Clear" "Disabled,Enabled"
eventfld.long 0x0C 0. " MSI0_IRQ_ENABLE_CLR[0] ,MSI Interrupt 0 Clear" "Disabled,Enabled"
group.long 0x180++0x0F
line.long 0x00 "IRQ_STATUS_RAW,Raw Interrupt Status (RC mode)"
bitfld.long 0x00 3. " INTD ,Legacy Interrupt D raw status" "No interupt,Interrupt"
bitfld.long 0x00 2. " INTC ,Legacy Interrupt C raw status" "No interupt,Interrupt"
textline " "
bitfld.long 0x00 1. " INTB ,Legacy Interrupt B raw status" "No interupt,Interrupt"
bitfld.long 0x00 0. " INTA ,Legacy Interrupt A raw status" "No interupt,Interrupt"
line.long 0x04 "IRQ_STATUS,Interrupt Enabled Status"
bitfld.long 0x04 3. " INTD ,Legacy Interrupt D status" "No interupt,Interrupt"
bitfld.long 0x04 2. " INTC ,Legacy Interrupt C status" "No interupt,Interrupt"
textline " "
bitfld.long 0x04 1. " INTB ,Legacy Interrupt B status" "No interupt,Interrupt"
bitfld.long 0x04 0. " INTA ,Legacy Interrupt A status" "No interupt,Interrupt"
line.long 0x08 "IRQ_ENABLE_SET,Interrupt Enable Set"
bitfld.long 0x08 3. " INTD ,Legacy Interrupt D set" "Disabled,Enabled"
bitfld.long 0x08 2. " INTC ,Legacy Interrupt C set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " INTB ,Legacy Interrupt B set" "Disabled,Enabled"
bitfld.long 0x08 0. " INTA ,Legacy Interrupt A set" "Disabled,Enabled"
line.long 0x0C "IRQ_ENABLE_CLR,Interrupt Enable Clearr"
eventfld.long 0x0C 3. " INTD ,Legacy Interrupt D clear" "Disabled,Enabled"
eventfld.long 0x0C 2. " INTC ,Legacy Interrupt C clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 1. " INTB ,Legacy Interrupt B clear" "Disabled,Enabled"
eventfld.long 0x0C 0. " INTA ,Legacy Interrupt A clear" "Disabled,Enabled"
group.long 0x1C0++0x1F
line.long 0x00 "ERR_IRQ_STATUS_RAW,Raw ERR Interrupt Status"
bitfld.long 0x00 5. " ERR_AER ,ECRC error raw status" "No error,Error"
bitfld.long 0x00 4. " ERR_AXI ,AXI tag lookup fatal error raw status" "No error,Error"
textline " "
bitfld.long 0x00 3. " ERR_CORR ,Correctable error raw status" "No error,Error"
bitfld.long 0x00 2. " ERR_NONFATAL ,Nonfatal error raw status" "No error,Error"
textline " "
bitfld.long 0x00 1. " ERR_FATAL ,Fatal error raw status" "No error,Error"
bitfld.long 0x00 0. " ERR_SYS ,System Error raw status" "No error,Error"
line.long 0x04 "ERR_IRQ_STATUS,ERR Interrupt Enabled Status"
bitfld.long 0x04 5. " ERR_AER ,ECRC error status" "No error,Error"
bitfld.long 0x04 4. " ERR_AXI ,AXI tag lookup fatal error status" "No error,Error"
textline " "
bitfld.long 0x04 3. " ERR_CORR ,Correctable error status" "No error,Error"
bitfld.long 0x04 2. " ERR_NONFATAL ,Nonfatal error status" "No error,Error"
textline " "
bitfld.long 0x04 1. " ERR_FATAL ,Fatal error status" "No error,Error"
bitfld.long 0x04 0. " ERR_SYS ,System Error status" "No error,Error"
line.long 0x08 "ERR_IRQ_ENABLE_SET,ERR Interrupt Enable Set"
bitfld.long 0x08 5. " ERR_AER ,ECRC error interrupt set " "Disabled,Enabled"
bitfld.long 0x08 4. " ERR_AXI ,AXI tag lookup fatal error interrupt set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " ERR_CORR ,Correctable error interrupt set" "Disabled,Enabled"
bitfld.long 0x08 2. " ERR_NONFATAL ,Nonfatal error interrupt set" "Disabled,Enabled"
textline " "
bitfld.long 0x08 1. " ERR_FATAL ,Fatal error interrupt set" "Disabled,Enabled"
bitfld.long 0x08 0. " ERR_SYS ,System error interrupt set" "Disabled,Enabled"
line.long 0x0C "ERR_IRQ_ENABLE_CLR,ERR Interrupt Enable Clear"
eventfld.long 0x0C 5. " ERR_AER ,ECRC error interrupt clear" "Disabled,Enabled"
eventfld.long 0x0C 4. " ERR_AXI ,AXI tag lookup fatal error interrupt clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 3. " ERR_CORR ,Correctable error interrupt clear" "Disabled,Enabled"
eventfld.long 0x0C 2. " ERR_NONFATAL ,Nonfatal error interrupt clear" "Disabled,Enabled"
textline " "
eventfld.long 0x0C 1. " ERR_FATAL ,Fatal error interrupt clear" "Disabled,Enabled"
eventfld.long 0x0C 0. " ERR_SYS ,System error interrupt clear" "Disabled,Enabled"
line.long 0x10 "PMRST_IRQ_STATUS_RAW,Power Management and Reset Interrupt Status"
bitfld.long 0x10 3. " LINK_RST_REQ ,Link Request Reset interrupt raw status" "No interrupt,Interrupt"
bitfld.long 0x10 2. " PM_PME ,Power Management PME message received interrupt raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x10 1. " PM_TO_ACK ,Power Management ACK received interrupt raw status" "No interrupt,Interrupt"
bitfld.long 0x10 0. " PM_TURNOFF ,Power Management Turnoff message received raw status" "No interrupt,Interrupt"
line.long 0x14 "PMRST_IRQ_STATUS,Power Management and Reset Interrupt Enabled Status"
bitfld.long 0x14 3. " LINK_RST_REQ ,Link Request Reset interrupt status" "No interrupt,Interrupt"
bitfld.long 0x14 2. " PM_PME ,Power Management PME message received interrupt status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x14 1. " PM_TO_ACK ,Power Management ACK received interrupt status" "No interrupt,Interrupt"
bitfld.long 0x14 0. " PM_TURNOFF ,Power Management Turnoff message received status" "No interrupt,Interrupt"
line.long 0x18 "PMRST_ENABLE_SET,Power Management and Reset Interrupt Enable Set"
bitfld.long 0x18 3. " LINK_RST_REQ ,Link Request Reset interrupt set" "Disabled,Enabled"
bitfld.long 0x18 2. " PM_PME ,Power Management PME message received interrupt set" "Disabled,Enabled"
textline " "
bitfld.long 0x18 1. " PM_TO_ACK ,Power Management ACK received interrupt set" "Disabled,Enabled"
bitfld.long 0x18 0. " PM_TURNOFF ,Power Management Turnoff message received set" "Disabled,Enabled"
line.long 0x1C "PMRST_ENABLE_CLR,Power Management and Reset Interrupt Enable Clear"
eventfld.long 0x1C 3. " LINK_RST_REQ ,Link Request Reset interrupt clear" "Disabled,Enabled"
eventfld.long 0x1C 2. " PM_PME ,Power Management PME message received interrupt clear" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 1. " PM_TO_ACK ,Power Management ACK received interrupt clear" "Disabled,Enabled"
eventfld.long 0x1C 0. " PM_TURNOFF ,Power Management Turnoff message received clear" "Disabled,Enabled"
group.long 0x200++0x13F
line.long 0x0 "OB_OFFSET_INDEX0,Outbound Translation Region 0 Offset Low and Index"
hexmask.long.word 0x0 20.--31. 0x10 " OB_OFFSET0_LO ,Offset bits for translation region 0"
bitfld.long 0x0 0. " OB_ENABLE0 ,Enable translation region 0" "Disabled,Enabled"
line.long (0x0+0x04) "OB_OFFSET0_HI,OB_OFFSET0_HI Register"
line.long 0x8 "OB_OFFSET_INDEX1,Outbound Translation Region 1 Offset Low and Index"
hexmask.long.word 0x8 20.--31. 0x10 " OB_OFFSET1_LO ,Offset bits for translation region 1"
bitfld.long 0x8 0. " OB_ENABLE1 ,Enable translation region 1" "Disabled,Enabled"
line.long (0x8+0x04) "OB_OFFSET1_HI,OB_OFFSET1_HI Register"
line.long 0x10 "OB_OFFSET_INDEX2,Outbound Translation Region 2 Offset Low and Index"
hexmask.long.word 0x10 20.--31. 0x10 " OB_OFFSET2_LO ,Offset bits for translation region 2"
bitfld.long 0x10 0. " OB_ENABLE2 ,Enable translation region 2" "Disabled,Enabled"
line.long (0x10+0x04) "OB_OFFSET2_HI,OB_OFFSET2_HI Register"
line.long 0x18 "OB_OFFSET_INDEX3,Outbound Translation Region 3 Offset Low and Index"
hexmask.long.word 0x18 20.--31. 0x10 " OB_OFFSET3_LO ,Offset bits for translation region 3"
bitfld.long 0x18 0. " OB_ENABLE3 ,Enable translation region 3" "Disabled,Enabled"
line.long (0x18+0x04) "OB_OFFSET3_HI,OB_OFFSET3_HI Register"
line.long 0x20 "OB_OFFSET_INDEX4,Outbound Translation Region 4 Offset Low and Index"
hexmask.long.word 0x20 20.--31. 0x10 " OB_OFFSET4_LO ,Offset bits for translation region 4"
bitfld.long 0x20 0. " OB_ENABLE4 ,Enable translation region 4" "Disabled,Enabled"
line.long (0x20+0x04) "OB_OFFSET4_HI,OB_OFFSET4_HI Register"
line.long 0x28 "OB_OFFSET_INDEX5,Outbound Translation Region 5 Offset Low and Index"
hexmask.long.word 0x28 20.--31. 0x10 " OB_OFFSET5_LO ,Offset bits for translation region 5"
bitfld.long 0x28 0. " OB_ENABLE5 ,Enable translation region 5" "Disabled,Enabled"
line.long (0x28+0x04) "OB_OFFSET5_HI,OB_OFFSET5_HI Register"
line.long 0x30 "OB_OFFSET_INDEX6,Outbound Translation Region 6 Offset Low and Index"
hexmask.long.word 0x30 20.--31. 0x10 " OB_OFFSET6_LO ,Offset bits for translation region 6"
bitfld.long 0x30 0. " OB_ENABLE6 ,Enable translation region 6" "Disabled,Enabled"
line.long (0x30+0x04) "OB_OFFSET6_HI,OB_OFFSET6_HI Register"
line.long 0x38 "OB_OFFSET_INDEX7,Outbound Translation Region 7 Offset Low and Index"
hexmask.long.word 0x38 20.--31. 0x10 " OB_OFFSET7_LO ,Offset bits for translation region 7"
bitfld.long 0x38 0. " OB_ENABLE7 ,Enable translation region 7" "Disabled,Enabled"
line.long (0x38+0x04) "OB_OFFSET7_HI,OB_OFFSET7_HI Register"
line.long 0x40 "OB_OFFSET_INDEX8,Outbound Translation Region 8 Offset Low and Index"
hexmask.long.word 0x40 20.--31. 0x10 " OB_OFFSET8_LO ,Offset bits for translation region 8"
bitfld.long 0x40 0. " OB_ENABLE8 ,Enable translation region 8" "Disabled,Enabled"
line.long (0x40+0x04) "OB_OFFSET8_HI,OB_OFFSET8_HI Register"
line.long 0x48 "OB_OFFSET_INDEX9,Outbound Translation Region 9 Offset Low and Index"
hexmask.long.word 0x48 20.--31. 0x10 " OB_OFFSET9_LO ,Offset bits for translation region 9"
bitfld.long 0x48 0. " OB_ENABLE9 ,Enable translation region 9" "Disabled,Enabled"
line.long (0x48+0x04) "OB_OFFSET9_HI,OB_OFFSET9_HI Register"
line.long 0x50 "OB_OFFSET_INDEX10,Outbound Translation Region 10 Offset Low and Index"
hexmask.long.word 0x50 20.--31. 0x10 " OB_OFFSET10_LO ,Offset bits for translation region 10"
bitfld.long 0x50 0. " OB_ENABLE10 ,Enable translation region 10" "Disabled,Enabled"
line.long (0x50+0x04) "OB_OFFSET10_HI,OB_OFFSET10_HI Register"
line.long 0x58 "OB_OFFSET_INDEX11,Outbound Translation Region 11 Offset Low and Index"
hexmask.long.word 0x58 20.--31. 0x10 " OB_OFFSET11_LO ,Offset bits for translation region 11"
bitfld.long 0x58 0. " OB_ENABLE11 ,Enable translation region 11" "Disabled,Enabled"
line.long (0x58+0x04) "OB_OFFSET11_HI,OB_OFFSET11_HI Register"
line.long 0x60 "OB_OFFSET_INDEX12,Outbound Translation Region 12 Offset Low and Index"
hexmask.long.word 0x60 20.--31. 0x10 " OB_OFFSET12_LO ,Offset bits for translation region 12"
bitfld.long 0x60 0. " OB_ENABLE12 ,Enable translation region 12" "Disabled,Enabled"
line.long (0x60+0x04) "OB_OFFSET12_HI,OB_OFFSET12_HI Register"
line.long 0x68 "OB_OFFSET_INDEX13,Outbound Translation Region 13 Offset Low and Index"
hexmask.long.word 0x68 20.--31. 0x10 " OB_OFFSET13_LO ,Offset bits for translation region 13"
bitfld.long 0x68 0. " OB_ENABLE13 ,Enable translation region 13" "Disabled,Enabled"
line.long (0x68+0x04) "OB_OFFSET13_HI,OB_OFFSET13_HI Register"
line.long 0x70 "OB_OFFSET_INDEX14,Outbound Translation Region 14 Offset Low and Index"
hexmask.long.word 0x70 20.--31. 0x10 " OB_OFFSET14_LO ,Offset bits for translation region 14"
bitfld.long 0x70 0. " OB_ENABLE14 ,Enable translation region 14" "Disabled,Enabled"
line.long (0x70+0x04) "OB_OFFSET14_HI,OB_OFFSET14_HI Register"
line.long 0x78 "OB_OFFSET_INDEX15,Outbound Translation Region 15 Offset Low and Index"
hexmask.long.word 0x78 20.--31. 0x10 " OB_OFFSET15_LO ,Offset bits for translation region 15"
bitfld.long 0x78 0. " OB_ENABLE15 ,Enable translation region 15" "Disabled,Enabled"
line.long (0x78+0x04) "OB_OFFSET15_HI,OB_OFFSET15_HI Register"
line.long 0x80 "OB_OFFSET_INDEX16,Outbound Translation Region 16 Offset Low and Index"
hexmask.long.word 0x80 20.--31. 0x10 " OB_OFFSET16_LO ,Offset bits for translation region 16"
bitfld.long 0x80 0. " OB_ENABLE16 ,Enable translation region 16" "Disabled,Enabled"
line.long (0x80+0x04) "OB_OFFSET16_HI,OB_OFFSET16_HI Register"
line.long 0x88 "OB_OFFSET_INDEX17,Outbound Translation Region 17 Offset Low and Index"
hexmask.long.word 0x88 20.--31. 0x10 " OB_OFFSET17_LO ,Offset bits for translation region 17"
bitfld.long 0x88 0. " OB_ENABLE17 ,Enable translation region 17" "Disabled,Enabled"
line.long (0x88+0x04) "OB_OFFSET17_HI,OB_OFFSET17_HI Register"
line.long 0x90 "OB_OFFSET_INDEX18,Outbound Translation Region 18 Offset Low and Index"
hexmask.long.word 0x90 20.--31. 0x10 " OB_OFFSET18_LO ,Offset bits for translation region 18"
bitfld.long 0x90 0. " OB_ENABLE18 ,Enable translation region 18" "Disabled,Enabled"
line.long (0x90+0x04) "OB_OFFSET18_HI,OB_OFFSET18_HI Register"
line.long 0x98 "OB_OFFSET_INDEX19,Outbound Translation Region 19 Offset Low and Index"
hexmask.long.word 0x98 20.--31. 0x10 " OB_OFFSET19_LO ,Offset bits for translation region 19"
bitfld.long 0x98 0. " OB_ENABLE19 ,Enable translation region 19" "Disabled,Enabled"
line.long (0x98+0x04) "OB_OFFSET19_HI,OB_OFFSET19_HI Register"
line.long 0xA0 "OB_OFFSET_INDEX20,Outbound Translation Region 20 Offset Low and Index"
hexmask.long.word 0xA0 20.--31. 0x10 " OB_OFFSET20_LO ,Offset bits for translation region 20"
bitfld.long 0xA0 0. " OB_ENABLE20 ,Enable translation region 20" "Disabled,Enabled"
line.long (0xA0+0x04) "OB_OFFSET20_HI,OB_OFFSET20_HI Register"
line.long 0xA8 "OB_OFFSET_INDEX21,Outbound Translation Region 21 Offset Low and Index"
hexmask.long.word 0xA8 20.--31. 0x10 " OB_OFFSET21_LO ,Offset bits for translation region 21"
bitfld.long 0xA8 0. " OB_ENABLE21 ,Enable translation region 21" "Disabled,Enabled"
line.long (0xA8+0x04) "OB_OFFSET21_HI,OB_OFFSET21_HI Register"
line.long 0xB0 "OB_OFFSET_INDEX22,Outbound Translation Region 22 Offset Low and Index"
hexmask.long.word 0xB0 20.--31. 0x10 " OB_OFFSET22_LO ,Offset bits for translation region 22"
bitfld.long 0xB0 0. " OB_ENABLE22 ,Enable translation region 22" "Disabled,Enabled"
line.long (0xB0+0x04) "OB_OFFSET22_HI,OB_OFFSET22_HI Register"
line.long 0xB8 "OB_OFFSET_INDEX23,Outbound Translation Region 23 Offset Low and Index"
hexmask.long.word 0xB8 20.--31. 0x10 " OB_OFFSET23_LO ,Offset bits for translation region 23"
bitfld.long 0xB8 0. " OB_ENABLE23 ,Enable translation region 23" "Disabled,Enabled"
line.long (0xB8+0x04) "OB_OFFSET23_HI,OB_OFFSET23_HI Register"
line.long 0xC0 "OB_OFFSET_INDEX24,Outbound Translation Region 24 Offset Low and Index"
hexmask.long.word 0xC0 20.--31. 0x10 " OB_OFFSET24_LO ,Offset bits for translation region 24"
bitfld.long 0xC0 0. " OB_ENABLE24 ,Enable translation region 24" "Disabled,Enabled"
line.long (0xC0+0x04) "OB_OFFSET24_HI,OB_OFFSET24_HI Register"
line.long 0xC8 "OB_OFFSET_INDEX25,Outbound Translation Region 25 Offset Low and Index"
hexmask.long.word 0xC8 20.--31. 0x10 " OB_OFFSET25_LO ,Offset bits for translation region 25"
bitfld.long 0xC8 0. " OB_ENABLE25 ,Enable translation region 25" "Disabled,Enabled"
line.long (0xC8+0x04) "OB_OFFSET25_HI,OB_OFFSET25_HI Register"
line.long 0xD0 "OB_OFFSET_INDEX26,Outbound Translation Region 26 Offset Low and Index"
hexmask.long.word 0xD0 20.--31. 0x10 " OB_OFFSET26_LO ,Offset bits for translation region 26"
bitfld.long 0xD0 0. " OB_ENABLE26 ,Enable translation region 26" "Disabled,Enabled"
line.long (0xD0+0x04) "OB_OFFSET26_HI,OB_OFFSET26_HI Register"
line.long 0xD8 "OB_OFFSET_INDEX27,Outbound Translation Region 27 Offset Low and Index"
hexmask.long.word 0xD8 20.--31. 0x10 " OB_OFFSET27_LO ,Offset bits for translation region 27"
bitfld.long 0xD8 0. " OB_ENABLE27 ,Enable translation region 27" "Disabled,Enabled"
line.long (0xD8+0x04) "OB_OFFSET27_HI,OB_OFFSET27_HI Register"
line.long 0xE0 "OB_OFFSET_INDEX28,Outbound Translation Region 28 Offset Low and Index"
hexmask.long.word 0xE0 20.--31. 0x10 " OB_OFFSET28_LO ,Offset bits for translation region 28"
bitfld.long 0xE0 0. " OB_ENABLE28 ,Enable translation region 28" "Disabled,Enabled"
line.long (0xE0+0x04) "OB_OFFSET28_HI,OB_OFFSET28_HI Register"
line.long 0xE8 "OB_OFFSET_INDEX29,Outbound Translation Region 29 Offset Low and Index"
hexmask.long.word 0xE8 20.--31. 0x10 " OB_OFFSET29_LO ,Offset bits for translation region 29"
bitfld.long 0xE8 0. " OB_ENABLE29 ,Enable translation region 29" "Disabled,Enabled"
line.long (0xE8+0x04) "OB_OFFSET29_HI,OB_OFFSET29_HI Register"
line.long 0xF0 "OB_OFFSET_INDEX30,Outbound Translation Region 30 Offset Low and Index"
hexmask.long.word 0xF0 20.--31. 0x10 " OB_OFFSET30_LO ,Offset bits for translation region 30"
bitfld.long 0xF0 0. " OB_ENABLE30 ,Enable translation region 30" "Disabled,Enabled"
line.long (0xF0+0x04) "OB_OFFSET30_HI,OB_OFFSET30_HI Register"
line.long 0xF8 "OB_OFFSET_INDEX31,Outbound Translation Region 31 Offset Low and Index"
hexmask.long.word 0xF8 20.--31. 0x10 " OB_OFFSET31_LO ,Offset bits for translation region 31"
bitfld.long 0xF8 0. " OB_ENABLE31 ,Enable translation region 31" "Disabled,Enabled"
line.long (0xF8+0x04) "OB_OFFSET31_HI,OB_OFFSET31_HI Register"
line.long 0x100 "IB_BAR0,IInbound Translation Bar Match 0"
bitfld.long 0x100 0.--2. " IB_BAR0 ,BAR number to match for inbound translation region 0" "0,1,2,3,4,5,6,7"
line.long (0x100+0x04) "IB_START0_LO,Inbound Translation 0 Start Address Low"
hexmask.long.tbyte (0x100+0x04) 8.--31. 1. " IB_START0_LO ,Start address bits for inbound translation region 0"
line.long (0x100+0x08) "IB_START0_HI,Inbound Translation 0 Start Address High"
line.long (0x100+0x0C) "IB_OFFSET0,Inbound Translation 0 Address Offset"
hexmask.long.tbyte (0x100+0x0C) 8.--31. 1. " IB_OFFSET0 ,Offset address bits for inbound translation region 0"
line.long 0x110 "IB_BAR1,IInbound Translation Bar Match 1"
bitfld.long 0x110 0.--2. " IB_BAR1 ,BAR number to match for inbound translation region 1" "0,1,2,3,4,5,6,7"
line.long (0x110+0x04) "IB_START1_LO,Inbound Translation 1 Start Address Low"
hexmask.long.tbyte (0x110+0x04) 8.--31. 1. " IB_START1_LO ,Start address bits for inbound translation region 1"
line.long (0x110+0x08) "IB_START1_HI,Inbound Translation 1 Start Address High"
line.long (0x110+0x0C) "IB_OFFSET1,Inbound Translation 1 Address Offset"
hexmask.long.tbyte (0x110+0x0C) 8.--31. 1. " IB_OFFSET1 ,Offset address bits for inbound translation region 1"
line.long 0x120 "IB_BAR2,IInbound Translation Bar Match 2"
bitfld.long 0x120 0.--2. " IB_BAR2 ,BAR number to match for inbound translation region 2" "0,1,2,3,4,5,6,7"
line.long (0x120+0x04) "IB_START2_LO,Inbound Translation 2 Start Address Low"
hexmask.long.tbyte (0x120+0x04) 8.--31. 1. " IB_START2_LO ,Start address bits for inbound translation region 2"
line.long (0x120+0x08) "IB_START2_HI,Inbound Translation 2 Start Address High"
line.long (0x120+0x0C) "IB_OFFSET2,Inbound Translation 2 Address Offset"
hexmask.long.tbyte (0x120+0x0C) 8.--31. 1. " IB_OFFSET2 ,Offset address bits for inbound translation region 2"
line.long 0x130 "IB_BAR3,IInbound Translation Bar Match 3"
bitfld.long 0x130 0.--2. " IB_BAR3 ,BAR number to match for inbound translation region 3" "0,1,2,3,4,5,6,7"
line.long (0x130+0x04) "IB_START3_LO,Inbound Translation 3 Start Address Low"
hexmask.long.tbyte (0x130+0x04) 8.--31. 1. " IB_START3_LO ,Start address bits for inbound translation region 3"
line.long (0x130+0x08) "IB_START3_HI,Inbound Translation 3 Start Address High"
line.long (0x130+0x0C) "IB_OFFSET3,Inbound Translation 3 Address Offset"
hexmask.long.tbyte (0x130+0x0C) 8.--31. 1. " IB_OFFSET3 ,Offset address bits for inbound translation region 3"
group.long 0x380++0x07
line.long 0x00 "PCS_CFG0,PCS Configuration 0"
bitfld.long 0x00 24.--28. " PCS_SYNC ,Receiver Lock/Sync Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x00 16.--23. 1. " PCS_HOLDOFF ,Receiver Initialization Hold Off Control"
textline " "
bitfld.long 0x00 12.--13. " PCS_RC_DELAY ,Rate Change Delay" "0,1,2,3"
bitfld.long 0x00 8.--11. " PCS_DET_DELAY ,Detection Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x00 7. " PCS_SHRT_TM ,Enable short times for debug purposes" "Disabled,Enabled"
bitfld.long 0x00 6. " PCS_STAT186 ,Enable PIPE Spec 1.86 for PHY status behavior" "Disabled,Enabled"
textline " "
bitfld.long 0x00 5. " PCS_FIX_TERM ,Fed term output to 3'b100 during reset" "Not fed,Fed"
bitfld.long 0x00 4. " PCS_FIX_STD ,Fix std output to 2'b10" "Not fixed,Fixed"
textline " "
bitfld.long 0x00 3. " PCS_L2_ENIDL_OFF ,Deassert ENIDL during L2 state" "Asserted,Deasserted"
bitfld.long 0x00 2. " PCS_L0S_RX_OFF ,Deassert Rx Enable in L0s state" "Asserted,Deasserted"
textline " "
bitfld.long 0x00 1. " PCS_RXTX_ON ,RX and TX on during reset and TX on in P1 state" "Disabled,Enabled"
bitfld.long 0x00 0. " PCS_RXTX_RST ,RX and TX on during reset" "Disabled,Enabled"
line.long 0x04 "PCS_CFG1,PCS Configuration 1"
hexmask.long.word 0x04 16.--25. 1. " PCS_ERR_BIT ,Error Bit enable"
bitfld.long 0x04 8.--9. " PCS_ERR_LN ,Error Lane enable" "0,1,2,3"
textline " "
bitfld.long 0x04 0.--1. " PCS_ERR_MODE ,Error Injection Mode" "0,1,2,3"
rgroup.long 0x388++0x03
line.long 0x00 "PCS_STATUS,PCS Status"
bitfld.long 0x00 12.--14. " PCS_REV ,PCS RTL Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--9. " PCS_LN_EN ,PCS Lanes enabled status" "0,1,2,3"
textline " "
bitfld.long 0x00 4.--5. " PCS_TX_EN ,PCS Transmitters enabled status" "0,1,2,3"
bitfld.long 0x00 0.--1. " PCS_RX_EN ,PCS Receivers enabled status" "0,1,2,3"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")
group.long 0x38C++0x03
line.long 0x00 "SERDES_STATUS,SerDes Status Register"
hexmask.long.word 0x00 16.--31. 1. " STSTX ,Serdes transmit status"
hexmask.long.word 0x00 0.--15. 1. " SRSRX ,Serdes receive status"
sif (cpuis("AM387*")||cpuis("DRA62*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
width 21.
group.long 0x390++0x27
line.long 0x00 "SERDES_RXCFG0,SerDes RX Config 0 Status Register"
bitfld.long 0x00 31. " LOOPBACK[1] ,Internal Digital loop back" "Disabled,Not supported"
bitfld.long 0x00 30. " LOOPBACK[0] ,Internal Analog loop back" "Disabled,Not supported"
textline " "
bitfld.long 0x00 29. " RX_TRIM_BYPASS ,Trim bits generated from the calibration algorithm bypass (for calibration)" "Not bypassed,Bypassed"
bitfld.long 0x00 28. " CDR_ELV_IDLE_FIX ,CDR ELV Idle fix" "Disabled,Enabled"
textline " "
bitfld.long 0x00 26.--27. " CDRAUX ,Clock/data recovery auxilliary" "0,1,2,3"
bitfld.long 0x00 24.--25. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
textline " "
bitfld.long 0x00 23. " ENOC ,Enable offset compensation" "Disabled,Enabled"
bitfld.long 0x00 19.--22. " EQ ,Equalizer" "Disabled,Enabled,?..."
textline " "
bitfld.long 0x00 16.--18. " CDR ,Clock/data recovery" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13.--15. " LOS ,Loss of signal detection" "Disabled,Disabled,Disabled,Disabled,Enabled (without CDR override control),Disabled,Enabled (with CDR override control),Disabled"
textline " "
bitfld.long 0x00 11.--12. " ALIGN ,Symbol alignment" "Disabled,Coma alignment,Alignment Jog,?..."
bitfld.long 0x00 8.--10. " TERM ,Input termination options" "Reserved,Common point set to 0.8 VDDA,Reserved,Common point floating,Common point set to VSSA,Common point set to 0.2 VDDA,Reserved,Common point floating"
textline " "
bitfld.long 0x00 7. " INVPAIR ,Inverts polarity of RXPi and RXNi" "Not inverted,Inverted"
bitfld.long 0x00 5.--6. " RATE ,Operating rate" "Full,Half,?..."
textline " "
bitfld.long 0x00 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
bitfld.long 0x00 1. " ENRXLDO ,Enable RXLDO" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " ENRX ,Enable receiver" "Disabled,Enabled"
line.long 0x04 "SERDES_RXCFG1,SerDes RX Config 1 Status Register"
bitfld.long 0x04 30.--31. " EQ_ICM_S2 ,Trims common mode pullup current in second equalizer stage" "0,1,2,3"
bitfld.long 0x04 28.--29. " EQ_ICM_S1 ,Trims common mode pullup current in first equalizer stage" "0,1,2,3"
textline " "
bitfld.long 0x04 21.--23. " EQ_I_STAGE2 ,Trims the current in the second stage of the equalizer" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 18.--20. " EQ_I_STAGEFB ,Trims the current in the feedback stage of the equalizer" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x04 15.--17. " EQ_I_STAGE1 ,Trims the current in the first stage of the equalizer" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 14. " ANALOG_LOOPBACK ,Enables analog loop back" "Disabled,Enabled"
textline " "
bitfld.long 0x04 13. " RXTRIM_CALIB ,RX trimming control to the calibration block" "Functional mode,eFuse training mode"
bitfld.long 0x04 12. " RXTRIM_BYPASS_CTRL ,RXTRIM bypass control" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7.--11. " RXTRIM_BYPASS_BITS ,Bypass bits for RXTRIM[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the calout signal inside digital (for calibration)" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " CTG_DIG_RSVD1 ,Clock inversion for rpclk" "Disabled,Enabled"
bitfld.long 0x04 4. " CTG_DIG_RSVD0 ,Clock inversion for fclk" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " ENTEST ,Enable test" "Disabled,Enabled"
bitfld.long 0x04 0.--2. " TESTPATT ,Enables and selects test patterns" "Reserved,Alternating 0/1 pattern with a period of 2 UI,7-bit LFSR with feedback polynomial x7+x6+1,23-bit LFSR with feedback polynomial x23+x18+1,31-bit LFSR with feedback polynomial x31+x28+1,?..."
line.long 0x08 "SERDES_RXCFG2,SerDes RX Config 2 Status Register"
bitfld.long 0x08 27.--31. " SAMP_BYPASS_SAD1 ,Bypass bits for SAD1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 22.--26. " SAMP_BYPASS_SAT0 ,Bypass bits for SAT0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 17.--21. " SAMP_BYPASS_SAD0 ,Bypass bits for SAD0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 12.--16. " SAMP_BYPASS_SAT1 ,Bypass bits for SAT1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0c "SERDES_RXCFG3,SerDes RX Config 3 Status Register"
bitfld.long 0x0c 31. " AMUX_EYESCAN_REF ,Connect the eyescan reference voltages to the test mux inputs" "Disabled,Enabled"
bitfld.long 0x0c 30. " SAMP_OC_SEL ,Sampler offset correction is controlled" "TRXDIG SAT1/SAD0/SAT0/SAD1,CFG_CTRL/CFGRX_2"
textline " "
bitfld.long 0x0c 24.--29. " SAMP_ES_VREF_BYPASS_BITS ,Adjusts the eyescan reference voltage level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0c 20.--23. " SAMP_ESCM_RES ,Trims the pullup resistors in the eyescan common mode loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x0c 17.--19. " SAMP_ESCM_I ,Trims the current in the eyescan common mode loop" "0,1,2,3,4,5,6,7"
bitfld.long 0x0c 16. " SAMP_3_VREF_2_ES ,Sampler 3 VREF" "EQCM,Sampler 3"
textline " "
bitfld.long 0x0c 15. " SAMP_2_VREF_2_ES ,Sampler 2 VREF" "EQCM,Sampler 2"
bitfld.long 0x0c 14. " SAMP_1_VREF_2_ES ,Sampler 1 VREF" "EQCM,Sampler 1"
textline " "
bitfld.long 0x0c 13. " SAMP_0_VREF_2_ES ,Sampler 0 VREF" "EQCM,Sampler 0"
bitfld.long 0x0c 8.--12. " SAMP_IBIAS_Z ,Adjusts the current mirror ratio in the sampler bias current block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x0c 7. " SAMP_ES_VREF_BYPASS_CTRL ,Eyescan reference offset voltage control" "IEEE1500,CFGRX_3"
bitfld.long 0x0c 3. " SAMP_EN_3_ODD ,Enable sampler 3 (odd data)" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 2. " SAMP_EN_2_EOTR ,Enable sampler 2 (even to odd transition)" "Disabled,Enabled"
bitfld.long 0x0c 1. " SAMP_EN_1_EVEN ,Enable sampler 1 (even data)" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 0. " SAMP_EN_0_OETR ,Enable sampler 0 (odd to even transition)" "Disabled,Enabled"
line.long 0x10 "SERDES_RXCFG4,SerDes RX Config 4 Status Register"
bitfld.long 0x10 28.--29. " RCLK_SAMP ,RCLK_SAMP[1:0]" "0,1,2,3"
bitfld.long 0x10 26.--27. " RCLK_DIG ,RCLK_DIG[1:0]" "0,1,2,3"
textline " "
bitfld.long 0x10 24. " DCD_EN_BUF ,DCD_EN_BUF" "Low,High"
bitfld.long 0x10 23. " DCD_EN_CLK ,DCD_EN_CLK" "Low,High"
textline " "
bitfld.long 0x10 22. " DCD_EN_M ,DCD_EN_M" "Low,High"
bitfld.long 0x10 21. " DCD_EN_P ,DCD_EN_P" "Low,High"
textline " "
bitfld.long 0x10 19. " PI_VCM_Z_0 ,PI_VCM_Z[0]" "Low,High"
bitfld.long 0x10 18. " PI_VCM_1 ,PI_VCM[1]" "Low,High"
textline " "
bitfld.long 0x10 17. " PI_VCM_Z_2 ,PI_VCM_Z[2]" "Low,High"
bitfld.long 0x10 16. " PI_VCM_Z_3 ,PI_VCM_Z[3]" "Low,High"
textline " "
bitfld.long 0x10 15. " PI_BIAS_DISABLE ,PI_BIAS_DISABLE" "No,Yes"
bitfld.long 0x10 14. " PI_ED_CAL_LEVEL_DEC ,PI_ED_CAL_LEVEL_DEC" "Low,High"
textline " "
bitfld.long 0x10 13. " PI_ED_CAL_LEVEL_INC ,PI_ED_CAL_LEVEL_INC" "Low,High"
bitfld.long 0x10 12. " PI_ED_CAL ,PI_ED_CAL" "Low,High"
textline " "
bitfld.long 0x10 11. " PI_ED_RESET ,PI_ED_RESET" "No reset,Reset"
bitfld.long 0x10 10. " PI_ED_EN ,PI_ED_EN" "Disabled,Enabled"
textline " "
bitfld.long 0x10 9. " PI_ED_VOUTP ,PI_ED_VOUTP" "Low,High"
bitfld.long 0x10 8. " PI_ED_VOUTM ,PI_ED_VOUTM" "Low,High"
textline " "
bitfld.long 0x10 7. " PI_I50U ,PI_I50U" "Low,High"
bitfld.long 0x10 6. " PI_I100U_Z ,PI_I100U_Z" "Low,High"
textline " "
bitfld.long 0x10 0.--5. " PI_IBIAS_Z ,PI_IBIAS_Z[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "SERDES_TXCFG0,SerDes TX Config 0 Status Register"
bitfld.long 0x14 28.--29. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
bitfld.long 0x14 25.--26. " DET_CTL ,Receiver detect control" "0,1,2,3"
textline " "
bitfld.long 0x14 24. " ENIDL ,Idle Control" "Disabled,Enabled"
bitfld.long 0x14 21. " TM_EXTRA_LOAD[2] ,Enable different extraload resistors to make driver constant current at speed" "Disabled,Enabled"
textline " "
bitfld.long 0x14 20. " TM_EXTRA_LOAD[1] ,Enable static dummy load during electrical idle" "Disabled,Enabled"
bitfld.long 0x14 19. " TM_EXTRA_LOAD[0] ,Enable switching dummy load during electrical idle" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13.--17. " DEEMP ,Selects one of output de-emphasis settings (PCIE/eSATA full rate/eSata half rate)" "0/0/0,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved"
bitfld.long 0x14 9.--12. " SWING ,TX Output swing selection" "148 (half),148 (half),258 (half),258 (half),295 (full/half),295 (full/half),516 (full/half),516 (full/half),774 (full/half),774 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half)"
textline " "
bitfld.long 0x14 7. " INVPAIR ,Inverts polarity of TXPi and TXNi" "Not inverted,Inverted"
bitfld.long 0x14 5.--6. " RATE ,Operating rate" "Full,Half,?..."
textline " "
bitfld.long 0x14 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
bitfld.long 0x14 1. " ENTXLDO ,TX Analog LDO" "Disabled,Enabled"
textline " "
bitfld.long 0x14 0. " ENTX ,Enable transmiter" "Disabled,Enabled"
line.long 0x18 "SERDES_TXCFG1,SerDes TX Config 1 Status Register"
bitfld.long 0x18 28.--31. " TRIM_HIGH_THRESHOLD ,4-b programmable threshold (for calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 27. " TX_DISABLE_ON_THE_FLY ,Disables the pattern match (for calibration)" "No,Yes"
textline " "
bitfld.long 0x18 26. " TX_FORCE_UPDATE ,Forces the update to be made to the Analog trim bits without looking for any specific data pattern or electrical idle (for calibration)" "Not forced,Forced"
bitfld.long 0x18 25. " TX_TRIM_BYPASS ,Bypasses the trim bits generated from the calibration algorithm (for calibration)" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x18 24. " TRIM_2B_MODE ,Enables 2-b data pattern detection mode for trim updates (for calibration)" "Disabled,Enabled"
bitfld.long 0x18 21.--22. " TRIM_STEP_CHANGE ,Step change value for staircase logic (for calibration)" "1,2,4,8"
textline " "
bitfld.long 0x18 19.--20. " TRIM_LOW_THRESHOLD ,2-b programmable threshold (for calibration)" "diff >= 1,diff >= 2,diff >= 3,diff >= 4"
bitfld.long 0x18 17.--18. " CALIB_WAIT_CYCLES ,2-b programmable number of wait cycles before polling the calout signal (for calibration)" "1 MHz clock,1 MHz clock,1 MHz clock,1 MHz clock"
textline " "
bitfld.long 0x18 16. " ENABLE_LOOP_DELAY ,Enables the additional loop delay of 40 clock cycles before sweeping the trim code during the calibration (for calibration)" "Disabled,Enabled"
bitfld.long 0x18 15. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the callout signal inside digital (for calibration)" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x18 14. " NOLCKRST ,Reset override bit during PLL unlock" "No reset,Reset"
bitfld.long 0x18 13. " ENBSPLS ,Receiver pulse boundary scan" "Disabled,Enabled"
textline " "
bitfld.long 0x18 12. " ENBSRX ,Enables IEEE 1149.6 boundary scan control of RXP and RXN" "Disabled,Enabled"
bitfld.long 0x18 11. " ENBSTX ,Enables IEEE 1149.6 boundary scan control of TXP and TXN" "Disabled,Enabled"
textline " "
bitfld.long 0x18 10. " BSINITCLK ,BS initialization clock" "Disabled,Enabled"
bitfld.long 0x18 9. " BSINRXN ,Boundary scan initialization for RXN" "Disabled,Enabled"
textline " "
bitfld.long 0x18 8. " BSINRXP ,Boundary scan initialization for RXP" "Disabled,Enabled"
bitfld.long 0x18 7. " TSYNC_ENABLE ,Tsync Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x18 6. " ENTEST ,Enable test" "Disabled,Enabled"
bitfld.long 0x18 5. " BSTX ,Boundary scan data" "Low,High"
textline " "
bitfld.long 0x18 1. " USE_STAIRCASE ,Staircase logic for trim code change (for calibration)" "Disabled,Enabled"
line.long 0x1c "SERDES_TXCFG2,SerDes TX Config 2 Status Register"
bitfld.long 0x1c 29.--30. " TM_DUMMY2IDLE ,Control ldo dummy digital load" "Disabled,1.5 mA,1.5 mA,3 mA"
bitfld.long 0x1c 27.--28. " TM_DUMMY1IDLE ,Control ldo dummy resistor load" "Disabled,6 mA,9.6 mA,15 mA"
textline " "
bitfld.long 0x1c 25.--26. " TM_TEXTRALOAD ,Driver dummy current controlled by tx_extraload" "Disabled,1 mA,2 mA,3 mA"
bitfld.long 0x1c 23. " DISABLE_FB1_TM_SRCONTROL ,TM_SRCONTROL disable" "No,Yes"
textline " "
bitfld.long 0x1c 21.--22. " SC_SATA ,Control for SATA slew-control" "0,1,2,3"
bitfld.long 0x1c 19.--20. " SC_PCIE ,Control for PCIe slew-control" "0,1,2,3"
textline " "
bitfld.long 0x1c 18. " DISABLE_PCIE_SC ,Disable PCIE SC" "No,Yes"
bitfld.long 0x1c 17. " DISABLE_SATA_SC ,Disable SATA SC" "No,Yes"
textline " "
bitfld.long 0x1c 14. " TXDCC_PWRDN ,TX clock duty-cycle correction bypass" "Disabled,Enabled"
bitfld.long 0x1c 4.--8. " TMTRIM ,Termination resistor calibration code for grounded resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x1c 3. " TRIMBYPASS ,Digital control of termination resistor bypass" "Disabled,Enabled"
bitfld.long 0x1c 1.--2. " RDTCT_VTMODE ,Receive detect test mode to program threshold" ".285V,0.3V,.27V,0.35V"
line.long 0x20 "SERDES_TXCFG3,SerDes TX Config 3 Status Register"
bitfld.long 0x20 24.--27. " RXLDO_CTRL[15:13] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 23. " RXLDO_CTRL[12] ,Force LDO UP signal high" "Not forced,Forced"
textline " "
bitfld.long 0x20 22. " RXLDO_CTRL[11] ,Low dropout mode" "Disabled,Enabled"
bitfld.long 0x20 21. " RXLDO_CTRL[10] ,Vref magnitude selection" "Disabled,Enabled"
textline " "
bitfld.long 0x20 20. " RXLDO_CTRL[9] ,Iref magnitude selection" "Disabled,Enabled"
bitfld.long 0x20 18.--19. " RXLDO_CTRL[8:7] ,Quiescent current programmability" "0,1,2,3"
textline " "
bitfld.long 0x20 17. " RXLDO_CTRL[6] ,Overshoot control block" "Disabled,Enabled"
bitfld.long 0x20 12.--16. " RXLDO_CTRL[5:0] ,Trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x20 11. " RXLDO_HITRAN_UNUSED ,RX LDO transient improvement" "Disabled,Enabled"
bitfld.long 0x20 7.--10. " TXLDO_CTRL[9:6] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x20 6. " TXLDO_CTRL[5] ,Force LDO UP signal high" "Not forced,Forced"
bitfld.long 0x20 5. " TXLDO_CTRL[4] ,Low dropout mode" "Disabled,Enabled"
textline " "
bitfld.long 0x20 4. " TXLDO_CTRL[3] ,Vref magnitude selection" "Disabled,Enabled"
bitfld.long 0x20 3. " TXLDO_CTRL[2] ,Iref magnitude selection" "Disabled,Enabled"
textline " "
bitfld.long 0x20 1.--2. " TXLDO_CTRL[1:0] ,Quiescent current programmability" "0,1,2,3"
bitfld.long 0x20 0. " TXLDO_DISABLE_OVERSHOOT ,TX LDO disable overshoot control" "No,Yes"
line.long 0x24 "SERDES_TXCFG4,SerDes TX Config 4 Status Register"
bitfld.long 0x24 4. " TM_BIASCTR ,TM_BIASCTR used in DCC" "Disabled,Enabled"
bitfld.long 0x24 1.--3. " TRIM_MODE ,TRIM_MODE[2:0]" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x24 0. " HYST_DISABLE ,HYST_DISABLE_Z and CALOUT_TX" "No,Yes"
else
group.long 0x390++0x1F
line.long 0x0 "SERDES_RXCFG0,SerDes RX Config 0 Register"
line.long 0x4 "SERDES_RXCFG1,SerDes RX Config 1 Register"
line.long 0x8 "SERDES_RXCFG2,SerDes RX Config 2 Register"
line.long 0xC "SERDES_RXCFG3,SerDes RX Config 3 Register"
line.long 0x10 "SERDES_TXCFG0,SerDes TX Config 0 Register"
line.long 0x14 "SERDES_TXCFG1,SerDes TX Config 1 Register"
line.long 0x18 "SERDES_TXCFG2,SerDes TX Config 2 Register"
line.long 0x1C "SERDES_TXCFG3,SerDes TX Config 3 Register"
endif
else
group.long 0x390++0x07
line.long 0x0 "SERDES_CFG0,SerDes Configuration for Lane 0"
bitfld.long 0x0 19.--20. " TX_LOOPBACK ,Enable TX loopback" "Disabled,Disabled,Disabled,Enabled"
bitfld.long 0x0 18. " TX_MSYNC ,Master mode for synchronization" "Disabled,Enabled"
textline " "
bitfld.long 0x0 17. " TX_CM ,Enable common mode adjustment" "Disabled,Enabled"
bitfld.long 0x0 16. " TX_INVPAIR ,Invert TX pair polarity" "Not inverted,Inverted"
textline " "
bitfld.long 0x0 14.--15. " RX_LOOPBACK ,Enable RX loopback" "Disabled,Disabled,Disabled,Enabled"
bitfld.long 0x0 13. " RX_ENOC ,Enable RX offset compensation" "Disabled,Enabled"
textline " "
bitfld.long 0x0 9.--12. " RX_EQ ,Enable RX adaptive equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 6.--8. " RX_CDR ,Enable RX clock data recovery" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x0 3.--5. " RX_LOS ,Enable RX loss of signal detection" "0,1,2,3,4,5,6,7"
bitfld.long 0x0 1.--2. " RX_ALIGN ,Enable RX symbol alignment" "0,1,2,3"
textline " "
bitfld.long 0x0 0. " RX_INVPAIR ,Invert RX pair polarity" "Not inverted,Inverted"
line.long 0x4 "SERDES_CFG1,SerDes Configuration for Lane 1"
bitfld.long 0x4 19.--20. " TX_LOOPBACK ,Enable TX loopback" "Disabled,Disabled,Disabled,Enabled"
bitfld.long 0x4 18. " TX_MSYNC ,Master mode for synchronization" "Disabled,Enabled"
textline " "
bitfld.long 0x4 17. " TX_CM ,Enable common mode adjustment" "Disabled,Enabled"
bitfld.long 0x4 16. " TX_INVPAIR ,Invert TX pair polarity" "Not inverted,Inverted"
textline " "
bitfld.long 0x4 14.--15. " RX_LOOPBACK ,Enable RX loopback" "Disabled,Disabled,Disabled,Enabled"
bitfld.long 0x4 13. " RX_ENOC ,Enable RX offset compensation" "Disabled,Enabled"
textline " "
bitfld.long 0x4 9.--12. " RX_EQ ,Enable RX adaptive equalization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x4 6.--8. " RX_CDR ,Enable RX clock data recovery" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x4 3.--5. " RX_LOS ,Enable RX loss of signal detection" "0,1,2,3,4,5,6,7"
bitfld.long 0x4 1.--2. " RX_ALIGN ,Enable RX symbol alignment" "0,1,2,3"
textline " "
bitfld.long 0x4 0. " RX_INVPAIR ,Invert RX pair polarity" "Not inverted,Inverted"
endif
width 11.
tree.end
tree.open "PRCM (Power Reset and Clock Management)"
base ad:0x48180000
width 21.
tree "PRM (Power Reset Manager)"
tree "PRM_DEVICE"
group.long 0xa0++0xb
line.long 0x00 "PRM_RSTCTRL,Software Global Cold and Warm Reset Control Register"
bitfld.long 0x00 1. " RST_GLOBAL_COLD_SW ,Software Global Cold Reset control" "No reset,Reset"
bitfld.long 0x00 0. " RST_GLOBAL_WARM_SW ,Software Global Warm Reset control" "No reset,Reset"
line.long 0x04 "PRM_RSTTIME,Reset Duration Control Register"
bitfld.long 0x04 8.--12. " RSTTIME2 ,(Power domain) reset duration 2 (number of RM.SYSCLK clock cycles)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x04 0.--7. 1. " RSTTIME1 ,(Global) reset duration 1 (number of SYS_CLK clock cycles)"
line.long 0x08 "PRM_RSTST,Global Reset Sources Register"
bitfld.long 0x08 9. " ICEPICK_RST ,IcePick Reset event" "No reset,Reset"
bitfld.long 0x08 5. " EXTERNAL_WARM_RST ,External Warm Reset event" "No reset,Reset"
bitfld.long 0x08 3. " MPU_WDT_RST ,Watchdog Timer Reset event" "No reset,Reset"
textline " "
bitfld.long 0x08 2. " MPU_SECURITY_VIOL_RST ,Security Violation Reset event" "No reset,Reset"
bitfld.long 0x08 1. " GLOBAL_WARM_SW_RST ,Software Global Warm Reset event" "No reset,Reset"
bitfld.long 0x08 0. " GLOBAL_COLD_RST ,Power-on Reset (POR) event" "No reset,Reset"
tree.end
tree "OCP_SOCKET_PRM"
rgroup.long 0x200++0x3
line.long 0x00 "REVISION_PRM,PRM IP Revision Code Register"
hexmask.long.byte 0x00 0.--7. 1. " REV ,IP revision"
tree.end
tree "PRM_ACTIVE"
group.long 0xa00++0x3
line.long 0x00 "PM_ACTIVE_PWRSTCTRL,ACTIVE Power State Control Register"
bitfld.long 0x00 16.--17. " ACTIVE_MEM_ONSTATE ,Active Domain memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xa04++0x3
line.long 0x00 "PM_ACTIVE_PWRSTST,ACTIVE Power State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
sif (cpuis("C6A816*DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0xa10++0x7
line.long 0x00 "RM_ACTIVE_RSTCTRL,ACTIVE Domain Resets Control Register"
bitfld.long 0x00 1. " GEM_SW_RST ,ACTIVE Domain C674x DSP warm reset control" "No reset,Reset"
bitfld.long 0x00 0. " GEM_LRST ,ACTIVE Domain C674x DSP local reset control" "No reset,Reset"
line.long 0x04 "RM_ACTIVE_RSTST,ACTIVE Domain Reset Sources Register"
eventfld.long 0x04 1. " GEM_GRST ,C674x DSP warm reset" "No reset,Reset"
eventfld.long 0x04 0. " GEM_LRST ,C674x DSP local SW reset" "No reset,Reset"
endif
tree.end
tree "PRM_DEFAULT"
group.long 0xb00++0x3
line.long 0x00 "PM_DEFAULT_PWRSTCTRL,DEFAULT Power State Control Register"
bitfld.long 0x00 16.--17. " DEFAULT_MEM_ONSTATE ,DEFAULT Domain memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xb04++0x3
line.long 0x00 "PM_DEFAULT_PWRSTST,DEFAULT Power State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xb10++0x7
line.long 0x00 "RM_DEFAULT_RSTCTRL,DEFAULT Domain Resets Control Register"
bitfld.long 0x00 7. " PCI_LRST ,ACTIVE domain PCI Local reset control" "No reset,Reset"
bitfld.long 0x00 6. " USB2_LRST ,USB2 local reset control" "No reset,Reset"
bitfld.long 0x00 5. " USB1_LRST ,USB1 local reset control" "No reset,Reset"
textline " "
bitfld.long 0x00 4. " DUCATI_RST3 ,Ducati logic and MMU reset control" "No reset,Reset"
bitfld.long 0x00 3. " DUCATI_M3_RST2 ,Ducati Second M3 reset control" "No reset,Reset"
bitfld.long 0x00 2. " DUCATI_M3_RST1 ,Ducati First M3 reset control" "No reset,Reset"
line.long 0x04 "RM_DEFAULT_RSTST,DEFAULT Domain Reset Sources Register"
eventfld.long 0x04 7. " PCI_LRST ,PCI Local software reset control" "No reset,Reset"
eventfld.long 0x04 6. " USB2_LRST ,USB2 local software reset control" "No reset,Reset"
eventfld.long 0x04 5. " USB1_LRST ,USB1 local software reset control" "No reset,Reset"
textline " "
eventfld.long 0x04 4. " DUCATI_RST3 ,Ducati logic and MMU software reset control" "No reset,Reset"
eventfld.long 0x04 3. " DUCATI_M3_RST2 ,Ducati Second M3 software reset control" "No reset,Reset"
eventfld.long 0x04 2. " DUCATI_M3_RST1 ,Ducati First M3 software reset control" "No reset,Reset"
tree.end
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
tree "PRM_IVAHD0"
group.long 0xC00++0x3
line.long 0x00 "PM_IVAHD0_PWRSTCTRL,HDVICP2-0 Power State Control Register"
bitfld.long 0x00 16.--17. " IVA0_MEM_ONSTATE ,HDVICP2-0 memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xC04++0x3
line.long 0x00 "PM_IVAHD0_PWRSTST,HDVICP2-0 Power State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xC10++0x7
line.long 0x00 "RM_IVAHD0_RSTCTRL,HDVICP2-0 Domain Resets Control Register"
bitfld.long 0x00 2. " IVA0_RST3 ,HDVICP2-0 logic and SL2 reset control" "No reset,Reset"
bitfld.long 0x00 1. " IVA0_RST2 ,HDVICP2-0 sequencer2 reset control" "No reset,Reset"
bitfld.long 0x00 0. " IVA0_RST1 ,HDVICP2-0 sequencer1 reset control" "No reset,Reset"
line.long 0x04 "RM_IVAHD0_RSTST,HDVICP2-0 Domain Reset Sources Register"
eventfld.long 0x04 2. " IVA0_RST3 ,HDVICP2-0 logic and SL2 reset control" "No reset,Reset"
eventfld.long 0x04 1. " IVA0_RST2 ,HDVICP2-0 sequencer2 reset control" "No reset,Reset"
eventfld.long 0x04 0. " IVA0_RST1 ,HDVICP2-0 sequencer1 reset control" "No reset,Reset"
tree.end
tree "PRM_IVAHD1"
group.long 0xD00++0x3
line.long 0x00 "PM_IVAHD1_PWRSTCTRL,HDVICP2-1 Power State Control Register"
bitfld.long 0x00 16.--17. " IVA1_MEM_ONSTATE ,HDVICP2-1 memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xD04++0x3
line.long 0x00 "PM_IVAHD1_PWRSTST,HDVICP2-1 Power State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xD10++0x7
line.long 0x00 "RM_IVAHD1_RSTCTRL,HDVICP2-1 Domain Resets Control Register"
bitfld.long 0x00 2. " IVA1_RST3 ,HDVICP2-1 logic and SL2 reset control" "No reset,Reset"
bitfld.long 0x00 1. " IVA1_RST2 ,HDVICP2-1 sequencer2 reset control" "No reset,Reset"
bitfld.long 0x00 0. " IVA1_RST1 ,HDVICP2-1 sequencer1 reset control" "No reset,Reset"
line.long 0x04 "RM_IVAHD1_RSTST,HDVICP2-1 Domain Reset Sources Register"
eventfld.long 0x04 2. " IVA1_RST3 ,HDVICP2-1 logic and SL2 reset control" "No reset,Reset"
eventfld.long 0x04 1. " IVA1_RST2 ,HDVICP2-1 sequencer2 reset control" "No reset,Reset"
eventfld.long 0x04 0. " IVA1_RST1 ,HDVICP2-1 sequencer1 reset control" "No reset,Reset"
tree.end
tree "PRM_IVAHD2"
group.long 0xE00++0x3
line.long 0x00 "PM_IVAHD2_PWRSTCTRL,HDVICP2-2 Power State Control Register"
bitfld.long 0x00 16.--17. " IVA2_MEM_ONSTATE ,HDVICP2-2 memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xE04++0x3
line.long 0x00 "PM_IVAHD2_PWRSTST,HDVICP2-2 Power State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xE10++0x7
line.long 0x00 "RM_IVAHD2_RSTCTRL,HDVICP2-2 Domain Resets Control Register"
bitfld.long 0x00 2. " IVA2_RST3 ,HDVICP2-2 logic and SL2 reset control" "No reset,Reset"
bitfld.long 0x00 1. " IVA2_RST2 ,HDVICP2-2 sequencer2 reset control" "No reset,Reset"
bitfld.long 0x00 0. " IVA2_RST1 ,HDVICP2-2 sequencer1 reset control" "No reset,Reset"
line.long 0x04 "RM_IVAHD2_RSTST,HDVICP2-2 Domain Reset Sources Register"
eventfld.long 0x04 2. " IVA2_RST3 ,HDVICP2-2 logic and SL2 reset control" "No reset,Reset"
eventfld.long 0x04 1. " IVA2_RST2 ,HDVICP2-2 sequencer2 reset control" "No reset,Reset"
eventfld.long 0x04 0. " IVA2_RST1 ,HDVICP2-2 sequencer1 reset control" "No reset,Reset"
tree.end
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
tree "PRM_HDVICP"
group.long 0xc00++0x3
line.long 0x00 "PM_HDVICP_PWRSTCTRL,HDVICP Power State Control Register"
rbitfld.long 0x00 16.--17. " HDVICP_MEM_ONSTATE ,HDVICP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xc04++0x3
line.long 0x00 "PM_HDVICP_PWRSTST,HDVICP Power Domain State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 4.--5. " HDVICP_MEM_STATEST ,HDVICP memory state status" "OFF,Reserved,Reserved,ON"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
textline " "
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xc10++0x7
line.long 0x00 "RM_HDVICP_RSTCTRL,HDVICP Domain Resets Control Register"
bitfld.long 0x00 2. " HDVICP_RST3 ,HDVICP logic and SL2 reset control" "No reset,Reset"
bitfld.long 0x00 1. " HDVICP_RST2 ,HDVICP sequencer2 reset control" "No reset,Reset"
bitfld.long 0x00 0. " HDVICP_RST1 ,HDVICP sequencer1 reset control" "No reset,Reset"
line.long 0x04 "RM_HDVICP_RSTST,HDVICP Domain Reset Sources Register"
bitfld.long 0x04 6. " ICECRUSHER_SEQ2_RST2 ,Sequencer2 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
bitfld.long 0x04 5. " ICECRUSHER_SEQ1_RST1 ,Sequencer1 CPU reset due to ICECRUSHER1 reset" "No reset,Reset"
bitfld.long 0x04 4. " EMULATION_SEQ2_RST2 ,Sequencer2 CPU reset due to emulation reset" "No reset,Reset"
textline " "
bitfld.long 0x04 3. " EMULATION_SEQ1_RST1 ,Sequencer1 CPU reset due to emulation reset" "No reset,Reset"
bitfld.long 0x04 2. " HDVICP_RST3 ,HDVICP logic and SL2 SW reset" "No reset,Reset"
bitfld.long 0x04 1. " HDVICP_RST2 ,HDVICP Sequencer2 CPU SW reset" "No reset,Reset"
textline " "
bitfld.long 0x04 0. " HDVICP_RST1 ,HDVICP Sequencer1 CPU SW reset" "No reset,Reset"
tree.end
tree "PRM_ISP"
group.long 0xd00++0x3
line.long 0x00 "PM_ISP_PWRSTCTRL,ISP Power State Control Register"
rbitfld.long 0x00 16.--17. " ISP_MEM_ONSTATE ,ISP memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xd04++0x3
line.long 0x00 "PM_ISP_PWRSTST,ISP Power Domain State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 4.--5. " ISP_MEM_STATEST ,ISP memory state status" "OFF,Reserved,Reserved,ON"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
textline " "
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xd10++0x7
line.long 0x00 "RM_ISP_RSTCTRL,ISP Domain Resets Control Register"
bitfld.long 0x00 2. " ISP_RST ,ISP logic reset control" "No reset,Reset"
line.long 0x04 "RM_ISP_RSTST,ISP Domain Reset Sources Register"
bitfld.long 0x04 2. " ISP_RST ,ISP logic and FDIF SW reset" "No reset,Reset"
tree.end
tree "PRM_DSS"
group.long 0xe00++0x3
line.long 0x00 "PM_DSS_PWRSTCTRL,DSS Power State Control Register"
rbitfld.long 0x00 16.--17. " DSS_MEM_ONSTATE ,DSS memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
bitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request (after a sleep transition)" "Not requested,Requested"
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
rgroup.long 0xe04++0x3
line.long 0x00 "PM_DSS_PWRSTST,DSS Power Domain State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
bitfld.long 0x00 4.--5. " DSS_MEM_STATEST ,DSS memory state status" "OFF,Reserved,Reserved,ON"
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
textline " "
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xe10++0x7
line.long 0x00 "RM_DSS_RSTCTRL,DSS Domain Resets Control Register"
bitfld.long 0x00 2. " DSS_RST ,DSS and HDMI reset control" "No reset,Reset"
line.long 0x04 "RM_DSS_RSTST,DSS Domain Reset Sources Register"
bitfld.long 0x04 2. " DSS_RST ,DSS logic and HDMI SW reset" "No reset,Reset"
tree.end
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="C6A8168DSP"||cpu()=="DM8166"||cpu()=="DM8168"||cpu()=="DM8148DSP"||cpu()=="DM8166DSP"||cpu()=="DM8168DSP")
tree "PRM_SGX"
group.long 0xf00++0x7
line.long 0x00 "PM_SGX_PWRSTCTRL,SGX Power State Control Register"
rbitfld.long 0x00 16.--17. " SGX_MEM_ONSTATE ,SGX memory state when domain is ON" "Reserved,Reserved,Reserved,ON"
textline " "
sif (cpu()=="DM8148DSP")
rbitfld.long 0x00 4. " LOWPOWERSTATECHANGE ,Power state change request" "Not requested,Requested"
textline " "
endif
bitfld.long 0x00 0.--1. " POWERSTATE ,Power state control" "OFF,Reserved,Reserved,ON"
line.long 0x04 "RM_SGX_RSTCTRL,SGX Domain Resets Control Register"
bitfld.long 0x04 0. " SGX_RST ,SGX local reset control" "No reset,Reset"
rgroup.long 0xf10++0x3
line.long 0x00 "PM_SGX_PWRSTST,SGX Power Domain State Status Register"
bitfld.long 0x00 20. " INTRANSITION ,Domain transition status" "No transition,In progress"
textline " "
sif (cpu()=="DM8148DSP")
bitfld.long 0x00 4.--5. " SGX_MEM_STATEST ,SGX memory state status" "OFF,Reserved,Reserved,ON"
textline " "
endif
bitfld.long 0x00 2. " LOGICSTATEST ,Logic state status" "OFF,ON"
bitfld.long 0x00 0.--1. " POWERSTATEST ,Current Power State Status" "OFF,Reserved,Reserved,ON"
group.long 0xf14++0x3
line.long 0x00 "RM_SGX_RSTST,SGX Domain Reset Sources Register"
bitfld.long 0x00 0. " SGX_RST ,SGX Domain Logic Reset" "No reset,Reset"
tree.end
endif
tree "RM_ALWON"
group.long 0x1814++0x03
line.long 0x00 "RM_ALWON_RSTST,ALWAYS ON Domain Reset Sources Register"
bitfld.long 0x00 6. " ICECRUSHER_MPU_RST ,MPU Processor reset due to ICECRUSHER1 reset" "No reset,Reset"
bitfld.long 0x00 5. " EMULATION_MPU_RST ,MPU Processor reset due to emulation reset" "No reset,Reset"
tree.end
tree.end
tree "CM (Clock Manager)"
tree "CM_DEVICE"
width 16.
group.long 0x100++0x3
line.long 0x00 "CM_CLKOUT_CTRL,SYS_CLKOUT Output Control Register"
bitfld.long 0x00 7. " CLKOUT2EN ,External clock (SYS_CLKOUT2) activity" "Disabled,Enabled"
textline " "
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
bitfld.long 0x00 3.--5. " CLKOUTDIV ,Clock divison factor of the CLKOUT Second Pin CLKOUT2" "/1,/2,/3,/4,/5,/6,/7,/8"
bitfld.long 0x00 0.--1. " CLKOUTSOURCE ,External output clock source" "MAIN_PLL_CLK,DPLL_DSP_CLK,VIDEO_PLL_CLK,AUDIO_PLL_CLK"
else
bitfld.long 0x00 3.--5. " CLKOUT2DIV ,External clock division factor" "/1,/2,/4,/8,/16,?..."
bitfld.long 0x00 0.--2. " CLKOUT2SOURCE ,External clock source output select" "MAIN_PLL_CLK5,DDR_PLL_CLK1,VIDEO_PLL_CLK1,AUDIO_PLL_CLK1,?..."
endif
tree.end
tree "CM_DPLL"
width 27.
sif (cpuis("C6A816*")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x300++0x3
line.long 0x00 "CM_SYSCLK1_CLKSEL,SYSCLK1 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK1 select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x304++0x3
line.long 0x00 "CM_SYSCLK2_CLKSEL,SYSCLK2 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK2 select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x308++0x3
line.long 0x00 "CM_SYSCLK3_CLKSEL,SYSCLK4 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK2 select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x30c++0xf
line.long 0x00 "CM_SYSCLK4_CLKSEL,SYSCLK4 Clock Select Register"
bitfld.long 0x00 0. " CLKSEL ,Divider value for SYSCLK4 select" "/1,/2"
line.long 0x04 "CM_SYSCLK5_CLKSEL,SYSCLK5 Clock Select Register"
bitfld.long 0x04 0. " CLKSEL ,Divider value for SYSCLK5 select" "/1,/2"
line.long 0x08 "CM_SYSCLK6_CLKSEL,SYSCLK6 Clock Select Register"
bitfld.long 0x08 0. " CLKSEL ,Divider value for SYSCLK6 select" "/2,/4"
line.long 0x0c "CM_SYSCLK7_CLKSEL,SYSCLK7 Clock Select Register"
bitfld.long 0x0c 0.--1. " CLKSEL ,Divider value for SYSCLK7 select" "/5,/6,/8,/16"
endif
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x324++0x3
line.long 0x00 "CM_SYSCLK10_CLKSEL,SYSCLK10 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK10 select" "/1,/2,/3,/4,/5,/6,/7,/8"
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x32C++0x3
line.long 0x00 "CM_SYSCLK11_CLKSEL,SYSCLK11 Clock Select Register"
bitfld.long 0x00 0. " CLKSEL ,Divider value for SYSCLK11 select" "/1,/2"
endif
else
group.long 0x324++0x7
line.long 0x00 "CM_SYSCLK10_CLKSEL,SYSCLK10 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK10 select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x04 "CM_SYSCLK11_CLKSEL,SYSCLK11 Clock Select Register"
bitfld.long 0x04 0. " CLKSEL ,Divider value for SYSCLK11 select" "/1,/2"
endif
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x334++0x7
line.long 0x00 "CM_SYSCLK13_CLKSEL,SYSCLK13 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK13 select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x04 "CM_SYSCLK15_CLKSEL,SYSCLK15 Clock Select Register"
bitfld.long 0x04 0.--2. " CLKSEL ,Divider value for SYSCLK15 select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
group.long 0x340++0x1b
line.long 0x00 "CM_VPB3_CLKSEL,PLL_VIDEO2 B3 Clock Select Register"
bitfld.long 0x00 0.--1. " CLKSEL ,Divider value B3 for PLL select" "/1,/2,/22,?..."
line.long 0x04 "CM_VPC1_CLKSEL,PLL_VIDEO1 C1 Clock Select Register"
bitfld.long 0x04 0.--1. " CLKSEL ,Divider value C1 for PLL select" "/1,/2,/22,?..."
line.long 0x08 "CM_VPD1_CLKSEL,PLL_VIDEO0 D1 Clock Select Register"
bitfld.long 0x08 0.--2. " CLKSEL ,Divider value D1 for PLL select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x0c "CM_SYSCLK19_CLKSEL,SYSCLK19 Clock Select Register"
bitfld.long 0x0c 0.--2. " CLKSEL ,Divider value for SYSCLK19 select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x10 "CM_SYSCLK20_CLKSEL,SYSCLK20 Clock Select Register"
bitfld.long 0x10 0.--2. " CLKSEL ,Divider value for SYSCLK20 select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x14 "CM_SYSCLK21_CLKSEL,SYSCLK21 Clock Select Register"
bitfld.long 0x14 0.--2. " CLKSEL ,Divider value for SYSCLK21 select" "/1,/2,/3,/4,/5,/6,/7,/8"
line.long 0x18 "CM_SYSCLK22_CLKSEL,SYSCLK22 Clock Select Register"
bitfld.long 0x18 0.--2. " CLKSEL ,Divider value for SYSCLK22 select" "/1,/2,/3,/4,/5,/6,/7,/8"
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
group.long 0x35c++0x03
line.long 0x00 "CM_APA_CLKSEL,Audio PLL A Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value Audio PLL A divider select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
group.long 0x370++0x1b
line.long 0x00 "CM_SYSCLK14_CLKSEL,SYSCLK14 Mux Select Line Register"
bitfld.long 0x00 0.--1. " CLKSEL ,Mux select line for SYSCLK14 select" "B3 div,CLKIN,C1 div,?..."
line.long 0x04 "CM_SYSCLK16_CLKSEL,SYSCLK16 Mux Select Line Register"
bitfld.long 0x04 0. " CLKSEL ,Mux select line for SYSCLK16 select" "D1 div,B3 div"
line.long 0x08 "CM_SYSCLK18_CLKSEL,SYSCLK18 Mux Select Line Register"
bitfld.long 0x08 0. " CLKSEL ,Mux select line for SYSCLK18 select" "32KHz clk,Audio PLL 32KHz clk"
line.long 0x0c "CM_AUDIOCLK_MCASP0_CLKSEL,McASP0 Audio Clock Mux Select Line Register"
bitfld.long 0x0c 0.--1. " CLKSEL ,Mux select line for McASP0 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
line.long 0x10 "CM_AUDIOCLK_MCASP1_CLKSEL,McASP1 Audio Clock Mux Select Line Register"
bitfld.long 0x10 0.--1. " CLKSEL ,Mux select line for McASP1 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
line.long 0x14 "CM_AUDIOCLK_MCASP2_CLKSEL,McASP2 Audio Clock Mux Select Line Register"
bitfld.long 0x14 0.--1. " CLKSEL ,Mux select line for McASP2 audio clock select" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
line.long 0x18 "CM_AUDIOCLK_MCBSP_CLKSEL,McBSP Audio Clock Mux Select Line Register"
bitfld.long 0x18 0.--1. " CLKSEL ,Mux select line for McBSP audio clock" "SYSCLK20,SYSCLK21,SYSCLK22,?..."
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x390++0x17
line.long 0x0 "CM_TIMER1_CLKSEL,TIMER1 Mux Select Line Register"
bitfld.long 0x0 0.--1. " CLKSEL ,Mux select line for TIMER1 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
line.long 0x4 "CM_TIMER2_CLKSEL,TIMER2 Mux Select Line Register"
bitfld.long 0x4 0.--1. " CLKSEL ,Mux select line for TIMER2 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
line.long 0x8 "CM_TIMER3_CLKSEL,TIMER3 Mux Select Line Register"
bitfld.long 0x8 0.--1. " CLKSEL ,Mux select line for TIMER3 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
line.long 0xC "CM_TIMER4_CLKSEL,TIMER4 Mux Select Line Register"
bitfld.long 0xC 0.--1. " CLKSEL ,Mux select line for TIMER4 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
line.long 0x10 "CM_TIMER5_CLKSEL,TIMER5 Mux Select Line Register"
bitfld.long 0x10 0.--1. " CLKSEL ,Mux select line for TIMER5 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
line.long 0x14 "CM_TIMER6_CLKSEL,TIMER6 Mux Select Line Register"
bitfld.long 0x14 0.--1. " CLKSEL ,Mux select line for TIMER6 clock" "TCLKIN,Ext 32KHz clk,CLKIN,?..."
endif
group.long 0x3b0++0x3
line.long 0x00 "CM_SYSCLK23_CLKSEL,SYSCLK23 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK23 select" "/1,/2,/3,/4,/5,/6,/7,/8"
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x3b4++0x3
line.long 0x00 "CM_SYSCLK24_CLKSEL,SYSCLK24 Clock Select Register"
bitfld.long 0x00 0.--2. " CLKSEL ,Divider value for SYSCLK24 select" "/1,/2,/3,/4,/5,/6,/7,/8"
endif
tree.end
tree "CM_ACTIVE"
width 25.
sif (cpuis("C6A816*DSP")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x400++0x3
line.long 0x00 "CM_GEM_CLKSTCTRL,DSP Clock Domain State Transitions Control Register"
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
bitfld.long 0x00 10. " CLKACTIVITY_GEM_TRCCLK ,State of GEM_TRCCLK clock" "Gated,Active"
bitfld.long 0x00 9. " CLKACTIVITY_GEM_VBUSPCLK ,State of GEM_VBUSP clock" "Gated,Active"
textline " "
bitfld.long 0x00 8. " CLKACTIVITY_GEM_GCLK ,State of GEM_GICLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,C674x DSP clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
else
bitfld.long 0x00 0.--1. " CLKTRCTRL ,Controls the clock state transition of the GEM clock domain" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
endif
endif
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x404++0x3
line.long 0x00 "CM_HDDSS_CLKSTCTRL,HD-DSS Clock Domain State Transitions Control Register"
bitfld.long 0x00 15. " CLKACTIVITY_HD_DSS_L3_EN_GCLK ,State of L3_EN_GCLK clock" "Gated,Active"
bitfld.long 0x00 14. " CLKACTIVITY_PRC_GCLK ,State of PRC_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 13. " CLKACTIVITY_HD_DSS_L4_GCLK ,State of HD_DSS_L4_GCLK clock" "Gated,Active"
bitfld.long 0x00 12. " CLKACTIVITY_HD_DSS_L4_GCLK ,State of HD_DSS_L3_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 10. " CLKACTIVITY_SD_GCLK ,State of SD_GCLK clock" "Gated,Active"
bitfld.long 0x00 9. " CLKACTIVITY_HD_VENC_A_GCLK ,State of HD_VENC_A_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 8. " CLKACTIVITY_HD_VENC_D_GCLK ,State of HD_VENC_D_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HD-DSS clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
width 25.
sif (cpuis("C6A816*DSP")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x420++0x3
line.long 0x00 "CM_ACTIVE_GEM_CLKCTRL,DSP Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x424++0x3
line.long 0x00 "CM_ACTIVE_HDDSS_CLKCTRL,HD_DSS Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
tree.end
tree "CM_DEFAULT"
width 29.
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x504++0x7
line.long 0x00 "CM_DEFAULT_L3_MED_CLKSTCTRL,L3_MED Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_L3_MED_GCLK ,State of the L3_SLOW_GCL clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_MED clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
line.long 0x04 "CM_DEFAULT_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
bitfld.long 0x04 9. " CLKACTIVITY_DDR_GCLK ,State of the DDR_GCLK clock" "Gated,Active"
bitfld.long 0x04 8. " CLKACTIVITY_L3_FAST_GCLK ,State of the L3_FAST_GCLK clock" "Gated,Active"
bitfld.long 0x04 0.--1. " CLKTRCTRL ,L3_FAST clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
group.long 0x510++0x3
line.long 0x00 "CM_DEFAULT_PCI_CLKSTCTRL,PCI Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_PCI_GCLK ,State of the PCI_GCLK clock" "Gated,Active"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 0.--1. " CLKTRCTRL ,PCI clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
bitfld.long 0x00 0.--1. " CLKTRCTRL ,PCI clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x514++0x3
line.long 0x00 "CM_DEFAULT_L3_SLOW_CLKSTCTRL,L3_SLOW Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_USB_GCLK ,State of the L3_SLOW_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
group.long 0x518++0x3
line.long 0x00 "CM_DEFAULT_DUCATI_CLKSTCTRL,DUCATI Clock Domain State Transitions Control Register"
bitfld.long 0x00 9. " CLKACTIVITY_DUCATI_GCLKIN200TR ,State of the CLKIN200TR clock" "Gated,Active"
bitfld.long 0x00 8. " CLKACTIVITY_DUCATI_GCLKINTR ,State of the CLKINTR clock" "Gated,Active"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DUCATI clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DUCATI clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
width 29.
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x520++0x7
line.long 0x00 "CM_DEFAULT_EMIF_0_CLKCTRL,EMIF_0 Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_DEFAULT_EMIF_1_CLKCTRL,EMIF_1 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
group.long 0x528++0x03
line.long 0x00 "CM_DEFAULT_DMM_CLKCTRL,DMM Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif ((cpu()!="DM8147DSP")&&(cpu()!="DM8148DSP"))
group.long 0x52c++0x3
line.long 0x00 "CM_DEFAULT_FW_CLKCTRL,EMIF FW Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
group.long 0x558++0x3
line.long 0x00 "CM_DEFAULT_USB_CLKCTRL,USB Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x560++0x3
line.long 0x00 "CM_DEFAULT_SATA_CLKCTRL,SATA Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x574++0x7
line.long 0x00 "CM_DEFAULT_DUCATI_CLKCTRL,DUCATI Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_DEFAULT_PCI_CLKCTRL,PCI Clocks Control Register"
rbitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
tree "CM_IVAHD0"
group.long 0x600++0x03
line.long 0x00 "CM_IVAHD0_CLKSTCTRL,IVAHD0 Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_IVAHD0_GCLK ,State of the IVAHD0_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP2-0 clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
group.long 0x620++0x07
line.long 0x00 "CM_IVAHD0_IVAHD_CLKCTRL,IVAHD0 Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_IVAHD0_SL2_CLKCTRL,IVAHD0 SL2 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
tree "CM_IVAHD1"
group.long 0x700++0x03
line.long 0x00 "CM_IVAHD1_CLKSTCTRL,IVAHD1 Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_IVAHD1_GCLK ,State of the HDVICP2-1_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP2-1 clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
group.long 0x720++0x07
line.long 0x00 "CM_IVAHD1_IVAHD_CLKCTRL,IVAHD1 Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_IVAHD1_SL2_CLKCTRL,IVAHD1 SL2 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
tree "CM_IVAHD2"
group.long 0x800++0x03
line.long 0x00 "CM_IVAHD2_CLKSTCTRL,IVAHD2 Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_IVAHD2_GCLK ,State of the IVAHD2_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP2-2 clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
group.long 0x820++0x07
line.long 0x00 "CM_IVAHD2_IVAHD_CLKCTRL,IVAHD2 Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_IVAHD2_SL2_CLKCTRL,IVAHD2 SL2 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
tree "CM_HDVICP"
width 24.
group.long 0x600++0x3
line.long 0x00 "CM_HDVICP_CLKSTCTRL,HDVICP Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_HDVICP_GCLK ,State of the HDVICP_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,HDVICP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
width 24.
group.long 0x620++0x7
line.long 0x00 "CM_HDVICP_CLKCTRL,HDVICP Clocks Control Register"
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_HDVICP_SL2_CLKCTRL,SL2 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
tree "CM_ISP"
width 24.
group.long 0x700++0x3
line.long 0x00 "CM_ISP_CLKSTCTRL,ISP Clock Domain State Transitions Control Register"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,ISP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
group.long 0x720++0x7
line.long 0x00 "CM_ISP_ISP_CLKCTRL,ISP Clocks Control Register"
bitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_ISP_FDIF_CLKCTRL,FDIF Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
tree "CM_DSS"
width 21.
group.long 0x800++0x3
line.long 0x00 "CM_DSS_CLKSTCTRL,DSS Clock Domain State Transitions Control Register"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,DSS clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
group.long 0x820++0x7
line.long 0x00 "CM_DSS_DSS_CLKCTRL,DSS Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_DSS_HDMI_CLKCTRL,HDMI Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
endif
sif (cpu()=="AM3894"||cpu()=="C6A8168"||cpu()=="C6A8168DSP"||(cpu()=="DM8166")||(cpu()=="DM8168")||cpu()=="DM8148DSP"||(cpu()=="DM8166DSP")||(cpu()=="DM8168DSP"))
tree "CM_SGX"
width 24.
group.long 0x900++0x3
line.long 0x00 "CM_SGX_CLKSTCTRL,SGX Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_SGX_GCLK ,State of the SGX_GCLK clock" "Gated,Active"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 0.--1. " CLKTRCTRL ,SGX clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
bitfld.long 0x00 0.--1. " CLKTRCTRL ,SGX clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
width 24.
group.long 0x920++0x3
line.long 0x00 "CM_SGX_CLKCTRL,SGX Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
tree.end
endif
tree "CM_ALWON"
width 29.
group.long 0x1400++0x1b
line.long 0x00 "CM_ALWON_L3_SLOW_CLKSTCTRL,L3_SLOW Clock Domain State Transitions Control Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 26. " CLKACTIVITY_SDIO_CLKADPI_GCLK ,State of the SDIO_ADPI clock" "Gated,Active"
textline " "
endif
bitfld.long 0x00 26. " CLKACTIVITY_TIMER7_GCLK ,State of the TIMER7 CLKTIMER clock" "Gated,Active"
bitfld.long 0x00 25. " CLKACTIVITY_TIMER6_GCLK ,State of the TIMER6 CLKTIMER clock" "Gated,Active"
textline " "
bitfld.long 0x00 24. " CLKACTIVITY_TIMER5_GCLK ,State of the TIMER5 CLKTIMER clock" "Gated,Active"
bitfld.long 0x00 23. " CLKACTIVITY_TIMER4_GCLK ,State of the TIMER4 CLKTIMER clock" "Gated,Active"
textline " "
bitfld.long 0x00 22. " CLKACTIVITY_TIMER3_GCLK ,State of the TIMER3 CLKTIMER clock" "Gated,Active"
bitfld.long 0x00 21. " CLKACTIVITY_TIMER2_GCLK ,State of the TIMER2 CLKTIMER clock" "Gated,Active"
textline " "
bitfld.long 0x00 20. " CLKACTIVITY_TIMER1_GCLK ,State of the TIMER1 CLKTIMER clock" "Gated,Active"
bitfld.long 0x00 17. " CLKACTIVITY_SPI_GSYSCLK ,State of the SPI_GSYSCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 16. " CLKACTIVITY_I2C_GSYSCLK ,State of the I2C_GSYSCLK clock" "Gated,Active"
bitfld.long 0x00 15. " CLKACTIVITY_GPIO_1_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 14. " CLKACTIVITY_GPIO_0_GDBCLK ,State of the GPIO_GDBCLK clock" "Gated,Active"
bitfld.long 0x00 13. " CLKACTIVITY_UART_GFCLK ,State of the UART_GFCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 12. " CLKACTIVITY_MCBSP_AUX_GCLK ,State of the MCBSP_AUX_GCLK clock" "Gated,Active"
bitfld.long 0x00 11. " CLKACTIVITY_MCASP2_AUX_GCLK ,State of the MCASP2_AUX_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 10. " CLKACTIVITY_MCASP1_AUX_GCLK ,State of the MCASP1_AUX_GCLK clock" "Gated,Active"
bitfld.long 0x00 9. " CLKACTIVITY_MCASP0_AUX_GCLK ,State of the MCASP0_AUX_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x00 8. " CLKACTIVITY_L3_SLOW_GCLK ,State of the L3_SLOW_GCLK clock" "Gated,Active"
textline " "
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3_SLOW clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
line.long 0x04 "CM_ETHERNET_CLKSTCTRL,ETHERNET Clock Domain State Transitions Control Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x04 0.--1. " CLKTRCTRL ,ETHERNET clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
bitfld.long 0x04 9. " CLKACTIVITY_RFT_GCLK ,State of the CPGMAC_RFT_GCLK clock" "Gated,Active"
bitfld.long 0x04 8. " CLKACTIVITY_ETHERNET_GCLK ,State of the ETHERNET_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x04 0.--1. " CLKTRCTRL ,ETHERNET clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
line.long 0x08 "CM_ALWON_L3_MED_CLKSTCTRL,L3 Medium Clock Domain State Transitions Control Register"
bitfld.long 0x08 0.--1. " CLKTRCTRL ,L3 Medium clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
line.long 0x0c "CM_MMU_CLKSTCTRL,MMU Clock Domain State Transitions Control Register"
bitfld.long 0x0c 8. " CLKACTIVITY_MMU_GCLK ,State of the MMU_GICLK clock" "Gated,Active"
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,MMU clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
line.long 0x10 "CM_MMUCFG_CLKSTCTRL,MMUCFG Clock Domain State Transitions Control Register"
bitfld.long 0x10 8. " CLKACTIVITY_MMUCFG_GCLK ,State of the MMUCFG_GICLK clock" "Gated,Active"
bitfld.long 0x10 0.--1. " CLKTRCTRL ,MMU CFG clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
line.long 0x14 "CM_ALWON_OCMC_0_CLKSTCTRL,OCMC 0 Clock Domain State Transitions Control Register"
bitfld.long 0x14 8. " CLKACTIVITY_OCMC_0_GCLK ,State of the OCMC_0_GICLK clock" "Gated,Active"
bitfld.long 0x14 0.--1. " CLKTRCTRL ,OCMC 0 clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
line.long 0x18 "CM_ALWON_VCP_CLKSTCTRL,VCP Clock Domain State Transitions Control Register"
bitfld.long 0x18 8. " CLKACTIVITY_VCP_GCLK ,State of the VCP_GCLK clock" "Gated,Active"
bitfld.long 0x18 0.--1. " CLKTRCTRL ,VCP clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
line.long 0x08 "CM_ALWON_L3_MED_CLKSTCTRL,L3 Medium Clock Domain State Transitions Control Register"
bitfld.long 0x08 0.--1. " CLKTRCTRL ,L3 Medium clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
line.long 0x0c "CM_MMU_CLKSTCTRL,MMU Clock Domain State Transitions Control Register"
bitfld.long 0x0c 8. " CLKACTIVITY_MMU_GCLK ,State of the MMU_GICLK clock" "Gated,Active"
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,MMU clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
line.long 0x10 "CM_MMUCFG_CLKSTCTRL,MMUCFG Clock Domain State Transitions Control Register"
bitfld.long 0x10 8. " CLKACTIVITY_MMUCFG_GCLK ,State of the MMUCFG_GICLK clock" "Gated,Active"
bitfld.long 0x10 0.--1. " CLKTRCTRL ,MMU CFG clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
line.long 0x14 "CM_ALWON_OCMC_0_CLKSTCTRL,OCMC 0 Clock Domain State Transitions Control Register"
bitfld.long 0x14 8. " CLKACTIVITY_OCMC_0_GCLK ,State of the OCMC_0_GICLK clock" "Gated,Active"
bitfld.long 0x14 0.--1. " CLKTRCTRL ,OCMC 0 clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
line.long 0x18 "CM_ALWON_OCMC_1_CLKSTCTRL,OCMC 1 Clock Domain State Transitions Control Register"
bitfld.long 0x18 8. " CLKACTIVITY_OCMC_1_GCLK ,State of the OCMC_1_GICLK clock" "Gated,Active"
bitfld.long 0x18 0.--1. " CLKTRCTRL ,OCMC 1 clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
rgroup.long 0x141c++0x13
line.long 0x00 "CM_ALWON_MPU_CLKSTCTRL,MPU Clock Domain State Transitions Control Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MPU clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
else
bitfld.long 0x00 8. " CLKACTIVITY_MPU_GCLK ,State of the MPU_GCLK clock" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,MPU clock state transition control" "Reserved,SW_SLEEP,SW_WKUP,?..."
endif
line.long 0x04 "CM_ALWON_SYSCLK4_CLKSTCTRL,SYSCLK4 Clock Domain State Transitions Control Register"
bitfld.long 0x04 11. " CLKACTIVITY_L3_F_EN_GCLK ,State of the L3_F_EN_GCLK clock" "Gated,Active"
bitfld.long 0x04 10. " CLKACTIVITY_L3_S_GCLK ,State of the L3_S_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x04 9. " CLKACTIVITY_L3_M_GCLK ,State of the L3_M_GCLK clock" "Gated,Active"
bitfld.long 0x04 8. " CLKACTIVITY_SYSCLK4_GCLK ,State of the SYSCLK4_GCLK clock" "Gated,Active"
textline " "
bitfld.long 0x04 0.--1. " CLKTRCTRL ,SYSCLK4 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
line.long 0x08 "CM_ALWON_SYSCLK5_CLKSTCTRL,SYSCLK5 Clock Domain State Transitions Control Register"
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
bitfld.long 0x08 8. " CLKACTIVITY_DEBUG_CLKA_GCLK ,State of the Debug clockA clock" "Gated,Active"
textline " "
endif
bitfld.long 0x08 8. " CLKACTIVITY_SYSCLK5_GCLK ,State of the SYSCLK5_GCLK clock" "Gated,Active"
bitfld.long 0x08 0.--1. " CLKTRCTRL ,SYSCLK5 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
line.long 0x0c "CM_ALWON_SYSCLK6_CLKSTCTRL,SYSCLK6 Clock Domain State Transitions Control Register"
bitfld.long 0x0c 8. " CLKACTIVITY_SYSCLK6_GCLK ,State of the SYSCLK6_GCLK clock" "Gated,Active"
bitfld.long 0x0c 0.--1. " CLKTRCTRL ,SYSCLK6 clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
line.long 0x10 "CM_ALWON_RTC_CLKSTCTRL,RTC Clock Domain State Transitions Control Register"
bitfld.long 0x10 8. " CLKACTIVITY_RTC_GCLK ,State of the RTC_GCLK clock" "Gated,Active"
bitfld.long 0x10 0.--1. " CLKTRCTRL ,RTC clock state transition control" "Reserved,Reserved,SW_WKUP,?..."
sif ((cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x1430++0x3
line.long 0x00 "CM_ALWON_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
bitfld.long 0x00 9. " CLKACTIVITY_FAST_GCLK ,State of the L3 Fast clock for TPTC and TPCC" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Fast clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
else
group.long 0x1430++0x3
line.long 0x00 "CM_ALWON_L3_FAST_CLKSTCTRL,L3_FAST Clock Domain State Transitions Control Register"
bitfld.long 0x00 8. " CLKACTIVITY_FAST_GCLK ,State of the L3 Fast clock for TPTC and TPCC" "Gated,Active"
bitfld.long 0x00 0.--1. " CLKTRCTRL ,L3 Fast clock state transition control" "NO_SLEEP,SW_SLEEP,SW_WKUP,HW_AUTO"
endif
width 29.
group.long 0x1540++0x1b
line.long 0x0 "CM_ALWON_MCASP0_CLKCTRL,MCASP0 Clocks Control Register"
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_MCASP1_CLKCTRL,MCASP1 Clocks Control Register"
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_MCASP2_CLKCTRL,MCASP2 Clocks Control Register"
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0xC "CM_ALWON_MCBSP_CLKCTRL,MCBSP Clocks Control Register"
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x10 "CM_ALWON_UART_0_CLKCTRL,UART_0 Clocks Control Register"
rbitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x14 "CM_ALWON_UART_1_CLKCTRL,UART_1 Clocks Control Register"
rbitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x18 "CM_ALWON_UART_2_CLKCTRL,UART_2 Clocks Control Register"
rbitfld.long 0x18 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x18 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x155c++0xf
line.long 0x00 "CM_ALWON_GPIO_0_CLKCTRL,GPIO_0 Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
bitfld.long 0x00 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_ALWON_GPIO_1_CLKCTRL,GPIO_1 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
bitfld.long 0x04 8. " OPTFCLKEN_DBCLK ,Optional functional clock control" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x08 "CM_ALWON_I2C_0_CLKCTRL,I2C_0 Clocks Control Register"
rbitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x0c "CM_ALWON_I2C_1_CLKCTRL,I2C_1 Clocks Control Register"
rbitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif ((cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.long 0x156c++0x3
line.long 0x00 "CM_ALWON_MCASP_3_4_5_CLKCTRL,MCASP_3_4_5 Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x1570++0x7
line.long 0x00 "CM_ALWON_ATL_CLKCTRL,ATL Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_ALWON_MLB_CLKCTRL,MLB Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x1578++0x3
line.long 0x00 "CM_ALWON_PATA_CLKCTRL,PATA Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x1580++0xb
line.long 0x0 "CM_ALWON_UART_3_CLKCTRL,UART_3 Clocks Control Register"
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_UART_4_CLKCTRL,UART_4 Clocks Control Register"
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_UART_5_CLKCTRL,UART_5 Clocks Control Register"
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
else
group.long 0x1570++0x1b
line.long 0x0 "CM_ALWON_TIMER_1_CLKCTRL,TIMER_1 Clocks Control Register"
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_TIMER_2_CLKCTRL,TIMER_2 Clocks Control Register"
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_TIMER_3_CLKCTRL,TIMER_3 Clocks Control Register"
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0xC "CM_ALWON_TIMER_4_CLKCTRL,TIMER_4 Clocks Control Register"
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x10 "CM_ALWON_TIMER_5_CLKCTRL,TIMER_5 Clocks Control Register"
rbitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x14 "CM_ALWON_TIMER_6_CLKCTRL,TIMER_6 Clocks Control Register"
rbitfld.long 0x14 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x14 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x18 "CM_ALWON_TIMER_7_CLKCTRL,TIMER_7 Clocks Control Register"
rbitfld.long 0x18 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (OCP),Disabled"
textline " "
bitfld.long 0x18 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
rgroup.long 0x158c++0x3
line.long 0x00 "CM_ALWON_WDTIMER_CLKCTRL,WDTIMER Clocks Control Register"
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x1590++0xf
line.long 0x00 "CM_ALWON_SPI_CLKCTRL,SPI Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_ALWON_MAILBOX_CLKCTRL,MAILBOX Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x08 "CM_ALWON_SPINBOX_CLKCTRL,SPINBOX Clocks Control Register"
rbitfld.long 0x08 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x08 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x0c "CM_ALWON_MMUDATA_CLKCTRL,MMU Data Clocks Control Register"
rbitfld.long 0x0c 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0c 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x15a8++0x3
line.long 0x00 "CM_ALWON_MMUCFG_CLKCTRL,MMU Config Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x15b0++0xb
line.long 0x00 "CM_ALWON_SDIO_CLKCTRL,SDIO Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
group.long 0x15b4++0x7
line.long 0x00 "CM_ALWON_OCMC_0_CLKCTRL,OCMC_0 Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
line.long 0x04 "CM_ALWON_VCP_CLKCTRL,VCP Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
else
line.long 0x04 "CM_ALWON_OCMC_1_CLKCTRL,OCMC_1 Clocks Control Register"
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
group.long 0x15c4++0x3
line.long 0x00 "CM_ALWON_CONTRL_CLKCTRL,CONTRL Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x15d0++0xb
line.long 0x00 "CM_ALWON_GPMC_CLKCTRL,GPMC Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x04 "CM_ALWON_ETHERNET_0_CLKCTRL,ETHERNET_0 Clocks Control Register"
rbitfld.long 0x04 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x04 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x04 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x15d8++0x03
line.long 0x00 "CM_ALWON_ETHERNET_1_CLKCTRL,ETHERNET_1 Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
rgroup.long 0x15dc++0x3
line.long 0x00 "CM_ALWON_MPU_CLKCTRL,MPU Clocks Control Register"
rbitfld.long 0x00 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
bitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Reserved,Reserved,Enabled,?..."
rgroup.long 0x15e4++0xf
line.long 0x0 "CM_ALWON_L3_CLKCTRL,L3 Clocks Control Register"
bitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_L4HS_CLKCTRL,L4HS Clocks Control Register"
bitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_L4LS_CLKCTRL,L4LS Clocks Control Register"
bitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0xC "CM_ALWON_RTC_CLKCTRL,RTC Clocks Control Register"
bitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x15f4++0x3
line.long 0x00 "CM_ALWON_TPCC_CLKCTRL,TPCC Clocks Control Register"
rbitfld.long 0x00 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x00 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
group.long 0x15f8++0xf
line.long 0x0 "CM_ALWON_TPTC0_CLKCTRL,TPTC0 Clocks Control Register"
rbitfld.long 0x0 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_TPTC1_CLKCTRL,TPTC1 Clocks Control Register"
rbitfld.long 0x4 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_TPTC2_CLKCTRL,TPTC2 Clocks Control Register"
rbitfld.long 0x8 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0xC "CM_ALWON_TPTC3_CLKCTRL,TPTC3 Clocks Control Register"
rbitfld.long 0xC 18. " STBYST ,Module standby status" "Functional,Standby"
textline " "
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
sif (cpu()!="DM8147DSP"&&cpu()!="DM8148DSP")
group.long 0x1608++0x7
line.long 0x0 "CM_ALWON_SR_0_CLKCTRL,Smart Reflex 0 Clocks Control Register"
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_SR_1_CLKCTRL,Smart Reflex 1 Clocks Control Register"
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
sif (cpu()=="DM8147DSP"||cpu()=="DM8148DSP")
group.long 0x1618++0x13
line.long 0x0 "CM_ALWON_DCAN_0_1_CLKCTRL,DCAN_0_1 Clocks Control Register"
rbitfld.long 0x0 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x0 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x4 "CM_ALWON_MMCHS_0_CLKCTRL,MMCHS_0 Clocks Control Register"
rbitfld.long 0x4 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x4 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x8 "CM_ALWON_MMCHS_1_CLKCTRL,MMCHS_1 Clocks Control Register"
rbitfld.long 0x8 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x8 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0xC "CM_ALWON_MMCHS_2_CLKCTRL,MMCHS_2 Clocks Control Register"
rbitfld.long 0xC 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0xC 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
line.long 0x10 "CM_ALWON_CUST_EFUSE_CLKCTRL,CUST_EFUSE Clocks Control Register"
rbitfld.long 0x10 16.--17. " IDLEST ,Module idle status" "Functional,WKUP/SLEEP/SLEEP abortion,Idle (INTERCONN),Disabled"
textline " "
bitfld.long 0x10 0.--1. " MODULEMODE ,Mandatory clocks management control" "Disabled,Reserved,Enabled,?..."
endif
tree.end
tree.end
width 11.
tree.end
tree "RTC (Real Time Clock)"
base ad:0x480C0000
width 0x14
group.long 0x0000++0x03
line.long 0x00 "SECOND,Seconds Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
bitfld.long 0x00 04.--07. " SEC ,Second" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
else
bitfld.long 0x00 04.--06. " SEC ,Second" "0,1,2,3,4,5,-,-"
endif
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
group.long 0x0004++0x03
line.long 0x00 "MINUTE,Minutes Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1707"&&cpu()!="AM1802"&&cpu()!="AM1806"&&cpu()!="AM1808"&&cpu()!="AM1810")
bitfld.long 0x00 04.--07. " MIN ,Minute" "0,1,2,3,4,5,-,-,-,-,-,-,-,?..."
else
bitfld.long 0x00 04.--06. " MIN ,Minute" "0,1,2,3,4,5,-,-"
endif
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x08)&0x30)==0x10)
group.long 0x0008++0x03
line.long 0x00 "HOUR,Hours Register"
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x08)&0x30)!=0x10)
group.long 0x0008++0x03
line.long 0x00 "HOUR,Hours Register"
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x08)&0x30)==0x20)
group.long 0x0008++0x03
line.long 0x00 "HOUR,Hours Register"
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x0008++0x03
line.long 0x00 "HOUR,Hours Register"
bitfld.long 0x00 04.--05. " HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)==0x30)
group.long 0x000C++0x03
line.long 0x00 "DAY,Days Register"
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)!=0x30)
group.long 0x000C++0x03
line.long 0x00 "DAY,Days Register"
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==0x02))
group.long 0x000C++0x03
line.long 0x00 "DAY,Days Register"
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x10)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x0c))&0x30)==0x30)
group.long 0x000C++0x03
line.long 0x00 "DAY,Days Register"
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x000C++0x03
line.long 0x00 "DAY,Days Register"
bitfld.long 0x00 04.--05. " DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x10)&0x10)==0x10))
//MONTH->MONTH[4.]=='1'
group.long 0x0010++0x03
line.long 0x00 "MONTH,Months Register"
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x0010++0x03
line.long 0x00 "MONTH,Months Register"
bitfld.long 0x00 04. " MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
group.long 0x0014++0x03
line.long 0x00 "YEAR,Years Register"
bitfld.long 0x00 04.--07. " YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
group.long 0x0018++0x03
line.long 0x00 "DOTW,Day of the Week Register"
bitfld.long 0x00 00.--02. " DOTW ,Day of the week" "Sun,Mon,Tue,Wed,Thu,Fri,Sat,-"
group.long 0x0020++0x03
line.long 0x00 "ALARMSECOND,Alarm Seconds Register"
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
group.long 0x0024++0x03
line.long 0x00 "ALARMMINUTE,Alarm Minutes Register"
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x28)&0x30)==0x10)
group.long 0x0028++0x03
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x28)&0x30)!=0x10)
group.long 0x0028++0x03
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x28)&0x30)==0x20)
group.long 0x0028++0x03
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x0028++0x03
line.long 0x00 "ALARMHOUR,Alarm Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)==0x30)
group.long 0x002C++0x03
line.long 0x00 "ALARMDAY,Alarm Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)!=0x30)
group.long 0x002C++0x03
line.long 0x00 "ALARMDAY,Alarm Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==0x02))
group.long 0x002C++0x03
line.long 0x00 "ALARMDAY,Alarm Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
elif (((data.long(ad:0x480C0000+0x30)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x2c))&0x30)==0x30)
group.long 0x002C++0x03
line.long 0x00 "ALARMDAY,Alarm Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x002C++0x03
line.long 0x00 "ALARMDAY,Alarm Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x30))&0x10)==0x10)
group.long 0x0030++0x03
line.long 0x00 "ALARMMONTH,Alarm Months Register"
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x30))&0x10)==0x00)
group.long 0x0030++0x03
line.long 0x00 "ALARMMONTH,Alarm Months Register"
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
group.long 0x0034++0x03
line.long 0x00 "ALARMYEAR,Alarm Years Register"
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
group.long 0x0040++0x13
line.long 0x00 "CTRL,RTC Control Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("AM387*")))&&(cpu()!="AM3872")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x00 07. " SPLITPOWER ,Enable split power" "Disabled,Enabled"
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
else
bitfld.long 0x00 06. " RTCDISABLE ,Disable RTC" "No,Yes"
endif
textline " "
bitfld.long 0x00 05. " SET32COUNTER ,Set the 32-kHz counter" "No action,Set"
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 04. " TESTMODE ,Test mode" "Functional,Test"
endif
textline " "
bitfld.long 0x00 03. " HOURMODE ,Mode 12-hours or 24-hours" "24-hour,12-hour"
bitfld.long 0x00 02. " AUTOCOMP ,Enable autocompensation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 01. " ROUNDMIN ,Round time to the closest minute" "Not rounded,Rounded"
bitfld.long 0x00 00. " RUN ,Stop RTC" "Stopped,Running"
line.long 0x04 "STATUS,RTC Status Register"
sif (cpuis("DRA62*"))
eventfld.long 0x04 07. " ALARM2 ,Alarm2 interrupt" "No interrupt,Interrupt"
textline " "
endif
eventfld.long 0x04 06. " ALARM ,Alarm interrupt" "No interrupt,Interrupt"
textline " "
bitfld.long 0x04 05. " DAYEVT ,One day has occurred" "Not occurred,Occurred"
bitfld.long 0x04 04. " HREVT ,One hour has occurred" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 03. " MINEVT ,One minute has occurred" "Not occurred,Occurred"
bitfld.long 0x04 02. " SECEVT ,One second has occurred" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 01. " RUN ,RTC run" "Stopped,Running"
bitfld.long 0x04 00. " BUSY ,Updating event in more than 15 us" "Not busy,Busy"
line.long 0x08 "INTERRUPT,RTC Interrupt Register"
sif (cpuis("DRA62*"))
bitfld.long 0x08 04. " ALARM2 ,Enable one interrupt when the alarm2 value is reached" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x08 03. " ALARM ,Enable one interrupt when the alarm value is reached" "Disabled,Enabled"
bitfld.long 0x08 02. " TIMER ,Enable periodic interrupt" "Disabled,Enabled"
textline " "
bitfld.long 0x08 00.--01. " EVERY ,Interrupt period" "Every second,Every minute,Every hour,Every day"
line.long 0x0c "COMPLSB,RTC Compensation LSB Register"
hexmask.long.byte 0x0c 00.--07. 1. " COMPLSB ,Lower bits of the 16-bit compensation value"
line.long 0x10 "COMPMSB,RTC Compensation MSB Register"
hexmask.long.byte 0x10 00.--07. 1. " COMPMSB ,Higher bits of the 16-bit compensation value"
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
group.long 0x0054++0x03
else
wgroup.long 0x0054++0x03
endif
line.long 0x00 "OSC,RTC Oscillator Register"
sif (cpuis("DRA62*"))
bitfld.long 0x00 6. " 32KCLK_EN ,32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk" "Disabled,Enabled"
bitfld.long 0x00 4. " OSC32K_GZ ,Disable the oscillator and apply high impedance to the output" "No,Yes"
textline " "
bitfld.long 0x00 3. " 32KCLK_SEL ,32-kHz clock source select" "rtc_32k_clk_rtc_32k_aux_clk,rtc_32k_clk_rtc_32k_clk"
textline " "
bitfld.long 0x00 2. " RES_SELECT ,External feedback resistor" "Internal,External"
textline " "
bitfld.long 0x00 1. " SW2 ,Inverter size adjustment" "Low,High"
bitfld.long 0x00 0. " SW1 ,Inverter size adjustment" "Low,High"
else
bitfld.long 0x00 05. " SWRESET ,Software reset" "No effect,Reset"
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 04. " OSC32KPWRDNR ,Control of 32 kHz Oscillator powerdown" "Disabled,Enabled"
textline " "
bitfld.long 0x00 00.--03. " SWRESPROG ,Value of the oscillator resistance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
endif
endif
group.long 0x0060++0x013
line.long 0x00 "SCRATCH0,Scratch Register 0"
line.long 0x04 "SCRATCH1,Scratch Register 1"
line.long 0x08 "SCRATCH2,Scratch Register 2"
line.long 0x0c "KICK0R,Kick 0 Register"
line.long 0x10 "KICK1R,Kick 1 Register"
sif ((cpuis("AM389*"))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
rgroup.long 0x0074++0x03
line.long 0x00 "REVISION,RTC Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Indicates a software compatible module family"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x0078++0x07
line.long 0x00 "SYSCONFIG,System Configuration Register"
bitfld.long 0x00 0.--1. " IDLEMODE ,Idle mode" "Force-idle,No-idle,Smart-idle,Smart-idle/wakeup-capable"
line.long 0x04 "IRQWAKEEN,Wakeup Enable Register"
bitfld.long 0x04 1. " ALARM_WAKEEN ,Wakeup generation for event Alarm" "Disabled,Enabled"
bitfld.long 0x04 0. " TIMER_WAKEEN ,Wakeup generation for event Timer" "Disabled,Enabled"
endif
sif (cpuis("DRA62*"))
group.long 0x0080++0x03
line.long 0x00 "ALARM2SECOND,Alarm2 Seconds Register"
bitfld.long 0x00 04.--06. " AL_SEC ,Second" "0,1,2,3,4,5,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
group.long 0x0084++0x03
line.long 0x00 "ALARM2MINUTE,Alarm2 Minutes Register"
bitfld.long 0x00 04.--06. " AL_MIN ,Minute" "0,1,2,3,4,5,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
if ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x88)&0x30)==0x10)
group.long 0x0088++0x03
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x08)&&((data.long(ad:0x480C0000+0x88)&0x30)!=0x10)
group.long 0x0088++0x03
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,-,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 07. " MERIDIEM ,PM_AM mode" "AM,PM"
elif ((data.long(ad:0x480C0000+0x40)&0x08)==0x00)&&((data.long(ad:0x480C0000+0x88)&0x30)==0x20)
group.long 0x0088++0x03
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x0088++0x03
line.long 0x00 "ALARM2HOUR,Alarm2 Hours Register"
bitfld.long 0x00 04.--05. " AL_HOUR ,Hour" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)==0x30)
group.long 0x008C++0x03
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,-,-,-,-,-,-,-,-,-,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x04||0x06||0x09||0x11)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)!=0x30)
group.long 0x008C++0x03
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==0x02))
group.long 0x008C++0x03
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,-"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,?..."
elif (((data.long(ad:0x480C0000+0x90)&0x1f)==(0x01||0x03||0x05||0x07||0x08||0x10||0x12)))&&(((data.long(ad:0x480C0000+0x8c))&0x30)==0x30)
group.long 0x008C++0x03
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,-,-,-,-,-,-,-,-,-,-,-,?..."
else
group.long 0x008C++0x03
line.long 0x00 "ALARM2DAY,Alarm2 Days Register"
bitfld.long 0x00 04.--05. " AL_DAY ,Day" "0,1,2,3"
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
if (((data.long(ad:0x480C0000+0x90))&0x10)==0x10)
group.long 0x0090++0x03
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "0,1,2,-,-,-,-,-,-,-,-,-,-,?..."
elif (((data.long(ad:0x480C0000+0x90))&0x10)==0x00)
group.long 0x0090++0x03
line.long 0x00 "ALARM2MONTH,Alarm2 Months Register"
bitfld.long 0x00 04. " AL_MONTH ,Month" "0,1"
bitfld.long 0x00 00.--03. "," "-,1,2,3,4,5,6,7,8,9,-,-,-,?..."
endif
group.long 0x0094++0x0B
line.long 0x00 "ALARM2YEAR,Alarm2 Years Register"
bitfld.long 0x00 04.--07. " AL_YEAR ,Year" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
bitfld.long 0x00 00.--03. "," "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
line.long 0x04 "RTC_PMIC,RTC PMIC Register"
bitfld.long 0x04 17.--18. " PWR_ENABL_SM ,Power state machine state" "Idle,Shutdown,Time-based wakeup,External-event-based wakeup"
bitfld.long 0x04 16. " PWR_ENABLE_EN ,PWR_enable enable" "Disabled,Enabled"
textline " "
eventfld.long 0x04 15. " EXT_WAKEUP_STATUS[3] ,External wakeup status 3" "Not occurred,Occurred"
eventfld.long 0x04 14. " EXT_WAKEUP_STATUS[2] ,External wakeup status 2" "Not occurred,Occurred"
textline " "
eventfld.long 0x04 13. " EXT_WAKEUP_STATUS[1] ,External wakeup status 1" "Not occurred,Occurred"
eventfld.long 0x04 12. " EXT_WAKEUP_STATUS[0] ,External wakeup status 0" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 11. " EXT_WAKEUP_DB_EN[3] ,External wakeup debounce enabled 3" "Disabled,Enabled"
bitfld.long 0x04 10. " EXT_WAKEUP_DB_EN[2] ,External wakeup debounce enabled 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 9. " EXT_WAKEUP_DB_EN[1] ,External wakeup debounce enabled 1" "Disabled,Enabled"
bitfld.long 0x04 8. " EXT_WAKEUP_DB_EN[0] ,External wakeup debounce enabled 0" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " EXT_WAKEUP_POL[3] ,External wakeup inputs polarity 3" "Active high,Active low"
bitfld.long 0x04 6. " EXT_WAKEUP_POL[2] ,External wakeup inputs polarity 2" "Active high,Active low"
textline " "
bitfld.long 0x04 5. " EXT_WAKEUP_POL[1] ,External wakeup inputs polarity 1" "Active high,Active low"
bitfld.long 0x04 4. " EXT_WAKEUP_POL[0] ,External wakeup inputs polarity 0" "Active high,Active low"
textline " "
bitfld.long 0x04 3. " EXT_WAKEUP_EN[3] ,Enable external wakeup inputs 3" "Disabled,Enabled"
bitfld.long 0x04 2. " EXT_WAKEUP_EN[2] ,Enable external wakeup inputs 2" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " EXT_WAKEUP_EN[1] ,Enable external wakeup inputs 1" "Disabled,Enabled"
bitfld.long 0x04 0. " EXT_WAKEUP_EN[0] ,Enable external wakeup inputs 0" "Disabled,Enabled"
line.long 0x08 "RTC_DEBOUNCE,RTC Debounce Register"
hexmask.long.byte 0x08 8.--15. 1. " XX ,xx"
hexmask.long.byte 0x08 0.--7. 1. " DEBOUNCE_REG ,Debounce time"
endif
width 0xb
tree.end
tree "SATA (Serial ATA)"
base ad:0x4A140000
width 9.
rgroup.long 0x00++0x03
line.long 0x00 "CAP,HBA Capabilities Register"
bitfld.long 0x00 31. " S64A ,Indicates Support for 64-Bit Addressing" "32bit,?..."
bitfld.long 0x00 30. " SNCQ ,Supports Native Command Queuing" "Not supported,Supported"
textline " "
bitfld.long 0x00 29. " SSNTF ,Supports SNotification Register" "Not supported,Supported"
bitfld.long 0x00 28. " SMPS ,Supports Mechanical Presence Switch" "Not supported,Supported"
textline " "
bitfld.long 0x00 27. " SSS ,Supports Staggered Spin-Up" "Not supported,Supported"
bitfld.long 0x00 26. " SALP ,Supports Aggressive Link Power Management" "Not supported,Supported"
textline " "
bitfld.long 0x00 25. " SAL ,Supports Activity LED" "Not supported,Supported"
bitfld.long 0x00 24. " SCLO ,Supports Command List Override" "Not supported,Supported"
textline " "
bitfld.long 0x00 20.--23. " ISS ,Interface Speed Support" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 19. " SNZO ,Supports Non-Zero DMA Offsets" "Not supported,Supported"
textline " "
bitfld.long 0x00 18. " SAM ,Supports AHCI Mode Only" "Not supported,Supported"
bitfld.long 0x00 17. " SPM ,Supports Port Multiplier" "Not supported,Supported"
textline " "
bitfld.long 0x00 15. " PMD ,PIO Multiple DRQ Block" "Not supported,Supported"
bitfld.long 0x00 14. " SSC ,Slumber State Capable" "Low,High"
textline " "
bitfld.long 0x00 13. " PSC ,Partial State Capable" "Low,High"
bitfld.long 0x00 8.--12. " NCS ,Number of Command Slots" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
textline " "
bitfld.long 0x00 7. " CCCS ,Command Completion Coalescing Supported" "Not supported,Supported"
bitfld.long 0x00 6. " EMS ,Enclosure Management Supported" "Not supported,Supported"
textline " "
bitfld.long 0x00 5. " SXS ,Supports External SATA" "Not supported,Supported"
sif ((cpuis("AM387*"))||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1,2,?..."
elif (cpu()=="AM1810")||(cpu()=="AM1808")
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1 port,?..."
else
bitfld.long 0x00 0.--4. " NP ,Number of Ports" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
endif
group.long 0x04++0x07
line.long 0x00 "GHC,Global HBA Control Register"
bitfld.long 0x00 31. " AE ,AHCI Enable" "Disabled,Enabled"
bitfld.long 0x00 1. " IE ,Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " HR ,HBA Reset" "No reset,Reset"
line.long 0x04 "IS,Interrupt Status Register"
eventfld.long 0x04 1. " IPS1 ,Interrupt Pending Status" "No pending,Pending"
eventfld.long 0x04 0. " IPS0 ,Interrupt Pending Status" "No pending,Pending"
rgroup.long 0x0C++0x07
line.long 0x00 "PI,Ports Implemented Register"
bitfld.long 0x00 1. " PI1 ,Ports 1 Implemented" "Not implemented,Implemented"
bitfld.long 0x00 0. " PI0 ,Ports 0 Implemented" "Not implemented,Implemented"
line.long 0x04 "VS,AHCI Version Register"
hexmask.long.word 0x04 16.--31. 1. " MJR ,Major Revision Number"
hexmask.long.word 0x04 0.--15. 1. " MNR ,Minor Revision Number"
group.long 0x14++0x07
line.long 0x00 "CCC_CTL,Command Completion Coalescing Control Register"
hexmask.long.word 0x00 16.--31. 1. " TV ,Time-out value"
hexmask.long.byte 0x00 8.--15. 1. " CC ,Command Completions"
textline " "
bitfld.long 0x00 3.--7. " INT ,Specifies the interrupt used by the CCC feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 0. " EN ,CCC feature enable" "Disabled,Enabled"
width 9.
line.long 0x04 "CCC_PORTS,Command Completion Coalescing Ports Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
bitfld.long 0x04 31. " PRT[31] ,Ports 31 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 30. " PRT[30] ,Ports 30 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 29. " PRT[29] ,Ports 29 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 28. " PRT[28] ,Ports 28 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 27. " PRT[27] ,Ports 27 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 26. " PRT[26] ,Ports 26 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 25. " PRT[25] ,Ports 25 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 24. " PRT[24] ,Ports 24 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 23. " PRT[23] ,Ports 23 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 22. " PRT[22] ,Ports 22 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 21. " PRT[21] ,Ports 21 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 20. " PRT[20] ,Ports 20 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 19. " PRT[19] ,Ports 19 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 18. " PRT[18] ,Ports 18 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 17. " PRT[17] ,Ports 17 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 16. " PRT[16] ,Ports 16 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 15. " PRT[15] ,Ports 15 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 14. " PRT[14] ,Ports 14 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 13. " PRT[13] ,Ports 13 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 12. " PRT[12] ,Ports 12 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 11. " PRT[11] ,Ports 11 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 10. " PRT[10] ,Ports 10 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 9. " PRT[9] ,Ports 9 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 8. " PRT[8] ,Ports 8 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 7. " PRT[7] ,Ports 7 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 6. " PRT[6] ,Ports 6 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 5. " PRT[5] ,Ports 5 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
bitfld.long 0x04 4. " PRT[4] ,Ports 4 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 3. " PRT[3] ,Ports 3 command completion coalescing (CCC) feature" "Not CCC,CCC"
bitfld.long 0x04 2. " PRT[2] ,Ports 2 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
endif
sif (cpu()!="AM1810"&&cpu()!="AM1808")
bitfld.long 0x04 1. " PRT[1] ,Port 1 command completion coalescing (CCC) feature" "Not CCC,CCC"
textline " "
endif
bitfld.long 0x04 0. " PRT[0] ,Port 0 command completion coalescing (CCC) feature" "Not CCC,CCC"
rgroup.long 0xA0++0x03
width 9.
line.long 0x00 "BISTAFR,BIST Active FIS Register"
hexmask.long.byte 0x00 8.--15. 1. " NCP ,Non-Compliant Pattern"
hexmask.long.byte 0x00 0.--7. 1. " PD ,Pattern Definition"
group.long 0xA4++0x0B
line.long 0x00 "BISTCR,BIST Control Register"
bitfld.long 0x00 18. " TXO ,Transmit Only" "Disabled,Enabled"
bitfld.long 0x00 17. " CNTCLR ,Counter Clear" "Not cleared,Cleared"
textline " "
bitfld.long 0x00 16. " NEALB ,Near-end Analog Loopback" "Not requested,Requested"
textline " "
bitfld.long 0x00 10. " LLC_RPD ,Repeat primitive drop" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
textline " "
bitfld.long 0x00 9. " LLC_DESCRAM ,Descrambler" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
textline " "
bitfld.long 0x00 8. " LLC_SCRAM ,Scrambler" "Disabled(Normal)/Enabled(BIST),Enabled(Normal)/Disabled(BIST)"
textline " "
bitfld.long 0x00 6. " ERREN ,Error Enable" "Disabled,Enabled"
bitfld.long 0x00 5. " FLIP ,Flip Disparity" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4. " PV ,Pattern Version" "Short,Long"
bitfld.long 0x00 0.--3. " PATTERN ,Defines one of the following SATA compliant patterns" "Simultaneous switching outputs pattern (SSOP),High-transition density pattern,Low-transition density pattern,Low-frequency spectral component pattern (LFSCP),Composite pattern (COMP),Lone bit pattern (LBP),Mid-frequency test pattern (MFTP),High-frequency test pattern (HFTP),Low-frequency test pattern (LFTP),?..."
width 9.
line.long 0x04 "BISTFCTR,BIST FIS Count Register"
line.long 0x08 "BISTSR,BIST Status Register"
hexmask.long.byte 0x08 16.--23. 1. " BRSTERR ,Burst Error"
hexmask.long.word 0x08 0.--15. 1. " FRAMERR ,Frame Error"
rgroup.long 0xB0++0x03
line.long 0x00 "BISTDECR,BIST DWORD Error Count Register"
group.long 0xE0++0x03
line.long 0x00 "TIMER1MS,BIST DWORD Error Count Register"
hexmask.long.tbyte 0x00 0.--19. 1. " TIMV ,1ms Timer Value"
rgroup.long 0xE8++0x0B
line.long 0x00 "GPARAM1R,Global Parameter 1 Register"
bitfld.long 0x00 31. " ALIGN_M ,Rx Data Alignment" "Not aligned,Aligned"
bitfld.long 0x00 30. " RX_BUFFER ,Rx Data Buffer" "Not occurred,Occurred"
textline " "
bitfld.long 0x00 28.--29. " PHY_DATA ,PHY Data Width" "0,1,2,3"
bitfld.long 0x00 27. " PHY_RST ,PHY Reset Mode" "Low,High"
textline " "
bitfld.long 0x00 21.--26. " PHY_CTRL ,PHY Control Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 15.--20. " PHY_STAT ,PHY Status Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
textline " "
bitfld.long 0x00 14. " LATCH_M ,Latch Mode" "Disabled,Enabled"
bitfld.long 0x00 13. " BIST_M ,BIST Loopback Checking Depth" "Disabled,Enabled"
textline " "
bitfld.long 0x00 12. " PHY_TYPE ,PHY Interface Type" "Non-Synopsis,Synopsis"
bitfld.long 0x00 10. " RETURN_ERR ,AHB Error Response" "Not returned,Returned"
textline " "
bitfld.long 0x00 8.--9. " AHB_ENDIAN ,Bus Endianness" "0,1,2,3"
bitfld.long 0x00 7. " S_HADDR ,Slave address bus width" "32-bit,?..."
textline " "
bitfld.long 0x00 6. " M_HADDR ,Master address bus width" "32-bit,?..."
bitfld.long 0x00 3.--5. " S_HDATA ,Slave Data Bus Width" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 0.--2. " M_HDATA ,Master Data Bus Width" "0,1,2,3,4,5,6,7"
line.long 0x04 "GPARAM2R,Global Parameter 2 Register"
bitfld.long 0x04 14. " DEV_CP ,Cold Presence Detect" "Not occurred,Occurred"
bitfld.long 0x04 13. " DEV_MP ,Cold Presence Detect" "Not occurred,Occurred"
textline " "
bitfld.long 0x04 12. " ENCODE_M ,8b/10b Encoding/Decoding" "8-bit,10-bit"
bitfld.long 0x04 11. " RXOOB_CLK_M ,Rx OOB Clock Mode" "Disabled,Enabled"
textline " "
bitfld.long 0x04 10. " RX_OOB_M ,Rx OOB Mode" "Disabled,Enabled"
bitfld.long 0x04 9. " TX_OOB_M ,Tx OOB Mode" "Disabled,Enabled"
textline " "
hexmask.long.word 0x04 0.--8. 1. " RXOOB_CLK ,Rx OOB Clock Frequency"
line.long 0x08 "PPARAMR,Port Parameter Register"
bitfld.long 0x08 9. " TX_MEM_M ,Tx FIFO Memory Read Port Type" "Synchronous,Asynchronous"
bitfld.long 0x08 8. " TX_MEM_S ,Tx FIFO Memory Type" "Inside,Outside"
textline " "
bitfld.long 0x08 7. " RX_MEM_M ,Rx FIFO Memory Read Port Type" "Synchronous,Asynchronous"
bitfld.long 0x08 6. " RX_MEM_S ,Rx FIFO Memory Type" "Inside,Outside"
textline " "
bitfld.long 0x08 3.--5. " TX_FIFO_DEPTH ,Tx FIFO Depth" "32,64,128,256,512,1024,2048,4096"
bitfld.long 0x08 0.--2. " RX_FIFO_DEPTH ,Rx FIFO Depth" "32,64,128,256,512,1024,2048,4096"
sif (!(cpuis("AM387*")))
group.long 0xF4++0x03
line.long 0x00 "TESTR,Test Register"
bitfld.long 0x00 16.--18. " PSEL ,Port Select" "0,1,..."
bitfld.long 0x00 0. " TEST_IF ,Test Interface" "Normal,Test"
endif
rgroup.long 0xF8++0x07
line.long 0x00 "VERSIONR,Version Register"
line.long 0x04 "IDR,ID register"
group.long 0x100++0x03
line.long 0x00 "P0CLB,Port Command List Base Address Register"
hexmask.long 0x00 10.--31. 0x400 " CLB ,Command List Base Address"
group.long (0x100+0x08)++0x03
line.long 0x00 "P0FB,Port FIS Base Address Register"
hexmask.long.tbyte 0x00 8.--31. 1. " FB ,FIS Base Address"
group.long (0x100+0x10)++0x0B
line.long 0x00 "P0IS,Port Interrupt Status Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
eventfld.long 0x00 31. " CPDS ,Cold Port Detect Status" "No interrupt,Interrupt"
textline " "
endif
eventfld.long 0x00 30. " TFES ,Task File Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 29. " HBFS ,Host Bus Fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 28. " HBDS ,Host Bus Data Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 27. " IFS ,Interface Fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 26. " INFS ,Interface Non-fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 24. " OFS ,Overflow Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 23. " IPMS ,Incorrect Port Multiplier Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 22. " PRCS ,PHYReady Change Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " DMPS ,Device Mechanical Presence Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 6. " PCS ,Port Connect Change Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 5. " DPS ,Descriptor Processed" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " UFS ,Unknown FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " SDBS ,Set Device Bits Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " DSS ,DMA Setup FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " PSS ,PIO Setup FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " DHRS ,Device to Host Register FIS Interrupt" "No interrupt,Interrupt"
line.long 0x04 "P0IE,Port Interrupt Enable Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x04 31. " CPDE ,Cold Port Detect Enable" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x04 30. " TFEE ,Task File Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 29. " HBFE ,Host Bus Fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " HBDE ,Host Bus Data Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 27. " IFE ,Interface Fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " INFE ,Interface Non-fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " OFE ,Overflow Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 23. " IPME ,Incorrect Port Multiplier Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " PRCE ,PHYReady Change Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " DMPE ,Device Mechanical Presence Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " PCE ,Port Change Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " DPE ,Descriptor Processed Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " UFE ,Unknown FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " SDBE ,Set Device Bits FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 2. " DSE ,DMA Setup FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " PSE ,PIO Setup FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " DHRE ,Device Host Register FIS Interrupt Enable" "Disabled,Enabled"
line.long 0x08 "P0CMD,Port Command Register"
bitfld.long 0x08 28.--31. " ICC ,Interface Communication Control" "No-Op/ Idle,Active,Partial,Reserved,Reserved,Reserved,Slumber,?..."
textline " "
bitfld.long 0x08 27. " ASP ,Aggressive Slumber/Partial" "Partial,Slumber"
textline " "
bitfld.long 0x08 26. " ALPE ,Aggressive Link Power Management Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 25. " DLAE ,Drive LED on ATAPI Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 24. " ATAPI ,Device is ATAPI" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " ESP ,External SATA Port" "Disabled,Enabled"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x08 20. " CPD ,Cold Presence Detection" "Not supported,Supported"
textline " "
endif
bitfld.long 0x08 19. " MPSP ,Mechanical Presence Switch Attached to Port" "Not supported,Supported"
textline " "
bitfld.long 0x08 18. " HPCP ,Hot Plug" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " PMA ,Port Multiplier Attached" "Not attached,Attached"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x08 16. " CPS ,Cold Presence State" "Not attached,Attached"
else
bitfld.long 0x08 16. " CPD ,Cold Presence Detection" "Not supported,Supported"
endif
textline " "
bitfld.long 0x08 15. " CR ,Command List Running" "Stop,Running"
textline " "
bitfld.long 0x08 14. " FR ,FIS Receive Running" "Stop,Running"
textline " "
bitfld.long 0x08 13. " MPSS ,Mechanical Presence Switch State" "Closed,Open"
textline " "
bitfld.long 0x08 8.--12. " CCS ,Current Command Slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 4. " FRE ,FIS Receive Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " CLO ,Command List Override" "Not forced,Forced"
textline " "
bitfld.long 0x08 2. " POD ,Power On Device" "No,Yes"
textline " "
bitfld.long 0x08 1. " SUD ,Spin-Up Device" "No,Yes"
textline " "
bitfld.long 0x08 0. " ST ,Start" "Not forced,Forced"
rgroup.long (0x100+0x20)++0x0B
line.long 0x00 "P0TFD,Port Task File Data Register"
hexmask.long.byte 0x00 8.--15. 1. " ERR ,Contains the latest copy of the task file error register"
hexmask.long.byte 0x00 0.--7. 1. " STS ,Contains the latest copy of the task file status register"
line.long 0x04 "P0SIG,Port Signature Register"
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,LBA High (Cylinder High) Register"
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,LBA Mid (Cylinder Low) Register"
textline " "
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,LBA Low (Sector Number) Register"
hexmask.long.byte 0x04 0.--7. 1. " SCR ,Sector Count Register"
width 9.
line.long 0x08 "P0SSTS,Port Serial ATA Status Register"
bitfld.long 0x08 8.--11. " IPM ,Interface Power Management" "Not present/Not established,Interface in active state,Partial,Reserved,Reserved,Reserved,Slumber,?..."
textline " "
bitfld.long 0x08 4.--7. " SPD ,Current Interface Speed" "Not present/Not established,1.5 Gbps,3 Gbps,?..."
textline " "
bitfld.long 0x08 0.--3. " DET ,Device Detection" "No detected/not established,Detected/Not established,Reserved,Detected/Established,0ffline mode/Disabled /BIST loopback mode,?..."
group.long (0x100+0x2C)++0x13
line.long 0x00 "P0SCTL,Port Serial ATA Control Register"
bitfld.long 0x00 8.--11. " IPM ,Interface Power Management Transitions Allowed" "No interface power management state restrictions,Transitions to the Partial state are disabled,Transitions to the Slumber state are disabled,Transitions to both Partial and Slumber states are disabled,?..."
textline " "
bitfld.long 0x00 4.--7. " SPD ,Speed Allowed" "No speed negotiation restrictions,1.5 Gbps,3 Gbps,?..."
textline " "
bitfld.long 0x00 0.--3. " DET ,Device Detection Initialization" "No device detection /Requested,Interface initialization sequence,Reserved,Reserved,Disabled/Offline mode,?..."
width 9.
line.long 0x04 "P0SERR,Port Serial ATA Error Register"
eventfld.long 0x04 26. " DIAG_X ,Exchanged" "No error,Error"
eventfld.long 0x04 25. " DIAG_F ,Unknown FIS Type" "No error,Error"
eventfld.long 0x04 24. " DIAG_T ,Transport State Transition Error" "No error,Error"
textline " "
eventfld.long 0x04 23. " DIAG_S ,Link Sequence Error" "No error,Error"
eventfld.long 0x04 22. " DIAG_H ,Handshake Error" "No error,Error"
eventfld.long 0x04 21. " DIAG_C ,CRC Error" "No error,Error"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("AM387*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
else
bitfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
endif
eventfld.long 0x04 19. " DIAG_B ,10B to 8B Decode Error" "No error,Error"
eventfld.long 0x04 18. " DIAG_W ,Comm Wake" "No error,Error"
textline " "
eventfld.long 0x04 17. " DIAG_I ,PHY Internal Error" "No error,Error"
eventfld.long 0x04 16. " DIAG_N ,PHY Ready Change" "No error,Error"
eventfld.long 0x04 11. " ERR_E ,Internal Error" "No error,Error"
textline " "
eventfld.long 0x04 10. " ERR_P ,Protocol Error" "No error,Error"
eventfld.long 0x04 9. " ERR_C ,Non-recovered Persistent Communication Error" "No error,Error"
eventfld.long 0x04 8. " ERR_T ,Non-recovered Transient Data Integrity Error" "No error,Error"
textline " "
eventfld.long 0x04 1. " ERR_M ,Recovered Communication Error" "No error,Error"
eventfld.long 0x04 0. " ERR_I ,Recovered Data Integrity" "No error,Error"
line.long 0x08 "P0SACT,Port Serial ATA Active Register"
bitfld.long 0x08 31. " DS[31] ,Bit 31 corresponds to the TAG" "Low,High"
bitfld.long 0x08 30. " DS[30] ,Bit 30 corresponds to the TAG" "Low,High"
bitfld.long 0x08 29. " DS[29] ,Bit 29 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 28. " DS[28] ,Bit 28 corresponds to the TAG" "Low,High"
bitfld.long 0x08 27. " DS[27] ,Bit 27 corresponds to the TAG" "Low,High"
bitfld.long 0x08 26. " DS[26] ,Bit 26 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 25. " DS[25] ,Bit 25 corresponds to the TAG" "Low,High"
bitfld.long 0x08 24. " DS[24] ,Bit 24 corresponds to the TAG" "Low,High"
bitfld.long 0x08 23. " DS[23] ,Bit 23 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 22. " DS[22] ,Bit 22 corresponds to the TAG" "Low,High"
bitfld.long 0x08 21. " DS[21] ,Bit 21 corresponds to the TAG" "Low,High"
bitfld.long 0x08 20. " DS[20] ,Bit 20 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 19. " DS[19] ,Bit 19 corresponds to the TAG" "Low,High"
bitfld.long 0x08 18. " DS[18] ,Bit 18 corresponds to the TAG" "Low,High"
bitfld.long 0x08 17. " DS[17] ,Bit 17 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 16. " DS[16] ,Bit 16 corresponds to the TAG" "Low,High"
bitfld.long 0x08 15. " DS[15] ,Bit 15 corresponds to the TAG" "Low,High"
bitfld.long 0x08 14. " DS[14] ,Bit 14 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 13. " DS[13] ,Bit 13 corresponds to the TAG" "Low,High"
bitfld.long 0x08 12. " DS[12] ,Bit 12 corresponds to the TAG" "Low,High"
bitfld.long 0x08 11. " DS[11] ,Bit 11 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 10. " DS[10] ,Bit 10 corresponds to the TAG" "Low,High"
bitfld.long 0x08 9. " DS[9] ,Bit 9 corresponds to the TAG" "Low,High"
bitfld.long 0x08 8. " DS[8] ,Bit 8 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 7. " DS[7] ,Bit 7 corresponds to the TAG" "Low,High"
bitfld.long 0x08 6. " DS[6] ,Bit 6 corresponds to the TAG" "Low,High"
bitfld.long 0x08 5. " DS[5] ,Bit 5 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 4. " DS[4] ,Bit 4 corresponds to the TAG" "Low,High"
bitfld.long 0x08 3. " DS[3] ,Bit 3 corresponds to the TAG" "Low,High"
bitfld.long 0x08 2. " DS[2] ,Bit 2 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 1. " DS[1] ,Bit 1 corresponds to the TAG" "Low,High"
bitfld.long 0x08 0. " DS[0] ,Bit 0 corresponds to the TAG" "Low,High"
line.long 0x0C "P0CI,Port Command Issue Register"
bitfld.long 0x0C 31. " CI[31] ,Bit 31 corresponds to a command slot 31" "Low,High"
bitfld.long 0x0C 30. " CI[30] ,Bit 30 corresponds to a command slot 30" "Low,High"
bitfld.long 0x0C 29. " CI[29] ,Bit 29 corresponds to a command slot 29" "Low,High"
textline " "
bitfld.long 0x0C 28. " CI[28] ,Bit 28 corresponds to a command slot 28" "Low,High"
bitfld.long 0x0C 27. " CI[27] ,Bit 27 corresponds to a command slot 27" "Low,High"
bitfld.long 0x0C 26. " CI[26] ,Bit 26 corresponds to a command slot 26" "Low,High"
textline " "
bitfld.long 0x0C 25. " CI[25] ,Bit 25 corresponds to a command slot 25" "Low,High"
bitfld.long 0x0C 24. " CI[24] ,Bit 24 corresponds to a command slot 24" "Low,High"
bitfld.long 0x0C 23. " CI[23] ,Bit 23 corresponds to a command slot 23" "Low,High"
textline " "
bitfld.long 0x0C 22. " CI[22] ,Bit 22 corresponds to a command slot 22" "Low,High"
bitfld.long 0x0C 21. " CI[21] ,Bit 21 corresponds to a command slot 21" "Low,High"
bitfld.long 0x0C 20. " CI[20] ,Bit 20 corresponds to a command slot 20" "Low,High"
textline " "
bitfld.long 0x0C 19. " CI[19] ,Bit 19 corresponds to a command slot 19" "Low,High"
bitfld.long 0x0C 18. " CI[18] ,Bit 18 corresponds to a command slot 18" "Low,High"
bitfld.long 0x0C 17. " CI[17] ,Bit 17 corresponds to a command slot 17" "Low,High"
textline " "
bitfld.long 0x0C 16. " CI[16] ,Bit 16 corresponds to a command slot 16" "Low,High"
bitfld.long 0x0C 15. " CI[15] ,Bit 15 corresponds to a command slot 15" "Low,High"
bitfld.long 0x0C 14. " CI[14] ,Bit 14 corresponds to a command slot 14" "Low,High"
textline " "
bitfld.long 0x0C 13. " CI[13] ,Bit 13 corresponds to a command slot 13" "Low,High"
bitfld.long 0x0C 12. " CI[12] ,Bit 12 corresponds to a command slot 12" "Low,High"
bitfld.long 0x0C 11. " CI[11] ,Bit 11 corresponds to a command slot 11" "Low,High"
textline " "
bitfld.long 0x0C 10. " CI[10] ,Bit 10 corresponds to a command slot 10" "Low,High"
bitfld.long 0x0C 9. " CI[9] ,Bit 9 corresponds to a command slot 9" "Low,High"
bitfld.long 0x0C 8. " CI[8] ,Bit 8 corresponds to a command slot 8" "Low,High"
textline " "
bitfld.long 0x0C 7. " CI[7] ,Bit 7 corresponds to a command slot 7" "Low,High"
bitfld.long 0x0C 6. " CI[6] ,Bit 6 corresponds to a command slot 6" "Low,High"
bitfld.long 0x0C 5. " CI[5] ,Bit 5 corresponds to a command slot 5" "Low,High"
textline " "
bitfld.long 0x0C 4. " CI[4] ,Bit 4 corresponds to a command slot 4" "Low,High"
bitfld.long 0x0C 3. " CI[3] ,Bit 3 corresponds to a command slot 3" "Low,High"
bitfld.long 0x0C 2. " CI[2] ,Bit 2 corresponds to a command slot 2" "Low,High"
textline " "
bitfld.long 0x0C 1. " CI[1] ,Bit 1 corresponds to a command slot 1" "Low,High"
bitfld.long 0x0C 0. " CI[0] ,Bit 0 corresponds to a command slot 0" "Low,High"
line.long 0x10 "P0SNTF,Port Serial ATA Notification Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x10 15. " PMN[15] ,PM Notify" "Low,High"
eventfld.long 0x10 14. " PMN[14] ,PM Notify" "Low,High"
eventfld.long 0x10 13. " PMN[13] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 12. " PMN[12] ,PM Notify" "Low,High"
eventfld.long 0x10 11. " PMN[11] ,PM Notify" "Low,High"
eventfld.long 0x10 10. " PMN[10] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 9. " PMN[9] ,PM Notify" "Low,High"
eventfld.long 0x10 8. " PMN[8] ,PM Notify" "Low,High"
eventfld.long 0x10 7. " PMN[7] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 6. " PMN[6] ,PM Notify" "Low,High"
eventfld.long 0x10 5. " PMN[5] ,PM Notify" "Low,High"
eventfld.long 0x10 4. " PMN[4] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 3. " PMN[3] ,PM Notify" "Low,High"
eventfld.long 0x10 2. " PMN[2] ,PM Notify" "Low,High"
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
else
sif (cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
endif
endif
textline " "
eventfld.long 0x10 0. " PMN[0] ,PM Notify" "Low,High"
width 9.
group.long (0x100+0x70)++0x03
line.long 0x00 "P0DMACR,Port DMA Control Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
textline " "
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
else
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
textline " "
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,?..."
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,?..."
endif
sif (!(cpuis("AM387*")))
group.long (0x100+0x78)++0x03
line.long 0x00 "P0PHYCR,Port PHY Control Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x00 31. " ENPLL ,Enable Phy PLL" "Disabled,Enabled"
textline " "
bitfld.long 0x00 30. " OVERRIDE ,Override for Clock Stopping" "Normal,Override"
textline " "
bitfld.long 0x00 22.--25. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%"
textline " "
bitfld.long 0x00 19.--21. " TXSWING ,Transmitter Output Swing" "125,250,500,625,750,1000,1250,1375"
textline " "
bitfld.long 0x00 18. " TXCM ,Transmitter Common Mode" "Normal,Raised"
textline " "
bitfld.long 0x00 17. " TXINVPAIR ,Transmitter Invert Polarity" "No,Yes"
textline " "
bitfld.long 0x00 13.--16. " RXEQ ,Receiver Equalizer" "-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,365 MHz,275 MHz,195 MHz,140 MHz,105 MHz,75 MHz,55 MHz,50 MHz"
textline " "
bitfld.long 0x00 10.--12. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 16,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 16,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 16,First order/Threshold of 1 with fast lock,Second order/Low precision with fast lock"
textline " "
bitfld.long 0x00 8.--9. " RXTERM ,Receiver Termination" "V_SSA,0.8 V_DDA,0.2 V_DDA,Wide common mode range"
textline " "
bitfld.long 0x00 7. " RXINVPAIR ,Receiver Invert Polarity" "No,Yes"
textline " "
bitfld.long 0x00 6. " LOS ,Loss of Signal Detection" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4.--5. " LB ,Loop Bandwidth" "Medium,Ultra High,Low,High"
textline " "
bitfld.long 0x00 0.--3. " MPY ,PLL Multiply" "Reserved,5x,6x,Reserved,8x,10x,12x,12.5x,15x,20x,25x,?..."
else
bitfld.long 0x00 27.--31. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%,?..."
textline " "
bitfld.long 0x00 23.--26. " TXSWING ,Transmitter Output Swing" "100,1,2,3,4,5,6,7,8,9,10,11,12,13,14,1000"
textline " "
bitfld.long 0x00 22. " TXCM ,Transmitter Common Mode" "Normal,Raised"
textline " "
bitfld.long 0x00 21. " TXINVPAIR ,Transmitter Invert Polarity" "Not inverted,Inverted"
textline " "
bitfld.long 0x00 20. " RXENOC ,Receiver Offset Compensation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16.--19. " RXEQ ,Receiver Equalizer Configuration (Low Frequency Gain/Zero Frequency)" "Max/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
textline " "
bitfld.long 0x00 13.--15. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 17,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 1,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 1,?..."
textline " "
bitfld.long 0x00 12. " RXLOS ,Loss of Signal Detection" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10.--11. " LOOPBACK ,Transmitter(T) and Receiver(R) Loopback(LB) Selection" "T/R-Disabled,Reserved,T-LB/R-N/A,T/R-LB"
textline " "
bitfld.long 0x00 9. " RXINVPAIR ,Receiver Invert Polarity" "Not inverted,Inverted"
textline " "
bitfld.long 0x00 7.--8. " CLKBYP ,Clock Bypass" "Not bypassed,Reserved,Functional,REFCLK observe"
textline " "
bitfld.long 0x00 5.--6. " LB ,Loopback enable" "Disabled,Reserved,Inner/CML-disabled,Inner/CML-enabled"
textline " "
bitfld.long 0x00 1.--4. " MPY ,PLL Multiply" "4x,5x,6x,8x,8.25x,10x,12x,12.5x,15x,16x,16.5x,20x,22x,25x,?..."
textline " "
bitfld.long 0x00 0. " ENPLL ,Enable PHY PLL" "Disabled,Enabled"
endif
width 9.
rgroup.long (0x100+0x7C)++0x03
line.long 0x00 "P0PHYSR,Port PHY Status Register"
bitfld.long 0x00 1. " SIGDET ,Signal Detect" "Not detected,Detected"
bitfld.long 0x00 0. " LOCK ,PLL Lock" "Not locked,Locked"
endif
group.long 0x180++0x03
line.long 0x00 "P1CLB,Port Command List Base Address Register"
hexmask.long 0x00 10.--31. 0x400 " CLB ,Command List Base Address"
group.long (0x180+0x08)++0x03
line.long 0x00 "P1FB,Port FIS Base Address Register"
hexmask.long.tbyte 0x00 8.--31. 1. " FB ,FIS Base Address"
group.long (0x180+0x10)++0x0B
line.long 0x00 "P1IS,Port Interrupt Status Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
eventfld.long 0x00 31. " CPDS ,Cold Port Detect Status" "No interrupt,Interrupt"
textline " "
endif
eventfld.long 0x00 30. " TFES ,Task File Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 29. " HBFS ,Host Bus Fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 28. " HBDS ,Host Bus Data Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 27. " IFS ,Interface Fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 26. " INFS ,Interface Non-fatal Error Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 24. " OFS ,Overflow Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 23. " IPMS ,Incorrect Port Multiplier Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 22. " PRCS ,PHYReady Change Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 7. " DMPS ,Device Mechanical Presence Status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 6. " PCS ,Port Connect Change Status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 5. " DPS ,Descriptor Processed" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 4. " UFS ,Unknown FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 3. " SDBS ,Set Device Bits Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 2. " DSS ,DMA Setup FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 1. " PSS ,PIO Setup FIS Interrupt" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " DHRS ,Device to Host Register FIS Interrupt" "No interrupt,Interrupt"
line.long 0x04 "P1IE,Port Interrupt Enable Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x04 31. " CPDE ,Cold Port Detect Enable" "Disabled,Enabled"
textline " "
endif
bitfld.long 0x04 30. " TFEE ,Task File Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 29. " HBFE ,Host Bus Fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 28. " HBDE ,Host Bus Data Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 27. " IFE ,Interface Fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26. " INFE ,Interface Non-fatal Error Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 24. " OFE ,Overflow Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 23. " IPME ,Incorrect Port Multiplier Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 22. " PRCE ,PHYReady Change Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 7. " DMPE ,Device Mechanical Presence Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 6. " PCE ,Port Change Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 5. " DPE ,Descriptor Processed Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 4. " UFE ,Unknown FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 3. " SDBE ,Set Device Bits FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 2. " DSE ,DMA Setup FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 1. " PSE ,PIO Setup FIS Interrupt Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " DHRE ,Device Host Register FIS Interrupt Enable" "Disabled,Enabled"
line.long 0x08 "P1CMD,Port Command Register"
bitfld.long 0x08 28.--31. " ICC ,Interface Communication Control" "No-Op/ Idle,Active,Partial,Reserved,Reserved,Reserved,Slumber,?..."
textline " "
bitfld.long 0x08 27. " ASP ,Aggressive Slumber/Partial" "Partial,Slumber"
textline " "
bitfld.long 0x08 26. " ALPE ,Aggressive Link Power Management Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 25. " DLAE ,Drive LED on ATAPI Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 24. " ATAPI ,Device is ATAPI" "Disabled,Enabled"
textline " "
bitfld.long 0x08 21. " ESP ,External SATA Port" "Disabled,Enabled"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x08 20. " CPD ,Cold Presence Detection" "Not supported,Supported"
textline " "
endif
bitfld.long 0x08 19. " MPSP ,Mechanical Presence Switch Attached to Port" "Not supported,Supported"
textline " "
bitfld.long 0x08 18. " HPCP ,Hot Plug" "Disabled,Enabled"
textline " "
bitfld.long 0x08 17. " PMA ,Port Multiplier Attached" "Not attached,Attached"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x08 16. " CPS ,Cold Presence State" "Not attached,Attached"
else
bitfld.long 0x08 16. " CPD ,Cold Presence Detection" "Not supported,Supported"
endif
textline " "
bitfld.long 0x08 15. " CR ,Command List Running" "Stop,Running"
textline " "
bitfld.long 0x08 14. " FR ,FIS Receive Running" "Stop,Running"
textline " "
bitfld.long 0x08 13. " MPSS ,Mechanical Presence Switch State" "Closed,Open"
textline " "
bitfld.long 0x08 8.--12. " CCS ,Current Command Slot" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 4. " FRE ,FIS Receive Enable" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " CLO ,Command List Override" "Not forced,Forced"
textline " "
bitfld.long 0x08 2. " POD ,Power On Device" "No,Yes"
textline " "
bitfld.long 0x08 1. " SUD ,Spin-Up Device" "No,Yes"
textline " "
bitfld.long 0x08 0. " ST ,Start" "Not forced,Forced"
rgroup.long (0x180+0x20)++0x0B
line.long 0x00 "P1TFD,Port Task File Data Register"
hexmask.long.byte 0x00 8.--15. 1. " ERR ,Contains the latest copy of the task file error register"
hexmask.long.byte 0x00 0.--7. 1. " STS ,Contains the latest copy of the task file status register"
line.long 0x04 "P1SIG,Port Signature Register"
hexmask.long.byte 0x04 24.--31. 1. " LBA_HIGH ,LBA High (Cylinder High) Register"
hexmask.long.byte 0x04 16.--23. 1. " LBA_MID ,LBA Mid (Cylinder Low) Register"
textline " "
hexmask.long.byte 0x04 8.--15. 1. " LBA_LOW ,LBA Low (Sector Number) Register"
hexmask.long.byte 0x04 0.--7. 1. " SCR ,Sector Count Register"
width 9.
line.long 0x08 "P1SSTS,Port Serial ATA Status Register"
bitfld.long 0x08 8.--11. " IPM ,Interface Power Management" "Not present/Not established,Interface in active state,Partial,Reserved,Reserved,Reserved,Slumber,?..."
textline " "
bitfld.long 0x08 4.--7. " SPD ,Current Interface Speed" "Not present/Not established,1.5 Gbps,3 Gbps,?..."
textline " "
bitfld.long 0x08 0.--3. " DET ,Device Detection" "No detected/not established,Detected/Not established,Reserved,Detected/Established,0ffline mode/Disabled /BIST loopback mode,?..."
group.long (0x180+0x2C)++0x13
line.long 0x00 "P1SCTL,Port Serial ATA Control Register"
bitfld.long 0x00 8.--11. " IPM ,Interface Power Management Transitions Allowed" "No interface power management state restrictions,Transitions to the Partial state are disabled,Transitions to the Slumber state are disabled,Transitions to both Partial and Slumber states are disabled,?..."
textline " "
bitfld.long 0x00 4.--7. " SPD ,Speed Allowed" "No speed negotiation restrictions,1.5 Gbps,3 Gbps,?..."
textline " "
bitfld.long 0x00 0.--3. " DET ,Device Detection Initialization" "No device detection /Requested,Interface initialization sequence,Reserved,Reserved,Disabled/Offline mode,?..."
width 9.
line.long 0x04 "P1SERR,Port Serial ATA Error Register"
eventfld.long 0x04 26. " DIAG_X ,Exchanged" "No error,Error"
eventfld.long 0x04 25. " DIAG_F ,Unknown FIS Type" "No error,Error"
eventfld.long 0x04 24. " DIAG_T ,Transport State Transition Error" "No error,Error"
textline " "
eventfld.long 0x04 23. " DIAG_S ,Link Sequence Error" "No error,Error"
eventfld.long 0x04 22. " DIAG_H ,Handshake Error" "No error,Error"
eventfld.long 0x04 21. " DIAG_C ,CRC Error" "No error,Error"
textline " "
sif ((!(cpuis("AM389*")))&&(!(cpuis("AM387*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
else
bitfld.long 0x04 20. " DIAG_D ,Disparity Error" "No error,Error"
endif
eventfld.long 0x04 19. " DIAG_B ,10B to 8B Decode Error" "No error,Error"
eventfld.long 0x04 18. " DIAG_W ,Comm Wake" "No error,Error"
textline " "
eventfld.long 0x04 17. " DIAG_I ,PHY Internal Error" "No error,Error"
eventfld.long 0x04 16. " DIAG_N ,PHY Ready Change" "No error,Error"
eventfld.long 0x04 11. " ERR_E ,Internal Error" "No error,Error"
textline " "
eventfld.long 0x04 10. " ERR_P ,Protocol Error" "No error,Error"
eventfld.long 0x04 9. " ERR_C ,Non-recovered Persistent Communication Error" "No error,Error"
eventfld.long 0x04 8. " ERR_T ,Non-recovered Transient Data Integrity Error" "No error,Error"
textline " "
eventfld.long 0x04 1. " ERR_M ,Recovered Communication Error" "No error,Error"
eventfld.long 0x04 0. " ERR_I ,Recovered Data Integrity" "No error,Error"
line.long 0x08 "P1SACT,Port Serial ATA Active Register"
bitfld.long 0x08 31. " DS[31] ,Bit 31 corresponds to the TAG" "Low,High"
bitfld.long 0x08 30. " DS[30] ,Bit 30 corresponds to the TAG" "Low,High"
bitfld.long 0x08 29. " DS[29] ,Bit 29 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 28. " DS[28] ,Bit 28 corresponds to the TAG" "Low,High"
bitfld.long 0x08 27. " DS[27] ,Bit 27 corresponds to the TAG" "Low,High"
bitfld.long 0x08 26. " DS[26] ,Bit 26 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 25. " DS[25] ,Bit 25 corresponds to the TAG" "Low,High"
bitfld.long 0x08 24. " DS[24] ,Bit 24 corresponds to the TAG" "Low,High"
bitfld.long 0x08 23. " DS[23] ,Bit 23 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 22. " DS[22] ,Bit 22 corresponds to the TAG" "Low,High"
bitfld.long 0x08 21. " DS[21] ,Bit 21 corresponds to the TAG" "Low,High"
bitfld.long 0x08 20. " DS[20] ,Bit 20 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 19. " DS[19] ,Bit 19 corresponds to the TAG" "Low,High"
bitfld.long 0x08 18. " DS[18] ,Bit 18 corresponds to the TAG" "Low,High"
bitfld.long 0x08 17. " DS[17] ,Bit 17 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 16. " DS[16] ,Bit 16 corresponds to the TAG" "Low,High"
bitfld.long 0x08 15. " DS[15] ,Bit 15 corresponds to the TAG" "Low,High"
bitfld.long 0x08 14. " DS[14] ,Bit 14 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 13. " DS[13] ,Bit 13 corresponds to the TAG" "Low,High"
bitfld.long 0x08 12. " DS[12] ,Bit 12 corresponds to the TAG" "Low,High"
bitfld.long 0x08 11. " DS[11] ,Bit 11 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 10. " DS[10] ,Bit 10 corresponds to the TAG" "Low,High"
bitfld.long 0x08 9. " DS[9] ,Bit 9 corresponds to the TAG" "Low,High"
bitfld.long 0x08 8. " DS[8] ,Bit 8 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 7. " DS[7] ,Bit 7 corresponds to the TAG" "Low,High"
bitfld.long 0x08 6. " DS[6] ,Bit 6 corresponds to the TAG" "Low,High"
bitfld.long 0x08 5. " DS[5] ,Bit 5 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 4. " DS[4] ,Bit 4 corresponds to the TAG" "Low,High"
bitfld.long 0x08 3. " DS[3] ,Bit 3 corresponds to the TAG" "Low,High"
bitfld.long 0x08 2. " DS[2] ,Bit 2 corresponds to the TAG" "Low,High"
textline " "
bitfld.long 0x08 1. " DS[1] ,Bit 1 corresponds to the TAG" "Low,High"
bitfld.long 0x08 0. " DS[0] ,Bit 0 corresponds to the TAG" "Low,High"
line.long 0x0C "P1CI,Port Command Issue Register"
bitfld.long 0x0C 31. " CI[31] ,Bit 31 corresponds to a command slot 31" "Low,High"
bitfld.long 0x0C 30. " CI[30] ,Bit 30 corresponds to a command slot 30" "Low,High"
bitfld.long 0x0C 29. " CI[29] ,Bit 29 corresponds to a command slot 29" "Low,High"
textline " "
bitfld.long 0x0C 28. " CI[28] ,Bit 28 corresponds to a command slot 28" "Low,High"
bitfld.long 0x0C 27. " CI[27] ,Bit 27 corresponds to a command slot 27" "Low,High"
bitfld.long 0x0C 26. " CI[26] ,Bit 26 corresponds to a command slot 26" "Low,High"
textline " "
bitfld.long 0x0C 25. " CI[25] ,Bit 25 corresponds to a command slot 25" "Low,High"
bitfld.long 0x0C 24. " CI[24] ,Bit 24 corresponds to a command slot 24" "Low,High"
bitfld.long 0x0C 23. " CI[23] ,Bit 23 corresponds to a command slot 23" "Low,High"
textline " "
bitfld.long 0x0C 22. " CI[22] ,Bit 22 corresponds to a command slot 22" "Low,High"
bitfld.long 0x0C 21. " CI[21] ,Bit 21 corresponds to a command slot 21" "Low,High"
bitfld.long 0x0C 20. " CI[20] ,Bit 20 corresponds to a command slot 20" "Low,High"
textline " "
bitfld.long 0x0C 19. " CI[19] ,Bit 19 corresponds to a command slot 19" "Low,High"
bitfld.long 0x0C 18. " CI[18] ,Bit 18 corresponds to a command slot 18" "Low,High"
bitfld.long 0x0C 17. " CI[17] ,Bit 17 corresponds to a command slot 17" "Low,High"
textline " "
bitfld.long 0x0C 16. " CI[16] ,Bit 16 corresponds to a command slot 16" "Low,High"
bitfld.long 0x0C 15. " CI[15] ,Bit 15 corresponds to a command slot 15" "Low,High"
bitfld.long 0x0C 14. " CI[14] ,Bit 14 corresponds to a command slot 14" "Low,High"
textline " "
bitfld.long 0x0C 13. " CI[13] ,Bit 13 corresponds to a command slot 13" "Low,High"
bitfld.long 0x0C 12. " CI[12] ,Bit 12 corresponds to a command slot 12" "Low,High"
bitfld.long 0x0C 11. " CI[11] ,Bit 11 corresponds to a command slot 11" "Low,High"
textline " "
bitfld.long 0x0C 10. " CI[10] ,Bit 10 corresponds to a command slot 10" "Low,High"
bitfld.long 0x0C 9. " CI[9] ,Bit 9 corresponds to a command slot 9" "Low,High"
bitfld.long 0x0C 8. " CI[8] ,Bit 8 corresponds to a command slot 8" "Low,High"
textline " "
bitfld.long 0x0C 7. " CI[7] ,Bit 7 corresponds to a command slot 7" "Low,High"
bitfld.long 0x0C 6. " CI[6] ,Bit 6 corresponds to a command slot 6" "Low,High"
bitfld.long 0x0C 5. " CI[5] ,Bit 5 corresponds to a command slot 5" "Low,High"
textline " "
bitfld.long 0x0C 4. " CI[4] ,Bit 4 corresponds to a command slot 4" "Low,High"
bitfld.long 0x0C 3. " CI[3] ,Bit 3 corresponds to a command slot 3" "Low,High"
bitfld.long 0x0C 2. " CI[2] ,Bit 2 corresponds to a command slot 2" "Low,High"
textline " "
bitfld.long 0x0C 1. " CI[1] ,Bit 1 corresponds to a command slot 1" "Low,High"
bitfld.long 0x0C 0. " CI[0] ,Bit 0 corresponds to a command slot 0" "Low,High"
line.long 0x10 "P1SNTF,Port Serial ATA Notification Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP")&&cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x10 15. " PMN[15] ,PM Notify" "Low,High"
eventfld.long 0x10 14. " PMN[14] ,PM Notify" "Low,High"
eventfld.long 0x10 13. " PMN[13] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 12. " PMN[12] ,PM Notify" "Low,High"
eventfld.long 0x10 11. " PMN[11] ,PM Notify" "Low,High"
eventfld.long 0x10 10. " PMN[10] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 9. " PMN[9] ,PM Notify" "Low,High"
eventfld.long 0x10 8. " PMN[8] ,PM Notify" "Low,High"
eventfld.long 0x10 7. " PMN[7] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 6. " PMN[6] ,PM Notify" "Low,High"
eventfld.long 0x10 5. " PMN[5] ,PM Notify" "Low,High"
eventfld.long 0x10 4. " PMN[4] ,PM Notify" "Low,High"
textline " "
eventfld.long 0x10 3. " PMN[3] ,PM Notify" "Low,High"
eventfld.long 0x10 2. " PMN[2] ,PM Notify" "Low,High"
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
else
sif (cpu()!="AM1810"&&cpu()!="AM1808")
eventfld.long 0x10 1. " PMN[1] ,PM Notify" "Low,High"
endif
endif
textline " "
eventfld.long 0x10 0. " PMN[0] ,PM Notify" "Low,High"
width 9.
group.long (0x180+0x70)++0x03
line.long 0x00 "P1DMACR,Port DMA Control Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(!(cpuis("AM387*")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
textline " "
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,128 DWORDs,256 DWORDs,512 DWORDs,1024 DWORDs,?..."
else
bitfld.long 0x00 12.--15. " RXABL ,Receive Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
bitfld.long 0x00 8.--11. " TXABL ,Transmit Burst Limit" "256 DWORDS,1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,Reserved,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS,256 DWORDS"
textline " "
bitfld.long 0x00 4.--7. " RXTS ,Receive Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,64 DWORDs,?..."
bitfld.long 0x00 0.--3. " TXTS ,Transmit Transaction Size" "1 DWORD,2 DWORDs,4 DWORDs,8 DWORDs,16 DWORDs,32 DWORDs,?..."
endif
sif (!(cpuis("AM387*")))
group.long (0x180+0x78)++0x03
line.long 0x00 "P1PHYCR,Port PHY Control Register"
sif ((!(cpuis("AM389*")))&&(!(cpuis("C6A816*")))&&(!(cpuis("C6A816*DSP")))&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(!cpuis("DRA6*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
bitfld.long 0x00 31. " ENPLL ,Enable Phy PLL" "Disabled,Enabled"
textline " "
bitfld.long 0x00 30. " OVERRIDE ,Override for Clock Stopping" "Normal,Override"
textline " "
bitfld.long 0x00 22.--25. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%"
textline " "
bitfld.long 0x00 19.--21. " TXSWING ,Transmitter Output Swing" "125,250,500,625,750,1000,1250,1375"
textline " "
bitfld.long 0x00 18. " TXCM ,Transmitter Common Mode" "Normal,Raised"
textline " "
bitfld.long 0x00 17. " TXINVPAIR ,Transmitter Invert Polarity" "No,Yes"
textline " "
bitfld.long 0x00 13.--16. " RXEQ ,Receiver Equalizer" "-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,365 MHz,275 MHz,195 MHz,140 MHz,105 MHz,75 MHz,55 MHz,50 MHz"
textline " "
bitfld.long 0x00 10.--12. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 16,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 16,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 16,First order/Threshold of 1 with fast lock,Second order/Low precision with fast lock"
textline " "
bitfld.long 0x00 8.--9. " RXTERM ,Receiver Termination" "V_SSA,0.8 V_DDA,0.2 V_DDA,Wide common mode range"
textline " "
bitfld.long 0x00 7. " RXINVPAIR ,Receiver Invert Polarity" "No,Yes"
textline " "
bitfld.long 0x00 6. " LOS ,Loss of Signal Detection" "Disabled,Enabled"
textline " "
bitfld.long 0x00 4.--5. " LB ,Loop Bandwidth" "Medium,Ultra High,Low,High"
textline " "
bitfld.long 0x00 0.--3. " MPY ,PLL Multiply" "Reserved,5x,6x,Reserved,8x,10x,12x,12.5x,15x,20x,25x,?..."
else
bitfld.long 0x00 27.--31. " TXDE ,Transmitter De-Emphasis" "0%,4.76%,9.52%,14.28%,19.04%,23.8%,28.56%,33.32%,38.08%,42.85%,47.61%,52.38%,57.14%,61.9%,66.66%,71.42%,?..."
textline " "
bitfld.long 0x00 23.--26. " TXSWING ,Transmitter Output Swing" "100,1,2,3,4,5,6,7,8,9,10,11,12,13,14,1000"
textline " "
bitfld.long 0x00 22. " TXCM ,Transmitter Common Mode" "Normal,Raised"
textline " "
bitfld.long 0x00 21. " TXINVPAIR ,Transmitter Invert Polarity" "Not inverted,Inverted"
textline " "
bitfld.long 0x00 20. " RXENOC ,Receiver Offset Compensation" "Disabled,Enabled"
textline " "
bitfld.long 0x00 16.--19. " RXEQ ,Receiver Equalizer Configuration (Low Frequency Gain/Zero Frequency)" "Max/-,Adaptive,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Adaptive/365 MHz,Adaptive/275 MHz,Adaptive/195 MHz,Adaptive/140 MHz,Adaptive/105 MHz,Adaptive/75 MHz,Adaptive/55 MHz,Adaptive/50 MHz"
textline " "
bitfld.long 0x00 13.--15. " RXCDR ,Receiver Clock/data Recovery" "First order/Threshold of 1,First order/Threshold of 17,Second order/High precision/Threshold of 1,Second order/High precision/Threshold of 1,Second order/Low precision/Threshold of 1,Second order/Low precision/Threshold of 1,?..."
textline " "
bitfld.long 0x00 12. " RXLOS ,Loss of Signal Detection" "Disabled,Enabled"
textline " "
bitfld.long 0x00 10.--11. " LOOPBACK ,Transmitter(T) and Receiver(R) Loopback(LB) Selection" "T/R-Disabled,Reserved,T-LB/R-N/A,T/R-LB"
textline " "
bitfld.long 0x00 9. " RXINVPAIR ,Receiver Invert Polarity" "Not inverted,Inverted"
endif
width 9.
rgroup.long (0x180+0x7C)++0x03
line.long 0x00 "P1PHYSR,Port PHY Status Register"
bitfld.long 0x00 1. " SIGDET ,Signal Detect" "Not detected,Detected"
bitfld.long 0x00 0. " LOCK ,PLL Lock" "Not locked,Locked"
endif
sif ((cpuis("AM389*"))||((cpuis("AM387*")))||(cpuis("C6A816*"))||(cpuis("C6A816*DSP"))||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpuis("DRA6*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
width 9.
group.long 0x1100++0x07
line.long 0x00 "IDLE,Idle Register"
bitfld.long 0x00 17. " OVERRIDE1 ,Override for Clock Stopping" "Normal,Override"
bitfld.long 0x00 16. " OVERRIDE0 ,Override for Clock Stopping" "Normal,Override"
textline " "
bitfld.long 0x00 2.--3. " STANDBYMODE ,Standby_mode controle" "0,1,2,3"
bitfld.long 0x00 0.--1. " IDLEMODE ,Idle_mode controle" "0,1,2,3"
sif cpuis("AM387*")
line.long 0x04 "CFGRX0,PHY Configuration Receive 0 Register"
bitfld.long 0x04 31. " LOOPBACK[1] ,Internal Digital loop back" "Disabled,Not supported"
bitfld.long 0x04 30. " LOOPBACK[0] ,Internal Analog loop back" "Disabled,Not supported"
textline " "
bitfld.long 0x04 29. " RX_TRIM_BYPASS ,Trim bits generated from the calibration algorithm bypass (for calibration)" "Not bypassed,Bypassed"
bitfld.long 0x04 28. " CDR_ELV_IDLE_FIX ,CDR ELV Idle fix" "Disabled,Enabled"
textline " "
bitfld.long 0x04 26.--27. " CDRAUX ,Clock/data recovery auxilliary" "0,1,2,3"
bitfld.long 0x04 24.--25. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
textline " "
bitfld.long 0x04 23. " ENOC ,Enable offset compensation" "Disabled,Enabled"
bitfld.long 0x04 19.--22. " EQ ,Equalizer" "Disabled,Enabled,?..."
textline " "
bitfld.long 0x04 16.--18. " CDR ,Clock/data recovery" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 13.--15. " LOS ,Enables loss of signal detection" "Disabled,Enabled (without CDR override control),Enabled (with CDR override control),Disabled,Disabled,Disabled,Disabled,Disabled"
textline " "
bitfld.long 0x04 11.--12. " ALIGN ,Symbol alignment" "Disabled,Coma alignment,Alignment Jog,?..."
bitfld.long 0x04 8.--10. " TERM ,Selects input termination options" "Reserved,Common point set to 0.8 VDDA,Reserved,Common point floating,Common point set to VSSA,Common point set to 0.2 VDDA,Reserved,Common point floating"
textline " "
bitfld.long 0x04 7. " INVPAIR ,Inverts polarity of RXPi and RXNi" "Not inverted,Inverted"
bitfld.long 0x04 5.--6. " RATE ,Value being driven to the phy's RATE field" "0,1,2,3"
textline " "
bitfld.long 0x04 2.--4. " BUSWIDTH ,Parallel interface width" "10-bit,?..."
bitfld.long 0x04 1. " ENRXLDO ,Enables RXLDO" "Disabled,Enabled"
textline " "
bitfld.long 0x04 0. " ENRX ,Reflects the ENRX of the phy" "Not received,Received"
else
line.long 0x04 "PHYCFGR2,PHY Configuration Register 2"
bitfld.long 0x04 8.--9. " P1ALIGN ,Port 1 Comma Alignment Enable" "Disabled,Enabled,Jog,?..."
bitfld.long 0x04 6.--7. " P0ALIGN ,Port 0 Comma Alignment Enable" "Disabled,Enabled,Jog,?..."
textline " "
bitfld.long 0x04 3.--5. " P1LOS ,Port 1 Loss-of-Signal Configuration" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 0.--2. " P0LOS ,Port 0 Loss-of-Signal Configuration" "0,1,2,3,4,5,6,7"
endif
endif
sif cpuis("AM387*")
width 11.
group.long 0x1108++0x2b
line.long 0x00 "CFGRX1,PHY Configuration Receive 1 Register"
bitfld.long 0x00 30.--31. " EQ_ICM_S2 ,Trims common mode pullup current in second equalizer stage" "0,1,2,3"
bitfld.long 0x00 28.--29. " EQ_ICM_S1 ,Trims common mode pullup current in first equalizer stage" "0,1,2,3"
textline " "
bitfld.long 0x00 21.--23. " EQ_I_STAGE2 ,Trims the current in the second stage of the equalizer" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. " EQ_I_STAGEFB ,Trims the current in the feedback stage of the equalizer" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 15.--17. " EQ_I_STAGE1 ,Trims the current in the first stage of the equalizer" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 14. " ANALOG_LOOPBACK ,Enables analog loop back" "Disabled,Enabled"
textline " "
bitfld.long 0x00 13. " RXTRIM_CALIB ,RX trimming control to the calibration block" "Functional mode,eFuse training mode"
bitfld.long 0x00 12. " RXTRIM_BYPASS_CTRL ,RXTRIM bypass control" "Fuse/calib,Cfg_ctrl"
textline " "
bitfld.long 0x00 7.--11. " RXTRIM_BYPASS_BITS ,Bypass bits for RXTRIM[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 6. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the calout signal inside digital (for calibration)" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x00 5. " CTG_DIG_RSVD1 ,Clock inversion for rpclk" "Not inverted,Inverted"
bitfld.long 0x00 4. " CTG_DIG_RSVD0 ,Clock inversion for fclk" "Not inverted,Inverted"
textline " "
bitfld.long 0x00 3. " ENTEST ,Value on the serdes_testpatt_p0_entestrx input" "Low,High"
bitfld.long 0x00 0.--2. " TESTPATT ,Value on the serdes_testpatt_p0_testpatt input" "0,1,2,3,4,5,6,7"
line.long 0x04 "CFGRX2,PHY Configuration Receive 2 Register"
bitfld.long 0x04 27.--31. " SAMP_BYPASS_SAD1 ,Bypass bits for SAD1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 22.--26. " SAMP_BYPASS_SAT0 ,Bypass bits for SAT0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x04 17.--21. " SAMP_BYPASS_SAD0 ,Bypass bits for SAD0[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 12.--16. " SAMP_BYPASS_SAT1 ,Bypass bits for SAT1[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "CFGRX3,PHY Configuration Receive 3 Register"
bitfld.long 0x08 31. " AMUX_EYESCAN_REF ,Connect the eyescan reference voltages to the test mux inputs" "Low,High"
bitfld.long 0x08 30. " SAMP_OC_SEL ,Sampler offset correction is controlled" "TRXDIG SAT1/SAD0/SAT0/SAD1,CFG_CTRL/CFGRX_2"
textline " "
bitfld.long 0x08 24.--29. " SAMP_ES_VREF_BYPASS_BITS ,Adjusts the eyescan reference voltage level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 20.--23. " SAMP_ESCM_RES ,Trims the pullup resistors in the eyescan common mode loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x08 17.--19. " SAMP_ESCM_I ,Trims the current in the eyescan common mode loop" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 16. " SAMP_3_VREF_2_ES ,Sampler 3 VREF" "EQCM,Sampler 3"
textline " "
bitfld.long 0x08 15. " SAMP_2_VREF_2_ES ,Sampler 2 VREF" "EQCM,Sampler 2"
bitfld.long 0x08 14. " SAMP_1_VREF_2_ES ,Sampler 1 VREF" "EQCM,Sampler 1"
textline " "
bitfld.long 0x08 13. " SAMP_0_VREF_2_ES ,Sampler 0 VREF" "EQCM,Sampler 0"
bitfld.long 0x08 8.--12. " SAMP_IBIAS_Z ,Sampler bias" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x08 7. " SAMP_ES_VREF_BYPASS_CTRL ,Eyescan reference offset voltage control" "IEEE1500,CFGRX_3"
bitfld.long 0x08 3. " SAMP_EN_3_ODD ,Samapler 3" "Disabled,Enabled"
textline " "
bitfld.long 0x08 2. " SAMP_EN_2_EOTR ,Sampler 2" "Disabled,Enabled"
bitfld.long 0x08 1. " SAMP_EN_1_EVEN ,Sampler 1" "Disabled,Enabled"
textline " "
bitfld.long 0x08 0. " SAMP_EN_0_OETR ,Sampler 0" "Disabled,Enabled"
line.long 0x0c "CFGRX4,PHY Configuration Receive 4 Register"
bitfld.long 0x0c 28.--29. " RCLK_SAMP ,RCLK_SAMP[1:0]" "0,1,2,3"
bitfld.long 0x0c 26.--27. " RCLK_DIG ,RCLK_DIG[1:0]" "0,1,2,3"
textline " "
bitfld.long 0x0c 24. " DCD_EN_BUF ,DCD_EN_BUF" "Disabled,Enabled"
bitfld.long 0x0c 23. " DCD_EN_CLK ,DCD_EN_CLK" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 22. " DCD_EN_M ,DCD_EN_M" "Disabled,Enabled"
bitfld.long 0x0c 21. " DCD_EN_P ,DCD_EN_P" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 19. " PI_VCM_Z_0 ,PI_VCM_Z[0]" "Low,High"
bitfld.long 0x0c 18. " PI_VCM_1 ,PI_VCM[1]" "Low,High"
textline " "
bitfld.long 0x0c 17. " PI_VCM_Z_2 ,PI_VCM_Z[2]" "Low,High"
bitfld.long 0x0c 16. " PI_VCM_Z_3 ,PI_VCM_Z[3]" "Low,High"
textline " "
bitfld.long 0x0c 15. " PI_BIAS_DISABLE ,PI_BIAS_DISABLE" "No,Yes"
bitfld.long 0x0c 14. " PI_ED_CAL_LEVEL_DEC ,PI_ED_CAL_LEVEL_DEC" "Low,High"
textline " "
bitfld.long 0x0c 13. " PI_ED_CAL_LEVEL_INC ,PI_ED_CAL_LEVEL_INC" "Low,High"
bitfld.long 0x0c 12. " PI_ED_CAL ,PI_ED_CAL" "Low,High"
textline " "
bitfld.long 0x0c 11. " PI_ED_RESET ,PI_ED_RESET" "Low,High"
bitfld.long 0x0c 10. " PI_ED_EN ,PI_ED_EN" "Disabled,Enabled"
textline " "
bitfld.long 0x0c 9. " PI_ED_VOUTP ,PI_ED_VOUTP" "Low,High"
bitfld.long 0x0c 8. " PI_ED_VOUTM ,PI_ED_VOUTM" "Low,High"
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bitfld.long 0x0c 7. " PI_I50U ,PI_I50U" "Low,High"
bitfld.long 0x0c 6. " PI_I100U_Z ,PI_I100U_Z" "Low,High"
textline " "
bitfld.long 0x0c 0.--5. " PI_IBIAS_Z ,PI_IBIAS_Z[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "PHY_STSRX,Receive Bus PHY-to-Controller Status Register"
bitfld.long 0x10 11.--15. " RX_RTRIM ,Trim bits for RX resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x10 10. " RX_CALOUT_D ,CalOut after the digital filter" "Low,High"
textline " "
bitfld.long 0x10 9. " RX_CALOUT_A ,CalOut coming from analog" "Low,High"
bitfld.long 0x10 6. " OCIP ,Offset Compensation in Progres. Driven high asynchronously during offset compensation" "Not in progres,In progres"
textline " "
bitfld.long 0x10 5. " BSRXN ,Boundary scan data" "Low,High"
bitfld.long 0x10 4. " BSRXP ,Boundary scan data" "Low,High"
textline " "
bitfld.long 0x10 3. " LOSDTCT ,Loss of Signal detect" "Not detected,Detected"
bitfld.long 0x10 2. " ODDCG ,Odd code group" "Not odd,Odd"
textline " "
bitfld.long 0x10 1. " SYNC ,Symbol alignment" "No alignment,Alignment"
bitfld.long 0x10 0. " TESTFAIL ,Test failure" "Not failed,Failed"
line.long 0x14 "CFGTX0,PHY Configuration Transmit 0 Register"
bitfld.long 0x14 28.--29. " CAL_FILTER_DEPTH ,Average engine depth (for calibration)" "7 samples,15 samples,31 samples,7 samples"
bitfld.long 0x14 25.--26. " DET_CTL ,Receiver detect control" "0,1,2,3"
textline " "
bitfld.long 0x14 24. " ENIDL ,Value of ENIDL field" "Normal,Idle"
bitfld.long 0x14 21. " TM_EXTRA_LOAD[2] ,Enable different extraload resistors to make driver constant current at speed" "Disabled,Enabled"
textline " "
bitfld.long 0x14 20. " TM_EXTRA_LOAD[1] ,Enable static dummy load during electrical idle" "Disabled,Enabled"
bitfld.long 0x14 19. " TM_EXTRA_LOAD[0] ,Enable switching dummy load during electrical idle" "Disabled,Enabled"
textline " "
bitfld.long 0x14 13.--17. " DEEMP ,Selects one of output de-emphasis settings (PCIE/eSATA full rate/eSata half rate)" "0/0/0,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,33.7/10/10,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved,50.2/25/Reserved"
bitfld.long 0x14 9.--12. " SWING ,TX Output swing selection" "148 (half),148 (half),258 (half),258 (half),295 (full/half),295 (full/half),516 (full/half),516 (full/half),774 (full/half),774 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half),1069 (full/half)"
textline " "
bitfld.long 0x14 7. " INVPAIR ,Inverts polarity of TXPi and TXNi" "Not inverted,Inverted"
bitfld.long 0x14 5.--6. " RATE ,Value of the phy's RATE field" "0,1,2,3"
textline " "
bitfld.long 0x14 2.--4. " BUSWIDTH ,Selects the parallel interface width" "10-bit operation,?..."
bitfld.long 0x14 1. " ENTXLDO ,Enables TX Analog LDO" "Disabled,Enabled"
textline " "
bitfld.long 0x14 0. " ENTX ,Value of the ENTX of the phy" "Reset/slumber,Enabled"
line.long 0x18 "CFGTX1,PHY Configuration Transmit 1 Register"
bitfld.long 0x18 28.--31. " TRIM_HIGH_THRESHOLD ,4-b programmable threshold (for calibration)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 27. " TX_DISABLE_ON_THE_FLY ,Disables the pattern match (for calibration)" "No,Yes"
textline " "
bitfld.long 0x18 26. " TX_FORCE_UPDATE ,Forces the update to be made to the Analog trim bits without looking for any specific data pattern or electrical idle (for calibration)" "Disabled,Enabled"
bitfld.long 0x18 25. " TX_TRIM_BYPASS ,Bypasses the trim bits generated from the calibration algorithm (for calibration)" "Disabled,Enabled"
textline " "
bitfld.long 0x18 24. " TRIM_2B_MODE ,Enables 2-b data pattern detection mode for trim updates (for calibration)" "Disabled,Enabled"
bitfld.long 0x18 21.--22. " TRIM_STEP_CHANGE ,Step change value for staircase logic (for calibration)" "1,2,4,8"
textline " "
bitfld.long 0x18 19.--20. " TRIM_LOW_THRESHOLD ,2-b programmable threshold (for calibration)" "Diff >= 1,Diff >= 2,Diff >= 3,Diff >= 4"
bitfld.long 0x18 17.--18. " CALIB_WAIT_CYCLES ,2-b programmable number of wait cycles before polling the calout signal (for calibration)" "1 MHz clock,1 MHz clock,1 MHz clock,1 MHz clock"
textline " "
bitfld.long 0x18 16. " ENABLE_LOOP_DELAY ,Enables the additional loop delay of 40 clock cycles before sweeping the trim code during the calibration (for calibration)" "Disabled,Enabled"
bitfld.long 0x18 15. " BYPASS_CALOUT_AVG ,Bypasses the averaging filter for the callout signal inside digital (for calibration)" "Not bypassed,Bypassed"
textline " "
bitfld.long 0x18 13. " ENBSPLS ,Value of the serdes_bscan_ctrl_p0_enbspt input" "Low,High"
bitfld.long 0x18 12. " ENBSRX ,Value of the serdes_bscan_ctrl_p0_enbsrx input" "Low,High"
textline " "
bitfld.long 0x18 11. " ENBSTX ,Value of the serdes_bscan_ctrl_p0_enbstx input" "Low,High"
bitfld.long 0x18 10. " BSINITCLK ,Value of the serdes_bscan_clk_p0_bsinitclk input" "Low,High"
textline " "
bitfld.long 0x18 9. " BSINRXN ,Value of the serdes_bscan_p0_bsinrxn input" "Low,High"
bitfld.long 0x18 8. " BSINRXP ,Value of the serdes_bscan_p0_bsinrxp input" "Low,High"
textline " "
bitfld.long 0x18 7. " TSYNC_ENABLE ,Tsync Enable" "Disabled,Enabled"
bitfld.long 0x18 6. " ENTEST ,Value of the serdes_testpatt_p0_entesttx input" "Low,High"
textline " "
bitfld.long 0x18 5. " BSTX ,Value of the serdes_bscan_p0_bstx input" "Low,High"
bitfld.long 0x18 1. " USE_STAIRCASE ,Staircase logic for trim code change (for calibration)" "Disabled,Enabled"
line.long 0x1c "CFGTX2,PHY Configuration Transmit 2 Register"
bitfld.long 0x1c 29.--30. " TM_DUMMY2IDLE ,Control ldo dummy digital load" "Disabled,1.5 mA,1.5 mA,3 mA"
bitfld.long 0x1c 27.--28. " TM_DUMMY1IDLE ,Control ldo dummy resistor load" "Disabled,6 mA,9.6 mA,15 mA"
textline " "
bitfld.long 0x1c 25.--26. " TM_TEXTRALOAD ,Driver dummy current controlled by tx_extraload" "Disabled,1 mA,2 mA,3 mA"
bitfld.long 0x1c 23. " DISABLE_FB1_TM_SRCONTROL ,DISABLE_FB1_TM_SRCONTROL" "No,Yes"
textline " "
bitfld.long 0x1c 21.--22. " SC_SATA ,Control for SATA slew-control" "0,1,2,3"
bitfld.long 0x1c 19.--20. " SC_PCIE ,Control for PCIe slew-control" "0,1,2,3"
textline " "
bitfld.long 0x1c 18. " DISABLE_PCIE_SC ,Output divider slew-rate control for PCIe mode" "No,Yes"
bitfld.long 0x1c 17. " DISABLE_SATA_SC ,Output driver slew-rate control for SATA mode" "No,Yes"
textline " "
bitfld.long 0x1c 14. " TXDCC_PWRDN ,TX clock will duty-cycle correction" "Disabled,Enabled"
bitfld.long 0x1c 4.--8. " TMTRIM ,Termination resistor calibration code for grounded resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x1c 3. " TRIMBYPASS ,Digital control of termination resistor" "Not bypassed,Bypassed"
bitfld.long 0x1c 1.--2. " RDTCT_VTMODE ,Receive detect test mode to program threshold" ".285V,0.3V,.27V,0.35V"
line.long 0x20 "CFGTX3,PHY Configuration Transmit 3 Register"
bitfld.long 0x20 24.--27. " RXLDO_CTRL[15:13] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 23. " RXLDO_CTRL[12] ,Force LDO UP signal high" "Not forced,Forced"
textline " "
bitfld.long 0x20 22. " RXLDO_CTRL[11] ,Low dropout mode" "Disabled,Enabled"
bitfld.long 0x20 21. " RXLDO_CTRL[10] ,Vref magnitude selection" "Not selected,Selected"
textline " "
bitfld.long 0x20 20. " RXLDO_CTRL[9] ,Iref magnitude selection" "Not selected,Selected"
bitfld.long 0x20 18.--19. " RXLDO_CTRL[8:7] ,Quiescent current programmability" "0,1,2,3"
textline " "
bitfld.long 0x20 17. " RXLDO_CTRL[6] ,Overshoot control block" "Disabled,Enabled"
bitfld.long 0x20 12.--16. " RXLDO_CTRL[5:0] ,Trim setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x20 11. " RXLDO_HITRAN_UNUSED ,RX LDO transient improvement" "Low,High"
bitfld.long 0x20 7.--10. " TXLDO_CTRL[9:6] ,LDO loop compensation control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
bitfld.long 0x20 6. " TXLDO_CTRL[5] ,Force LDO UP signal high" "Not forced,Forced"
bitfld.long 0x20 5. " TXLDO_CTRL[4] ,Low dropout mode" "Disabled,Enabled"
textline " "
bitfld.long 0x20 4. " TXLDO_CTRL[3] ,Vref magnitude selection" "Not selected,Selected"
bitfld.long 0x20 3. " TXLDO_CTRL[2] ,Iref magnitude selection" "Not selected,Selected"
textline " "
bitfld.long 0x20 1.--2. " TXLDO_CTRL[1:0] ,Quiescent current programmability" "0,1,2,3"
bitfld.long 0x20 0. " TXLDO_DISABLE_OVERSHOOT ,TX LDO disable overshoot control" "No,Yes"
line.long 0x24 "CFGTX4,PHY Configuration Transmit 4 Register"
bitfld.long 0x24 4. " TM_BIASCTR ,TM_BIASCTR used in DCC" "Disabled,Enabled"
bitfld.long 0x24 1.--3. " TRIM_MODE ,TRIM_MODE[2:0]" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x24 0. " HYST_DISABLE ,HYST_DISABLE_Z and CALOUT_TX" "No,Yes"
line.long 0x28 "STSRX_PHY,Transmit Bus Controller-to-PHY Status Register"
bitfld.long 0x28 9. " TX_CALOUT_D ,CalOut after the digital filter" "Low,High"
bitfld.long 0x28 8. " TX_CALOUT_A ,CalOut coming from analog" "Low,High"
textline " "
bitfld.long 0x28 3.--7. " TX_RTRIM ,Trim bits for TX resistor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 1. " RDTCTIP ,Receiver detect in progress" "Not in progress,In progress"
textline " "
bitfld.long 0x28 0. " TESTFAIL ,Test failure" "Not failed,Failed"
endif
width 0xb
tree.end
tree.open "Timers"
tree "TIMER1"
base ad:0x4802E000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER2"
base ad:0x48040000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER3"
base ad:0x48042000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER4"
base ad:0x48044000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER5"
base ad:0x48046000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER6"
base ad:0x48048000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree "TIMER7"
base ad:0x4804A000
width 15.
group.long 0x00++0x03
line.long 0x00 "TIDR,Identification Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL Version " "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major Revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Indicates a special version for a particular device" "0,1,2,3"
hexmask.long.byte 0x00 0.--5. 1. " Y_MINOR ,Minor Revision"
group.long 0x10++0x03
line.long 0x00 "TIOCP_CFG,Timer OCP Configuration Register"
bitfld.long 0x00 2.--3. " IDLEMODE ,Power management" "Forced-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
bitfld.long 0x00 1. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
bitfld.long 0x00 0. " SOFTRESET ,Software reset" "No reset,Reset"
group.long 0x20++0x03
line.long 0x00 "IRQ_EOI,Timer IRQ End-Of-Interrupt Register"
sif (cpuis("AM335*"))
bitfld.long 0x00 0. " DMAEVENT_ACK ,DMA event completion acknowledge" "Acknowledged,No effect"
else
bitfld.long 0x00 0. " LINE_NUMBER ,Number of interrupt line to apply a SW EOI" "0,No effect"
endif
group.long 0x24++0x03
line.long 0x00 "IRQSTATUS_RAW,Timer IRQSTATUS Raw Register"
bitfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ raw status for Capture" "No interrupt,Interrupt"
bitfld.long 0x00 1. " OVF_IT_FLAG ,IRQ raw status for Overflow" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " MAT_IT_FLAG ,IRQ raw status for Match" "No interrupt,Interrupt"
group.long 0x28++0x03
line.long 0x00 "IRQSTATUS,Timer IRQSTATUS Register"
eventfld.long 0x00 2. " TCAR_IT_FLAG ,IRQ status for Capture" "No interrupt,Interrupt"
eventfld.long 0x00 1. " OVF_IT_FLAG ,IRQ status for Overflow" "No interrupt,Interrupt"
textline " "
eventfld.long 0x00 0. " MAT_IT_FLAG ,IRQ status for Match" "No interrupt,Interrupt"
group.long 0x2C++0x03
line.long 0x00 "IRQENABLE_SET,Timer IRQENABLE Set Register"
bitfld.long 0x00 2. " TCAR_EN_FLAG ,IRQ enable for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_EN_FLAG ,IRQ enable for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_EN_FLAG ,IRQ enable for Match" "Disabled,Enabled"
group.long 0x30++0x03
line.long 0x00 "IRQENABLE_CLR,Timer IRQENABLE Clear Register"
eventfld.long 0x00 2. " TCAR_DIS_FLAG ,IRQ disable for Compare" "Disabled,Enabled"
eventfld.long 0x00 1. " OVF_DIS_FLAG ,IRQ disable for Overflow" "Disabled,Enabled"
textline " "
eventfld.long 0x00 0. " MAT_DIS_FLAG ,IRQ disable for Match" "Disabled,Enabled"
group.long 0x34++0x03
line.long 0x00 "IRQWAKEEN,Timer IRQ Wakeup Enable Register"
bitfld.long 0x00 2. " TCAR_WUP_ENA ,Wakeup generation for Compare" "Disabled,Enabled"
bitfld.long 0x00 1. " OVF_WUP_ENA ,Wakeup generation for Overflow" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " MAT_WUP_ENA ,Wakeup generation for Match" "Disabled,Enabled"
group.long 0x38++0x03
line.long 0x00 "TCLR,Timer Control Register"
bitfld.long 0x00 14. " GPO_CFG ,General Purpose Output" "0,1"
bitfld.long 0x00 13. " CAPT_MODE ,Capture mode select" "Single,On second event"
textline " "
bitfld.long 0x00 12. " PT ,Pulse or toggle mode on PORTIMERPWM output pin" "Pulse,Toggle"
bitfld.long 0x00 10.--11. " TRG ,Trigger output mode on PORTIMERPWM output pin" "No trigger,On overflow,On overflow and match,?..."
textline " "
bitfld.long 0x00 8.--9. " TCM ,Transition Capture Mode on PIEVENTCAPT input pin" "No capture,On low to high,On high to low,On both"
bitfld.long 0x00 7. " SCPWM ,PORTIMERPWM output pin and pulse mode select" "Cleared/Positive,Set/Negative"
textline " "
bitfld.long 0x00 6. " CE ,Compare enable" "Disabled,Enabled"
bitfld.long 0x00 5. " PRE ,Prescaler enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 2.--4. " PTV ,Pre-scale clock Timer Value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 1. " AR ,Auto-reload mode" "One shot,Auto-reload"
textline " "
bitfld.long 0x00 0. " ST ,Start/Stop timer control" "Stopped,Started"
group.long 0x3C++0x03
line.long 0x00 "TCRR,Timer Counter Register"
group.long 0x40++0x03
line.long 0x00 "TLDR,Timer Load Register"
rgroup.long 0x44++0x03
line.long 0x00 "TTGR,Timer Trigger Register"
group.long 0x48++0x03
line.long 0x00 "TWPS,Timer Write Posted Status Register"
bitfld.long 0x00 4. " W_PEND_TMAR ,Write pending for TMAR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_TTGR ,Write pending for TTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_TLDR ,Write pending for TLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_TCRR ,Write pending for TCRR" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " W_PEND_TCLR ,Write pending for TCLR" "Not pending,Pending"
group.long 0x4C++0x03
line.long 0x00 "TMAR,Timer Match Register"
group.long 0x50++0x03
line.long 0x00 "TCAR1,Timer Capture Register 1"
group.long 0x54++0x03
line.long 0x00 "TSICR,Timer Synchronous Interface Control Register "
bitfld.long 0x00 2. " POSTED ,Posted mode" "Inactive,Active"
textline " "
bitfld.long 0x00 1. " SFT ,Software reset" "Reset,No reset"
group.long 0x58++0x03
line.long 0x00 "TCAR2,Timer Capture Register 2"
width 0xb
tree.end
tree.end
tree "WDOG (Watchdog Timer)"
base ad:0x480C2000
width 17.
rgroup.long 0x0++0x3
line.long 0x00 "WDT_WIDR,IP revision identifier"
group.long 0x10++0x3
line.long 0x00 "WDT_WDSC,OCP interface parameters"
bitfld.long 0x00 5. " EMUFREE ,Emulation mode" "Frozen,Free-running"
textline " "
sif (cpuis("AM335*"))
bitfld.long 0x00 3.--4. " IDLEMODE ,Configuration of the local target state management mode" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup-capable"
textline " "
endif
bitfld.long 0x00 1. " SOFTRESET ,Software reset (Optional)" "Reset,No reset"
rgroup.long 0x14++0x3
line.long 0x00 "WDT_WDST,Status information"
bitfld.long 0x00 0. " RESETDONE ,Internal module reset monitoring" "Ongoing,Completed"
group.long 0x18++0x7
line.long 0x00 "WDT_WISR,Interrupt events pending"
eventfld.long 0x00 1. " DLY_IT_FLAG ,Pending delay interrupt status" "Not pending,Pending"
eventfld.long 0x00 0. " OVF_IT_FLAG ,Pending overflow interrupt status" "Not pending,Pending"
line.long 0x04 "WDT_WIER,Interrupt events control"
bitfld.long 0x04 1. " DLY_IT_ENA ,Delay interrupt enable/disable" "Disabled,Enabled"
bitfld.long 0x04 0. " OVF_IT_ENA ,Overflow interrupt enable/disable" "Disabled,Enabled"
sif (cpuis("DRA62*"))
group.long 0x20++0x3
line.long 0x00 "WDT_WWER,Wake-up events control"
bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled"
bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled"
endif
group.long 0x24++0x3
line.long 0x00 "WDT_WCLR,Counter prescaler control"
bitfld.long 0x00 5. " PRE ,Prescaler enable/disable configuration" "Disabled,Enabled"
bitfld.long 0x00 2.--4. " PTV ,Prescaler value" "0,1,2,3,4,5,6,7"
group.long 0x28++0xB
line.long 0x00 "WDT_WCRR,Internal counter value"
line.long 0x04 "WDT_WLDR,Timer load value"
line.long 0x08 "WDT_WTGR,Watchdog counter reload"
rgroup.long 0x34++0x3
line.long 0x00 "WDT_WWPS,Write posting bits"
bitfld.long 0x00 5. " W_PEND_WDLY ,Write pending for register WDLY" "Not pending,Pending"
bitfld.long 0x00 4. " W_PEND_WSPR ,Write pending for register WSPR" "Not pending,Pending"
bitfld.long 0x00 3. " W_PEND_WTGR ,Write pending for register WTGR" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " W_PEND_WLDR ,Write pending for register WLDR" "Not pending,Pending"
bitfld.long 0x00 1. " W_PEND_WCRR ,Write pending for register WCRR" "Not pending,Pending"
bitfld.long 0x00 0. " W_PEND_WCLR ,Write pending for register WCLR" "Not pending,Pending"
group.long 0x44++0x7
line.long 0x00 "WDT_WDLY,Event detection delay value"
line.long 0x04 "WDT_WSPR,Start-stop value"
group.long 0x54++0xF
line.long 0x00 "WDT_WIRQSTATRAW,IRQ unmasked status"
bitfld.long 0x00 1. " EVENT_DLY ,Settable raw status for delay event" "Not pending,Pending"
bitfld.long 0x00 0. " EVENT_OVF ,Settable raw status for overflow event" "Not pending,Pending"
line.long 0x04 "WDT_WIRQSTAT,IRQ masked status"
eventfld.long 0x04 1. " EVENT_DLY ,Clearable enabled status for delay event" "Not pending,Pending"
eventfld.long 0x04 0. " EVENT_OVF ,Clearable enabled status for overflow event" "Not pending,Pending"
line.long 0x08 "WDT_WIRQENSET,IRQ enable"
bitfld.long 0x08 1. " ENABLE_DLY ,Enable for delay event" "Disabled,Enabled"
bitfld.long 0x08 0. " ENABLE_OVF ,Enable for overflow event" "Disabled,Enabled"
line.long 0x0C "WDT_WIRQENCLR,IRQ enable clear"
eventfld.long 0x0C 1. " ENABLE_DLY ,Enable (Clear) for delay event" "Disabled,Enabled"
eventfld.long 0x0C 0. " ENABLE_OVF ,Enable (Clear) for overflow event" "Disabled,Enabled"
sif (cpuis("DRA62*"))
group.long 0x64++0x3
line.long 0x00 "WDT_WIRQWAKEEN,Wake-up events control"
bitfld.long 0x00 1. " DLY_WK_ENA ,Delay wake-up enable/disable" "Disabled,Enabled"
bitfld.long 0x00 0. " OVF_WK_ENA ,Overflow wake-up enable/disable" "Disabled,Enabled"
endif
width 0xb
tree.end
tree.open "UART (Universal Asynchronous Receiver/Transmitter)"
tree "UART 0"
base ad:0x48020000
width 15.
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
hgroup.word 0x00++0x01
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
in
else
group.word 0x00++0x01
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
endif
if ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
textline " "
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
hgroup.word 0x04++0x01
hide.word 0x00 "IER,Interrupt Enable Register"
else
group.word 0x04++0x01
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
endif
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
textline " "
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
hgroup.word 0x08++0x01
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
else
group.word 0x08++0x01
line.word 0x00 "EFR,Enhanced Feature Register"
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
endif
group.word 0x0C++0x01
line.word 0x00 "LCR,Line Control Register"
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
textline " "
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
textline " "
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
if (((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)
group.word 0x10++0x01
line.word 0x00 "MCR,Modem Control Register"
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
textline " "
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
textline " "
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
textline " "
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
else
group.word 0x10++0x01
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
textline " "
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
textline " "
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
textline " "
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
textline " "
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
textline " "
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
textline " "
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x7))
hgroup.word 0x14++0x01
hide.word 0x00 "LSR,Line Status Register"
else
group.word 0x14++0x01
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48020000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48020000+0x10)))&0x40)==0x0))
hgroup.word 0x18++0x01
hide.word 0x00 "MSR,Modem Status Register"
in
group.word 0x1C++0x01
line.word 0x00 "SPR,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
elif ((((d.w((ad:0x48020000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48020000+0x10)))&0x40)==0x0))
group.word 0x18++0x01
line.word 0x00 "XOFF1,XOFF1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
group.word 0x1c++0x01
line.word 0x00 "XOFF2,XOFF2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
else
group.word 0x18++0x01
line.word 0x00 "TCR,Transmission Control Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.word 0x1C++0x01
line.word 0x00 "TLR,Trigger Level Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
endif
if (((d.w((ad:0x48020000+0x20)))&0x7)==(0x4||0x5))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48020000+0x20)))&0x7)==0x1)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48020000+0x20)))&0x7)==0x6)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
elif (((d.w((ad:0x48020000+0x20)))&0x7)==(0x0||0x2||0x3))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
else
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
hgroup.word 0x24++0x01
hide.word 0x00 "MDR2,Mode Definition Register 2"
endif
rgroup.word 0x28++0x01
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
wgroup.word 0x28++0x01
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
rgroup.word 0x2c++0x01
line.word 0x00 "RESUME,Resume register"
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
wgroup.word 0x2c++0x01
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
rgroup.word 0x30++0x01
line.word 0x00 "SFREGL,Status FIFO Register Low"
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
wgroup.word 0x30++0x01
line.word 0x00 "RXFLL,Received Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
rgroup.word 0x34++0x01
line.word 0x00 "SFREGH,Status FIFO Register High"
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.word 0x34++0x01
line.word 0x00 "RXFLH,Received Frame Length High Register"
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
group.word 0x38++0x01
line.word 0x00 "BLR,BOF Control Register"
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
else
rgroup.word 0x38++0x01
line.word 0x00 "UASR,UART Autobauding Status Register"
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
textline " "
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
endif
if (((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)
group.word 0x3c++0x01
line.word 0x00 "ACREG,Auxiliary Control Register"
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
textline " "
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
textline " "
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
else
hgroup.word 0x3c++0x01
hide.word 0x00 "ACREG,Auxiliary Control Register"
endif
width 15.
group.word 0x40++0x01
line.word 0x00 "SCR,Supplementary Control Register"
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
textline " "
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
group.word 0x44++0x01
line.word 0x00 "SSR,Supplementary Status Register"
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
textline " "
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
width 15.
if ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
elif ((((d.w((ad:0x48020000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48020000+0x20)))&0x7)==0x6))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
else
hgroup.word 0x48++0x01
hide.word 0x00 "EBLR,BOF Length Register"
endif
rgroup.word 0x50++0x01
line.word 0x00 "MVR,Module Version Register"
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
group.word 0x54++0x01
line.word 0x00 "SYSC,System Configuration Register"
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
rgroup.word 0x58++0x01
line.word 0x00 "SYSS,System Status Register"
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.word 0x5c++0x01
line.word 0x00 "WER,Wake-Up Enable Register"
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
if (((d.w((ad:0x48020000+0x20)))&0x7)==0x6)
group.word 0x60++0x01
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
else
hgroup.word 0x60++0x01
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
endif
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.word 0x80++0x01
line.word 0x00 "MDR3,Mode Definition Register 3"
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
endif
sif (cpuis("AM335*"))
width 18.
group.word 0x84++0x01
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
endif
width 0xb
tree.end
tree "UART 1"
base ad:0x48022000
width 15.
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
hgroup.word 0x00++0x01
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
in
else
group.word 0x00++0x01
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
endif
if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
textline " "
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
hgroup.word 0x04++0x01
hide.word 0x00 "IER,Interrupt Enable Register"
else
group.word 0x04++0x01
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
endif
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
textline " "
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
hgroup.word 0x08++0x01
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
else
group.word 0x08++0x01
line.word 0x00 "EFR,Enhanced Feature Register"
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
endif
group.word 0x0C++0x01
line.word 0x00 "LCR,Line Control Register"
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
textline " "
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
textline " "
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
if (((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)
group.word 0x10++0x01
line.word 0x00 "MCR,Modem Control Register"
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
textline " "
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
textline " "
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
textline " "
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
else
group.word 0x10++0x01
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
textline " "
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
textline " "
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
textline " "
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
textline " "
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
textline " "
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
textline " "
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x7))
hgroup.word 0x14++0x01
hide.word 0x00 "LSR,Line Status Register"
else
group.word 0x14++0x01
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48022000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0))
hgroup.word 0x18++0x01
hide.word 0x00 "MSR,Modem Status Register"
in
group.word 0x1C++0x01
line.word 0x00 "SPR,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
elif ((((d.w((ad:0x48022000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48022000+0x10)))&0x40)==0x0))
group.word 0x18++0x01
line.word 0x00 "XOFF1,XOFF1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
group.word 0x1c++0x01
line.word 0x00 "XOFF2,XOFF2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
else
group.word 0x18++0x01
line.word 0x00 "TCR,Transmission Control Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.word 0x1C++0x01
line.word 0x00 "TLR,Trigger Level Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
endif
if (((d.w((ad:0x48022000+0x20)))&0x7)==(0x4||0x5))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x1)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48022000+0x20)))&0x7)==0x6)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
elif (((d.w((ad:0x48022000+0x20)))&0x7)==(0x0||0x2||0x3))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
else
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
hgroup.word 0x24++0x01
hide.word 0x00 "MDR2,Mode Definition Register 2"
endif
rgroup.word 0x28++0x01
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
wgroup.word 0x28++0x01
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
rgroup.word 0x2c++0x01
line.word 0x00 "RESUME,Resume register"
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
wgroup.word 0x2c++0x01
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
rgroup.word 0x30++0x01
line.word 0x00 "SFREGL,Status FIFO Register Low"
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
wgroup.word 0x30++0x01
line.word 0x00 "RXFLL,Received Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
rgroup.word 0x34++0x01
line.word 0x00 "SFREGH,Status FIFO Register High"
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.word 0x34++0x01
line.word 0x00 "RXFLH,Received Frame Length High Register"
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
group.word 0x38++0x01
line.word 0x00 "BLR,BOF Control Register"
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
else
rgroup.word 0x38++0x01
line.word 0x00 "UASR,UART Autobauding Status Register"
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
textline " "
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
endif
if (((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)
group.word 0x3c++0x01
line.word 0x00 "ACREG,Auxiliary Control Register"
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
textline " "
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
textline " "
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
else
hgroup.word 0x3c++0x01
hide.word 0x00 "ACREG,Auxiliary Control Register"
endif
width 15.
group.word 0x40++0x01
line.word 0x00 "SCR,Supplementary Control Register"
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
textline " "
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
group.word 0x44++0x01
line.word 0x00 "SSR,Supplementary Status Register"
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
textline " "
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
width 15.
if ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
elif ((((d.w((ad:0x48022000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48022000+0x20)))&0x7)==0x6))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
else
hgroup.word 0x48++0x01
hide.word 0x00 "EBLR,BOF Length Register"
endif
rgroup.word 0x50++0x01
line.word 0x00 "MVR,Module Version Register"
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
group.word 0x54++0x01
line.word 0x00 "SYSC,System Configuration Register"
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
rgroup.word 0x58++0x01
line.word 0x00 "SYSS,System Status Register"
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.word 0x5c++0x01
line.word 0x00 "WER,Wake-Up Enable Register"
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
if (((d.w((ad:0x48022000+0x20)))&0x7)==0x6)
group.word 0x60++0x01
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
else
hgroup.word 0x60++0x01
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
endif
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.word 0x80++0x01
line.word 0x00 "MDR3,Mode Definition Register 3"
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
endif
sif (cpuis("AM335*"))
width 18.
group.word 0x84++0x01
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
endif
width 0xb
tree.end
tree "UART 2"
base ad:0x48024000
width 15.
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
hgroup.word 0x00++0x01
hide.word 0x00 "RHR/THR,Receive/Transmit Holding Register"
in
else
group.word 0x00++0x01
line.word 0x00 "DLL,Divisor Latch LSB Value Register"
hexmask.word.byte 0x00 0.--7. 1. " CLOCK_LSB ,8-bit LSB divisor value"
endif
if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 07. " CTS_IT ,Enable /CTS interrupt" "Disabled,Enabled"
bitfld.word 0x00 06. " RTS_IT ,Enable /RTS interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
bitfld.word 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
textline " "
bitfld.word 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
bitfld.word 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
textline " "
bitfld.word 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
bitfld.word 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " STS_FIFO_TRIG_IT ,FIFO trigger level interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 2. " LAST_RX_BYTE_IT ,Last byte of frame in RX FIFO interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
group.word 0x04++0x01
line.word 0x00 "IER,Interrupt Enable Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,Transmit status interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 3. " RX_OVERRUN_IT ,RX overrun interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt and time-out interrupt enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
hgroup.word 0x04++0x01
hide.word 0x00 "IER,Interrupt Enable Register"
else
group.word 0x04++0x01
line.word 0x00 "DLH,Divisor Latch MSB Value Register"
hexmask.word.byte 0x00 0.--5. 1. " CLOCK_MSB ,6-bit MSB divisor value"
endif
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 6.--7. " FCR_MIRROR ,Mirror the contents of FCR[0] on both bits" "0,1,2,3"
bitfld.word 0x00 1.--5. " IT_TYPE ,Interrupt type" "Modem,THR,RHR,Receiver LSE,Reserved,Reserved,Rx timeout,Reserved,Xoff/special char,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CTS/RTS/DSR inactive,?..."
textline " "
bitfld.word 0x00 0. " IT_PENDING ,Interrupt pending" "Pending,Not pending"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 7. " EOF_IT ,Received EOF interrupt" "Inactive,Active"
bitfld.word 0x00 6. " LINE_STS_IT ,Receiver line status interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 4. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
bitfld.word 0x00 2. " RX_FIFO_LB_IT ,Last byte of frame in RX FIFO interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 1. " THR_IT ,THR interrupt" "Inactive,Active"
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
rgroup.word 0x08++0x01
line.word 0x00 "IIR,Interrupt Identification Register"
bitfld.word 0x00 5. " TX_STATUS_IT ,TX status interrupt" "Inactive,Active"
bitfld.word 0x00 3. " RX_OE_IT ,RX overrun interrupt" "Inactive,Active"
textline " "
bitfld.word 0x00 2. " RX_STOP_IT ,Receive stop interrupt" "Inactive,Active"
bitfld.word 0x00 1. " THR_IT ,THR interrupt enable" "Inactive,Active"
textline " "
bitfld.word 0x00 0. " RHR_IT ,RHR interrupt" "Inactive,Active"
wgroup.word 0x08++0x01
line.word 0x00 "FCR,FIFO Control Register"
bitfld.word 0x00 6.--7. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
bitfld.word 0x00 4.--5. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
textline " "
bitfld.word 0x00 3. " DMA_MODE ,DMA Mode" "Mode 0,Mode 1"
bitfld.word 0x00 2. " TX_FIFO_CLEAR ,Tx FIFO Clear" "No effect,Clear"
textline " "
bitfld.word 0x00 1. " RX_FIFO_CLEAR ,Rx FIFO Clear" "No effect,Clear"
bitfld.word 0x00 0. " FIFO_EN ,Tx/Rx FIFO Enable" "Disabled,Enabled"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
hgroup.word 0x08++0x01
hide.word 0x00 "IIR/FCR,Interrupt Identification/FIFO Control Register"
else
group.word 0x08++0x01
line.word 0x00 "EFR,Enhanced Feature Register"
bitfld.word 0x00 7. " AUTO_CTS_EN ,Auto-CTS flow control enable" "Disabled,Enabled"
bitfld.word 0x00 6. " AUTO_RTS_EN ,Auto-RTS flow control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " SPECIAL_CHAR_DETECT ,Special character detect enable" "Disabled,Enabled"
bitfld.word 0x00 4. " ENHANCED_EN ,Enhanced functions write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 2.--3. " TX_SW_FLOW_CONTROL ,Tx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
bitfld.word 0x00 0.--1. " RX_SW_FLOW_CONTROL ,Rx Software flow control selection" "No flow control,XON2/XOFF2,XON1/XOFF1,XON1/XON2/XOFF1/XOFF2"
endif
group.word 0x0C++0x01
line.word 0x00 "LCR,Line Control Register"
bitfld.word 0x00 7. " DIV_EN ,Divisor latch enable" "Disabled,Enabled"
bitfld.word 0x00 6. " BREAK_EN ,Break control enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " PARITY_TYPE2 ,Forced parity format select" "Odd/Even,Forced"
bitfld.word 0x00 4. " PARITY_TYPE1 ,Parity type" "Odd/1,Even/0"
textline " "
bitfld.word 0x00 3. " PARITY_EN ,Parity enable" "Disabled,Enabled"
bitfld.word 0x00 2. " NB_STOP ,Number of stop bits" "1,1.5/2"
textline " "
bitfld.word 0x00 0.--1. " CHAR_LENGTH ,Byte length" "5 bits,6 bits,7 bits,8 bits"
if (((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)
group.word 0x10++0x01
line.word 0x00 "MCR,Modem Control Register"
bitfld.word 0x00 6. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
bitfld.word 0x00 5. " XON_EN ,Enable XON any function" "Disabled,Enabled"
textline " "
bitfld.word 0x00 4. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
bitfld.word 0x00 3. " CD_STS_CH ,Force /DCD input" "High,Low"
textline " "
bitfld.word 0x00 2. " RI_STS_CH ,Force /RI input" "High,Low"
bitfld.word 0x00 1. " RTS ,Force /RTS output" "High,Low"
textline " "
bitfld.word 0x00 0. " DTR ,Force /DTR output" "High,Low"
else
group.word 0x10++0x01
line.word 0x00 "XON1_ADDR1,XON1/ADDR1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD1 ,XON1 character/ADDR1 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No error,Error"
bitfld.word 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
textline " "
bitfld.word 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
bitfld.word 0x00 04. " RX_BI ,Receive break" "No break,Break"
textline " "
bitfld.word 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
bitfld.word 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
textline " "
bitfld.word 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
bitfld.word 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 6. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 5. " RX_LAST_BYTE ,Receive last byte" "Not received,Received"
bitfld.word 0x00 4. " FRAME_TOO_LONG ,Frame too long" "No error,Error"
textline " "
bitfld.word 0x00 3. " ABORT ,Abort pattern received" "No abort,Abort"
bitfld.word 0x00 2. " CRC ,CRC error in the frame at the top of the STATUS FIFO" "No error,Error"
textline " "
bitfld.word 0x00 1. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
bitfld.word 0x00 0. " RX_FIFO_E ,RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
rgroup.word 0x14++0x01
line.word 0x00 "LSR,Line Status Register"
bitfld.word 0x00 7. " THR_EMPTY ,Transmit hold register empty" "Not empty,Empty"
bitfld.word 0x00 5. " RX_STOP ,Reception completed" "Not completed,Completed"
textline " "
bitfld.word 0x00 0. " RX_FIFO_E ,Receive RX FIFO empty" "Not empty,Empty"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x7))
hgroup.word 0x14++0x01
hide.word 0x00 "LSR,Line Status Register"
else
group.word 0x14++0x01
line.word 0x00 "XON2_ADDR2,XON2/ADDR2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XONWORD2 ,XON2 character/ADDR2 address (UART/IrDA modes)"
endif
if ((((d.w((ad:0x48024000+0x0c)))&0xff)!=0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0))
hgroup.word 0x18++0x01
hide.word 0x00 "MSR,Modem Status Register"
in
group.word 0x1C++0x01
line.word 0x00 "SPR,Scratchpad Register"
hexmask.word.byte 0x00 0.--7. 1. " SPR_WORD ,Scratchpad register"
elif ((((d.w((ad:0x48024000+0x0c)))&0xff)==0xbf)&&(((d.w((ad:0x48024000+0x10)))&0x40)==0x0))
group.word 0x18++0x01
line.word 0x00 "XOFF1,XOFF1 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD1 ,XOFF1 character (in UART modes)"
group.word 0x1c++0x01
line.word 0x00 "XOFF2,XOFF2 Register"
hexmask.word.byte 0x00 0.--7. 1. " XOFFWORD2 ,XOFF2 character (in UART modes)"
else
group.word 0x18++0x01
line.word 0x00 "TCR,Transmission Control Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_START ,Rx FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " RX_FIFO_TRIG_HALT ,Rx FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
group.word 0x1C++0x01
line.word 0x00 "TLR,Trigger Level Register"
bitfld.word 0x00 4.--7. " RX_FIFO_TRIG_DMA ,Rx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
bitfld.word 0x00 0.--3. " TX_FIFO_TRIG_DMA ,Tx FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
endif
if (((d.w((ad:0x48024000+0x20)))&0x7)==(0x4||0x5))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
bitfld.word 0x00 6. " SIP_MODE ,SIP mode" "Manual,Automatic"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x1)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 7. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
textline " "
bitfld.word 0x00 5. " SCT ,Store and control the transmission" "THR,ACREG[2]"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,IrDA sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 1.--2. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
bitfld.word 0x00 0. " IRTX_UNDERRUN ,IrDA transmission status interrupt" "No interrupt,Interrupt"
elif (((d.w((ad:0x48024000+0x20)))&0x7)==0x6)
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 4. " SET_TXIR ,Infrared transceiver configuration" "Low,High"
textline " "
bitfld.word 0x00 3. " IR_SLEEP ,CIR sleep mode enable" "Disabled,Enabled"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 7. " SETTXIRALT ,Alternate mode for SETTXIR" "Normal,Alternate"
bitfld.word 0x00 6. " IRRXINVERT ,No RX pin inversion performed" "Inversion,No inversion"
textline " "
bitfld.word 0x00 4.--5. " CIR_PULSE_MODE ,CIR pulse modulation definition" "3 from 12 cycles,4 from 12 cycles,5 from 12 cycles,6 from 12 cycles"
elif (((d.w((ad:0x48024000+0x20)))&0x7)==(0x0||0x2||0x3))
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
group.word 0x24++0x01
line.word 0x00 "MDR2,Mode Definition Register 2"
bitfld.word 0x00 3. " UART_PULSE ,UART mode with a pulse shaping" "Normal,Pulse"
else
group.word 0x20++0x01
line.word 0x00 "MDR1,Mode Definition Register 1"
bitfld.word 0x00 0.--2. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,CIR,Disabled"
hgroup.word 0x24++0x01
hide.word 0x00 "MDR2,Mode Definition Register 2"
endif
rgroup.word 0x28++0x01
line.word 0x00 "SFLSR,Status FIFO Line Status Register"
bitfld.word 0x00 4. " OE_ERROR ,Overrun error" "No error,Error"
bitfld.word 0x00 3. " FRAME_TOO_LONG_ERROR ,Frame-length too long error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ABORT_DETECT ,Abort pattern detect" "Not deteted,Detected"
bitfld.word 0x00 1. " CRC_ERROR ,CRC error" "No error,Error"
wgroup.word 0x28++0x01
line.word 0x00 "TXFLL,Transmit Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " TXFLL ,Frame length LSBs"
rgroup.word 0x2c++0x01
line.word 0x00 "RESUME,Resume register"
hexmask.word.byte 0x00 0.--7. 1. " RESUME ,Dummy read to restart the TX or RX"
wgroup.word 0x2c++0x01
line.word 0x00 "TXFLH,Transmit Frame Length High Register"
hexmask.word.byte 0x00 0.--4. 1. " TXFLH ,Frame length MSBs"
rgroup.word 0x30++0x01
line.word 0x00 "SFREGL,Status FIFO Register Low"
hexmask.word.byte 0x00 0.--7. 1. " SFREGL ,LSB part of the frame length"
wgroup.word 0x30++0x01
line.word 0x00 "RXFLL,Received Frame Length Low Register"
hexmask.word.byte 0x00 0.--7. 1. " RXFLL ,LSB part of the frame length in reception"
rgroup.word 0x34++0x01
line.word 0x00 "SFREGH,Status FIFO Register High"
bitfld.word 0x00 0.--3. " SFREGH ,MSB part of the frame length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
wgroup.word 0x34++0x01
line.word 0x00 "RXFLH,Received Frame Length High Register"
bitfld.word 0x00 0.--3. " RXFLH ,MSB part of the frame length in reception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
group.word 0x38++0x01
line.word 0x00 "BLR,BOF Control Register"
bitfld.word 0x00 7. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
bitfld.word 0x00 6. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
else
rgroup.word 0x38++0x01
line.word 0x00 "UASR,UART Autobauding Status Register"
bitfld.word 0x00 6.--7. " PARITY_TYPE ,Parity type" "No parity,Space,Even,Odd"
bitfld.word 0x00 5. " BIT_BY_CHAR ,Character identified" "7-bit,8-bit"
textline " "
bitfld.word 0x00 0.--4. " SPEED ,Speed identified" "Not identified,115 200 bauds,57 600 bauds,38 400 bauds,28 800 bauds,19 200 bauds,14 400 bauds,9 600 bauds,4 800 bauds,2 400 bauds,1 200 bauds,?..."
endif
if (((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)
group.word 0x3c++0x01
line.word 0x00 "ACREG,Auxiliary Control Register"
bitfld.word 0x00 7. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
bitfld.word 0x00 6. " SD_MOD ,Primary output used to configure transceivers" "High,Low"
textline " "
bitfld.word 0x00 5. " DIS_IR_RX ,RXIR input disable" "No,Yes"
bitfld.word 0x00 4. " DIS_TX_UNDERRUN ,TX underrun disable" "No,Yes"
textline " "
bitfld.word 0x00 3. " SEND_SIP ,Send serial infrared interaction pulse (MIR/FIR modes only)" "No action,Sent"
bitfld.word 0x00 2. " SCTX_EN ,Store and controlled Tx start enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " ABORT_EN ,Frame abort enable" "Disabled,Enabled"
bitfld.word 0x00 0. " EOT_EN ,End of transmission" "Not occurred,Occurred"
else
hgroup.word 0x3c++0x01
hide.word 0x00 "ACREG,Auxiliary Control Register"
endif
width 15.
group.word 0x40++0x01
line.word 0x00 "SCR,Supplementary Control Register"
bitfld.word 0x00 7. " RX_TRIG_GRANU1 ,RX level trigger granularity of 1 for trigger RX level enable" "Disabled,Enabled"
bitfld.word 0x00 6. " TX_TRIG_GRANU1 ,TX level trigger granularity of 1 for trigger TX level enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 5. " DSR_IT ,DSR interrupt enable" "Disabled,Enabled"
bitfld.word 0x00 4. " RX_CTS_WAKE_UP_ENABLE ,Wake-up on RX or CTS enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 3. " TX_EMPTY_CTL_IT ,THR interrupt mode" "Normal,Enabled"
bitfld.word 0x00 1.--2. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
textline " "
bitfld.word 0x00 0. " DMA_MODE_CTL ,DMA mode set" "FCR[3],SCR[2:1]"
group.word 0x44++0x01
line.word 0x00 "SSR,Supplementary Status Register"
bitfld.word 0x00 2. " DMA_COUNTER_RST ,DMA counter reset" "No reset,Reset"
bitfld.word 0x00 1. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX /CTS or /DSR" "Not occurred,Occurred"
textline " "
bitfld.word 0x00 0. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
width 15.
if ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==(0x1||0x4||0x5)))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of additional start flags"
elif ((((d.w((ad:0x48024000+0x0c)))&0x80)==0x00)&&(((d.w((ad:0x48024000+0x20)))&0x7)==0x6))
group.word 0x48++0x01
line.word 0x00 "EBLR,BOF Length Register"
hexmask.word.byte 0x00 0.--7. 1. " EBLR ,Number of consecutive zeros to be received before generating the RX_STOP interrupt"
else
hgroup.word 0x48++0x01
hide.word 0x00 "EBLR,BOF Length Register"
endif
rgroup.word 0x50++0x01
line.word 0x00 "MVR,Module Version Register"
hexmask.word.byte 0x00 4.--7. 1. " MAJOR_REV ,Major revision number"
hexmask.word.byte 0x00 0.--3. 1. " MINOR_REV ,Minor revision number"
group.word 0x54++0x01
line.word 0x00 "SYSC,System Configuration Register"
bitfld.word 0x00 3.--4. " IDLEMODE ,Power management request/acknowledge control" "Force idle,No idle,Smart idle,Smart idle Wakeup"
bitfld.word 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
textline " "
bitfld.word 0x00 1. " SOFTRESET ,Software reset" "No reset,Reset"
bitfld.word 0x00 0. " AUTOIDLE ,Internal OCP clock gating strategy" "Running,Applied"
rgroup.word 0x58++0x01
line.word 0x00 "SYSS,System Status Register"
bitfld.word 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Completed"
group.word 0x5c++0x01
line.word 0x00 "WER,Wake-Up Enable Register"
bitfld.word 0x00 7. " E7_TXWAKEUPEN ,Wake-up interrupt" "Not allowed,Allowed"
bitfld.word 0x00 6. " E6_RLS_INT ,Receiver line status interrupt allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 5. " E5_RHR_INT ,RHR interrupt allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 4. " E4_RX_INT ,RX activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 3. " E3_DCD_INT ,DCD activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 2. " E2_RI_INT ,RI activity allowed to wake up system" "Not allowed,Allowed"
textline " "
bitfld.word 0x00 1. " E1_DSR_INT ,DSR activity allowed to wake up system" "Not allowed,Allowed"
bitfld.word 0x00 0. " E0_CTS_INT ,CTS activity allowed to wake up system" "Not allowed,Allowed"
if (((d.w((ad:0x48024000+0x20)))&0x7)==0x6)
group.word 0x60++0x01
line.word 0x00 "CFPS,Carrier Frequency Prescaler"
hexmask.word.byte 0x00 0.--7. 1. " CFPS ,Carrier frequency prescaler"
else
hgroup.word 0x60++0x01
hide.word 0x00 "CFPS,Carrier Frequency Prescaler"
endif
sif (cpuis("DRA62*")||cpuis("AM335*")||(cpu()=="DM8147DSP")||(cpu()=="DM8148DSP"))
group.word 0x80++0x01
line.word 0x00 "MDR3,Mode Definition Register 3"
bitfld.word 0x00 2. " SET_DMA_TRESHOLD ,Set DMA treshold" "64-tx trigger,Different"
bitfld.word 0x00 1. " NONDEFAULT_REQ ,Non default req" "Default,Nondefault"
bitfld.word 0x00 0. " DISABLE_CIR_RX_DEMOD ,Disable CIR RX demodulation" "Enable,Disable"
endif
sif (cpuis("AM335*"))
width 18.
group.word 0x84++0x01
line.word 0x00 "TX_DMA_THRESHOLD,The TX DMA threshold register is selected with a register bit setting of LCR[7] = 0, LCR[7] not equal to BFh, or LCR[7] = BFh."
hexmask.word.byte 0x00 0.--5. 1. " TX_DMA_THRESHOLD ,Used to manually set the TX DMA threshold level"
endif
width 0xb
tree.end
tree.end
tree.open "USB (Universal Serial Bus)"
tree "USBSS"
base ad:0x47400000
width 12.
rgroup.long 0x00++0x03
line.long 0x00 "REVREG,Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Function indicates a software compatible module family"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "SYSCONFIG,SYSCONFIG Register"
sif cpuis("DM814?DSP")
bitfld.long 0x00 17. " USB1_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled"
bitfld.long 0x00 16. " USB0_D2_OCP_EN_N ,Active low clock enable for USB1_D2_OCP_CLK" "Enabled,Disabled"
textline " "
endif
bitfld.long 0x00 11. " USB0_OCP_CLK_EN ,Active low clock enable for usb0_ocp_clk" "Enabled,Disabled"
bitfld.long 0x00 10. " PHY0_UTMI_CLK_EN ,Active low clock enable for phy0_utmi_clk" "Enabled,Disabled"
textline " "
bitfld.long 0x00 9. " USB1_OCP_CLK_EN ,Active low clock enable for usb1_ocp_clk" "Enabled,Disabled"
bitfld.long 0x00 8. " PHY1_UTMI_CLK_EN ,Active low clock enable for phy1_utmi_clk" "Enabled,Disabled"
textline " "
sif (cpuis("DM814?DSP")||cpuis("AM335*")||cpuis("AM387*")||cpuis("DRA62*"))
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,No-standby,Smart-standby,Smart-standby wakeup capable"
bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Force-idle,No-idle,Smart-idle,Smart-idle wakeup capable"
else
bitfld.long 0x00 4.--5. " STANDBY_MODE ,Standby mode select" "Force-standby,Reserved,Smart-standby,Smart-standby wakeup capable"
bitfld.long 0x00 2.--3. " IDLEMODE ,Idlemode select" "Reserved,Reserved,Smart-standby,Smart-standby wakeup capable"
endif
textline " "
bitfld.long 0x00 1. " FREEEMU ,Sensitivity to emulation (debug) suspend input signal" "Sensitive,Not sensitive"
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USBSS USB0 and USB1 modules" "No reset,Reset"
sif (!cpuis("AM335*"))
group.long 0x20++0x3
line.long 0x00 "EOI,End of Interrupt Register"
bitfld.long 0x00 0. " EOI_VECTOR ,End of interrupt for USBSS Interrupt" "Completed,Not completed"
endif
group.long 0x24++0xf
line.long 0x00 "IRQSTATRAW,IRQ Status Raw Register"
bitfld.long 0x00 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
bitfld.long 0x00 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
bitfld.long 0x00 8. " TX_PKT_CMP_0 ,USB0 Tx CPPI DMA packet completion interrupt raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 2. " PD_CMP_FLAG ,Packet completed interrupt raw status" "No interrupt,Interrupt"
bitfld.long 0x00 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt raw status" "No interrupt,Interrupt"
textline " "
bitfld.long 0x00 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt raw status" "No interrupt,Interrupt"
line.long 0x04 "IRQSTAT,IRQ Status Register"
eventfld.long 0x04 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
eventfld.long 0x04 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x04 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
eventfld.long 0x04 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x04 2. " PD_CMP_FLAG ,Packet completed interrupt status" "No interrupt,Interrupt"
eventfld.long 0x04 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt status" "No interrupt,Interrupt"
textline " "
eventfld.long 0x04 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt status" "No interrupt,Interrupt"
line.long 0x08 "IRQENABLER,IRQ Enable Set Register"
bitfld.long 0x08 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
bitfld.long 0x08 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
bitfld.long 0x08 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt enable status" "Disabled,Enabled"
textline " "
bitfld.long 0x08 2. " PD_CMP_FLAG ,Packet completed interrupt enable status" "Disabled,Enabled"
bitfld.long 0x08 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt enable status" "Disabled,Enabled"
textline " "
bitfld.long 0x08 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt enable status" "Disabled,Enabled"
line.long 0x0c "IRQCLEARR,IRQ Enable Clear Register"
eventfld.long 0x0c 11. " RX_PKT_CMP_1 ,USB1 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
eventfld.long 0x0c 10. " TX_PKT_CMP_1 ,USB1 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
textline " "
eventfld.long 0x0c 9. " RX_PKT_CMP_0 ,USB0 Rx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
eventfld.long 0x0c 8. " TX_PKT_CMP_0 ,IUSB0 Tx CPPI DMA packet completion interrupt disable status" "Disabled,Enabled"
textline " "
eventfld.long 0x0c 2. " PD_CMP_FLAG ,Packet completed interrupt disable status" "Disabled,Enabled"
eventfld.long 0x0c 1. " RX_MOP_STARVATION ,Rx buffer cannot be allocated in the middle of packet interrupt disable status" "Disabled,Enabled"
textline " "
eventfld.long 0x0c 0. " RX_SOP_STARVATION ,Rx buffer cannot be allocated in the start of packet interrupt disable status" "Disabled,Enabled"
width 17.
tree "DMA Thresholds"
group.long 0x100++0x47
line.long (0x0+0x00) "IRQDMATHOLDTX00,IRQ DMA Threshold TX0 0 Register"
hexmask.long.byte (0x0+0x00) 24.--31. 1. " DMA_THRES_TX0_3 ,Threshold value for USB0 endpoint 3"
hexmask.long.byte (0x0+0x00) 16.--23. 1. " DMA_THRES_TX0_2 ,Threshold value for USB0 endpoint 2"
textline " "
hexmask.long.byte (0x0+0x00) 8.--15. 1. " DMA_THRES_TX0_1 ,Threshold value for USB0 endpoint 1"
line.long (0x0+0x04) "IRQDMATHOLDTX01,IRQ DMA Threshold TX0 1 Register"
hexmask.long.byte (0x0+0x04) 24.--31. 1. " DMA_THRES_TX0_7 ,Threshold value for USB0 endpoint 7"
hexmask.long.byte (0x0+0x04) 16.--23. 1. " DMA_THRES_TX0_6 ,Threshold value for USB0 endpoint 6"
textline " "
hexmask.long.byte (0x0+0x04) 8.--15. 1. " DMA_THRES_TX0_5 ,Threshold value for USB0 endpoint 5"
hexmask.long.byte (0x0+0x04) 0.--7. 1. " DMA_THRES_TX0_4 ,Threshold value for USB0 endpoint 4"
line.long (0x0+0x08) "IRQDMATHOLDTX02,IRQ DMA Threshold TX0 2 Register"
hexmask.long.byte (0x0+0x08) 24.--31. 1. " DMA_THRES_TX0_11 ,Threshold value for USB0 endpoint 11"
hexmask.long.byte (0x0+0x08) 16.--23. 1. " DMA_THRES_TX0_10 ,Threshold value for USB0 endpoint 10"
textline " "
hexmask.long.byte (0x0+0x08) 8.--15. 1. " DMA_THRES_TX0_9 ,Threshold value for USB0 endpoint 9"
hexmask.long.byte (0x0+0x08) 0.--7. 1. " DMA_THRES_TX0_8 ,Threshold value for USB0 endpoint 8"
line.long (0x0+0x0C) "IRQDMATHOLDTX03,IRQ DMA Threshold TX0 3 Register"
hexmask.long.byte (0x0+0x0C) 24.--31. 1. " DMA_THRES_TX0_15 ,Threshold value for USB0 endpoint 15"
hexmask.long.byte (0x0+0x0C) 16.--23. 1. " DMA_THRES_TX0_14 ,Threshold value for USB0 endpoint 14"
textline " "
hexmask.long.byte (0x0+0x0C) 8.--15. 1. " DMA_THRES_TX0_13 ,Threshold value for USB0 endpoint 13"
hexmask.long.byte (0x0+0x0C) 0.--7. 1. " DMA_THRES_TX0_12 ,Threshold value for USB0 endpoint 12"
line.long (0x10+0x00) "IRQDMATHOLDRX00,IRQ DMA Threshold RX0 0 Register"
hexmask.long.byte (0x10+0x00) 24.--31. 1. " DMA_THRES_RX0_3 ,Threshold value for USB0 endpoint 3"
hexmask.long.byte (0x10+0x00) 16.--23. 1. " DMA_THRES_RX0_2 ,Threshold value for USB0 endpoint 2"
textline " "
hexmask.long.byte (0x10+0x00) 8.--15. 1. " DMA_THRES_RX0_1 ,Threshold value for USB0 endpoint 1"
line.long (0x10+0x04) "IRQDMATHOLDRX01,IRQ DMA Threshold RX0 1 Register"
hexmask.long.byte (0x10+0x04) 24.--31. 1. " DMA_THRES_RX0_7 ,Threshold value for USB0 endpoint 7"
hexmask.long.byte (0x10+0x04) 16.--23. 1. " DMA_THRES_RX0_6 ,Threshold value for USB0 endpoint 6"
textline " "
hexmask.long.byte (0x10+0x04) 8.--15. 1. " DMA_THRES_RX0_5 ,Threshold value for USB0 endpoint 5"
hexmask.long.byte (0x10+0x04) 0.--7. 1. " DMA_THRES_RX0_4 ,Threshold value for USB0 endpoint 4"
line.long (0x10+0x08) "IRQDMATHOLDRX02,IRQ DMA Threshold RX0 2 Register"
hexmask.long.byte (0x10+0x08) 24.--31. 1. " DMA_THRES_RX0_11 ,Threshold value for USB0 endpoint 11"
hexmask.long.byte (0x10+0x08) 16.--23. 1. " DMA_THRES_RX0_10 ,Threshold value for USB0 endpoint 10"
textline " "
hexmask.long.byte (0x10+0x08) 8.--15. 1. " DMA_THRES_RX0_9 ,Threshold value for USB0 endpoint 9"
hexmask.long.byte (0x10+0x08) 0.--7. 1. " DMA_THRES_RX0_8 ,Threshold value for USB0 endpoint 8"
line.long (0x10+0x0C) "IRQDMATHOLDRX03,IRQ DMA Threshold RX0 3 Register"
hexmask.long.byte (0x10+0x0C) 24.--31. 1. " DMA_THRES_RX0_15 ,Threshold value for USB0 endpoint 15"
hexmask.long.byte (0x10+0x0C) 16.--23. 1. " DMA_THRES_RX0_14 ,Threshold value for USB0 endpoint 14"
textline " "
hexmask.long.byte (0x10+0x0C) 8.--15. 1. " DMA_THRES_RX0_13 ,Threshold value for USB0 endpoint 13"
hexmask.long.byte (0x10+0x0C) 0.--7. 1. " DMA_THRES_RX0_12 ,Threshold value for USB0 endpoint 12"
line.long (0x20+0x00) "IRQDMATHOLDTX10,IRQ DMA Threshold TX1 0 Register"
hexmask.long.byte (0x20+0x00) 24.--31. 1. " DMA_THRES_TX1_3 ,Threshold value for USB1 endpoint 3"
hexmask.long.byte (0x20+0x00) 16.--23. 1. " DMA_THRES_TX1_2 ,Threshold value for USB1 endpoint 2"
textline " "
hexmask.long.byte (0x20+0x00) 8.--15. 1. " DMA_THRES_TX1_1 ,Threshold value for USB1 endpoint 1"
line.long (0x20+0x04) "IRQDMATHOLDTX11,IRQ DMA Threshold TX1 1 Register"
hexmask.long.byte (0x20+0x04) 24.--31. 1. " DMA_THRES_TX1_7 ,Threshold value for USB1 endpoint 7"
hexmask.long.byte (0x20+0x04) 16.--23. 1. " DMA_THRES_TX1_6 ,Threshold value for USB1 endpoint 6"
textline " "
hexmask.long.byte (0x20+0x04) 8.--15. 1. " DMA_THRES_TX1_5 ,Threshold value for USB1 endpoint 5"
hexmask.long.byte (0x20+0x04) 0.--7. 1. " DMA_THRES_TX1_4 ,Threshold value for USB1 endpoint 4"
line.long (0x20+0x08) "IRQDMATHOLDTX12,IRQ DMA Threshold TX1 2 Register"
hexmask.long.byte (0x20+0x08) 24.--31. 1. " DMA_THRES_TX1_11 ,Threshold value for USB1 endpoint 11"
hexmask.long.byte (0x20+0x08) 16.--23. 1. " DMA_THRES_TX1_10 ,Threshold value for USB1 endpoint 10"
textline " "
hexmask.long.byte (0x20+0x08) 8.--15. 1. " DMA_THRES_TX1_9 ,Threshold value for USB1 endpoint 9"
hexmask.long.byte (0x20+0x08) 0.--7. 1. " DMA_THRES_TX1_8 ,Threshold value for USB1 endpoint 8"
line.long (0x20+0x0C) "IRQDMATHOLDTX13,IRQ DMA Threshold TX1 3 Register"
hexmask.long.byte (0x20+0x0C) 24.--31. 1. " DMA_THRES_TX1_15 ,Threshold value for USB1 endpoint 15"
hexmask.long.byte (0x20+0x0C) 16.--23. 1. " DMA_THRES_TX1_14 ,Threshold value for USB1 endpoint 14"
textline " "
hexmask.long.byte (0x20+0x0C) 8.--15. 1. " DMA_THRES_TX1_13 ,Threshold value for USB1 endpoint 13"
hexmask.long.byte (0x20+0x0C) 0.--7. 1. " DMA_THRES_TX1_12 ,Threshold value for USB1 endpoint 12"
line.long (0x30+0x00) "IRQDMATHOLDRX10,IRQ DMA Threshold RX1 0 Register"
hexmask.long.byte (0x30+0x00) 24.--31. 1. " DMA_THRES_RX1_3 ,Threshold value for USB1 endpoint 3"
hexmask.long.byte (0x30+0x00) 16.--23. 1. " DMA_THRES_RX1_2 ,Threshold value for USB1 endpoint 2"
textline " "
hexmask.long.byte (0x30+0x00) 8.--15. 1. " DMA_THRES_RX1_1 ,Threshold value for USB1 endpoint 1"
line.long (0x30+0x04) "IRQDMATHOLDRX11,IRQ DMA Threshold RX1 1 Register"
hexmask.long.byte (0x30+0x04) 24.--31. 1. " DMA_THRES_RX1_7 ,Threshold value for USB1 endpoint 7"
hexmask.long.byte (0x30+0x04) 16.--23. 1. " DMA_THRES_RX1_6 ,Threshold value for USB1 endpoint 6"
textline " "
hexmask.long.byte (0x30+0x04) 8.--15. 1. " DMA_THRES_RX1_5 ,Threshold value for USB1 endpoint 5"
hexmask.long.byte (0x30+0x04) 0.--7. 1. " DMA_THRES_RX1_4 ,Threshold value for USB1 endpoint 4"
line.long (0x30+0x08) "IRQDMATHOLDRX12,IRQ DMA Threshold RX1 2 Register"
hexmask.long.byte (0x30+0x08) 24.--31. 1. " DMA_THRES_RX1_11 ,Threshold value for USB1 endpoint 11"
hexmask.long.byte (0x30+0x08) 16.--23. 1. " DMA_THRES_RX1_10 ,Threshold value for USB1 endpoint 10"
textline " "
hexmask.long.byte (0x30+0x08) 8.--15. 1. " DMA_THRES_RX1_9 ,Threshold value for USB1 endpoint 9"
hexmask.long.byte (0x30+0x08) 0.--7. 1. " DMA_THRES_RX1_8 ,Threshold value for USB1 endpoint 8"
line.long (0x30+0x0C) "IRQDMATHOLDRX13,IRQ DMA Threshold RX1 3 Register"
hexmask.long.byte (0x30+0x0C) 24.--31. 1. " DMA_THRES_RX1_15 ,Threshold value for USB1 endpoint 15"
hexmask.long.byte (0x30+0x0C) 16.--23. 1. " DMA_THRES_RX1_14 ,Threshold value for USB1 endpoint 14"
textline " "
hexmask.long.byte (0x30+0x0C) 8.--15. 1. " DMA_THRES_RX1_13 ,Threshold value for USB1 endpoint 13"
hexmask.long.byte (0x30+0x0C) 0.--7. 1. " DMA_THRES_RX1_12 ,Threshold value for USB1 endpoint 12"
line.long 0x40 "IRQDMAENABLE0,IRQ DMA Enable 0 Register"
bitfld.long 0x40 31. " DMA_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x40 30. " DMA_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
bitfld.long 0x40 29. " DMA_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x40 28. " DMA_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
bitfld.long 0x40 27. " DMA_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
bitfld.long 0x40 26. " DMA_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x40 25. " DMA_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
bitfld.long 0x40 24. " DMA_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
bitfld.long 0x40 23. " DMA_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x40 22. " DMA_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
bitfld.long 0x40 21. " DMA_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
bitfld.long 0x40 20. " DMA_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x40 19. " DMA_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
bitfld.long 0x40 18. " DMA_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x40 17. " DMA_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
textline " "
bitfld.long 0x40 15. " DMA_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x40 14. " DMA_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
bitfld.long 0x40 13. " DMA_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x40 12. " DMA_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
bitfld.long 0x40 11. " DMA_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
bitfld.long 0x40 10. " DMA_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x40 9. " DMA_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
bitfld.long 0x40 8. " DMA_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
bitfld.long 0x40 7. " DMA_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x40 6. " DMA_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
bitfld.long 0x40 5. " DMA_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
bitfld.long 0x40 4. " DMA_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x40 3. " DMA_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
endif
bitfld.long 0x40 2. " DMA_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
sif (cpuis("AM335*"))
bitfld.long 0x40 0. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
else
bitfld.long 0x40 1. " DMA_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
endif
line.long 0x44 "IRQDMAENABLE1,IRQ DMA Enable 1 Register"
bitfld.long 0x44 31. " DMA_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x44 30. " DMA_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
bitfld.long 0x44 29. " DMA_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x44 28. " DMA_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
bitfld.long 0x44 27. " DMA_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
bitfld.long 0x44 26. " DMA_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x44 25. " DMA_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
bitfld.long 0x44 24. " DMA_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
bitfld.long 0x44 23. " DMA_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x44 22. " DMA_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
bitfld.long 0x44 21. " DMA_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
bitfld.long 0x44 20. " DMA_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x44 19. " DMA_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
bitfld.long 0x44 18. " DMA_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x44 17. " DMA_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
textline " "
bitfld.long 0x44 15. " DMA_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x44 14. " DMA_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
bitfld.long 0x44 13. " DMA_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x44 12. " DMA_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
bitfld.long 0x44 11. " DMA_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
bitfld.long 0x44 10. " DMA_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x44 9. " DMA_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
bitfld.long 0x44 8. " DMA_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
bitfld.long 0x44 7. " DMA_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x44 6. " DMA_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
bitfld.long 0x44 5. " DMA_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
bitfld.long 0x44 4. " DMA_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x44 3. " DMA_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
bitfld.long 0x44 2. " DMA_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x44 1. " DMA_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
tree.end
tree "FRAME Thresholds"
group.long 0x200++0x47
line.long (0x0+0x00) "IRQFRAMETHOLDTX00,IRQ FRAME Threshold TX0 0 Register"
hexmask.long.byte (0x0+0x00) 24.--31. 1. " FRAME_THRES_TX0_3 ,Threshold value for USB0 endpoint 3"
hexmask.long.byte (0x0+0x00) 16.--23. 1. " FRAME_THRES_TX0_2 ,Threshold value for USB0 endpoint 2"
textline " "
hexmask.long.byte (0x0+0x00) 8.--15. 1. " FRAME_THRES_TX0_1 ,Threshold value for USB0 endpoint 1"
line.long (0x0+0x04) "IRQFRAMETHOLDTX01,IRQ FRAME Threshold TX0 1 Register"
hexmask.long.byte (0x0+0x04) 24.--31. 1. " FRAME_THRES_TX0_7 ,Threshold value for USB0 endpoint 7"
hexmask.long.byte (0x0+0x04) 16.--23. 1. " FRAME_THRES_TX0_6 ,Threshold value for USB0 endpoint 6"
textline " "
hexmask.long.byte (0x0+0x04) 8.--15. 1. " FRAME_THRES_TX0_5 ,Threshold value for USB0 endpoint 5"
hexmask.long.byte (0x0+0x04) 0.--7. 1. " FRAME_THRES_TX0_4 ,Threshold value for USB0 endpoint 4"
line.long (0x0+0x08) "IRQFRAMETHOLDTX02,IRQ FRAME Threshold TX0 2 Register"
hexmask.long.byte (0x0+0x08) 24.--31. 1. " FRAME_THRES_TX0_11 ,Threshold value for USB0 endpoint 11"
hexmask.long.byte (0x0+0x08) 16.--23. 1. " FRAME_THRES_TX0_10 ,Threshold value for USB0 endpoint 10"
textline " "
hexmask.long.byte (0x0+0x08) 8.--15. 1. " FRAME_THRES_TX0_9 ,Threshold value for USB0 endpoint 9"
hexmask.long.byte (0x0+0x08) 0.--7. 1. " FRAME_THRES_TX0_8 ,Threshold value for USB0 endpoint 8"
line.long (0x0+0x0C) "IRQFRAMETHOLDTX03,IRQ FRAME Threshold TX0 3 Register"
hexmask.long.byte (0x0+0x0C) 24.--31. 1. " FRAME_THRES_TX0_15 ,Threshold value for USB0 endpoint 15"
hexmask.long.byte (0x0+0x0C) 16.--23. 1. " FRAME_THRES_TX0_14 ,Threshold value for USB0 endpoint 14"
textline " "
hexmask.long.byte (0x0+0x0C) 8.--15. 1. " FRAME_THRES_TX0_13 ,Threshold value for USB0 endpoint 13"
hexmask.long.byte (0x0+0x0C) 0.--7. 1. " FRAME_THRES_TX0_12 ,Threshold value for USB0 endpoint 12"
line.long (0x10+0x00) "IRQFRAMETHOLDRX00,IRQ FRAME Threshold RX0 0 Register"
hexmask.long.byte (0x10+0x00) 24.--31. 1. " FRAME_THRES_RX0_3 ,Threshold value for USB0 endpoint 3"
hexmask.long.byte (0x10+0x00) 16.--23. 1. " FRAME_THRES_RX0_2 ,Threshold value for USB0 endpoint 2"
textline " "
hexmask.long.byte (0x10+0x00) 8.--15. 1. " FRAME_THRES_RX0_1 ,Threshold value for USB0 endpoint 1"
line.long (0x10+0x04) "IRQFRAMETHOLDRX01,IRQ FRAME Threshold RX0 1 Register"
hexmask.long.byte (0x10+0x04) 24.--31. 1. " FRAME_THRES_RX0_7 ,Threshold value for USB0 endpoint 7"
hexmask.long.byte (0x10+0x04) 16.--23. 1. " FRAME_THRES_RX0_6 ,Threshold value for USB0 endpoint 6"
textline " "
hexmask.long.byte (0x10+0x04) 8.--15. 1. " FRAME_THRES_RX0_5 ,Threshold value for USB0 endpoint 5"
hexmask.long.byte (0x10+0x04) 0.--7. 1. " FRAME_THRES_RX0_4 ,Threshold value for USB0 endpoint 4"
line.long (0x10+0x08) "IRQFRAMETHOLDRX02,IRQ FRAME Threshold RX0 2 Register"
hexmask.long.byte (0x10+0x08) 24.--31. 1. " FRAME_THRES_RX0_11 ,Threshold value for USB0 endpoint 11"
hexmask.long.byte (0x10+0x08) 16.--23. 1. " FRAME_THRES_RX0_10 ,Threshold value for USB0 endpoint 10"
textline " "
hexmask.long.byte (0x10+0x08) 8.--15. 1. " FRAME_THRES_RX0_9 ,Threshold value for USB0 endpoint 9"
hexmask.long.byte (0x10+0x08) 0.--7. 1. " FRAME_THRES_RX0_8 ,Threshold value for USB0 endpoint 8"
line.long (0x10+0x0C) "IRQFRAMETHOLDRX03,IRQ FRAME Threshold RX0 3 Register"
hexmask.long.byte (0x10+0x0C) 24.--31. 1. " FRAME_THRES_RX0_15 ,Threshold value for USB0 endpoint 15"
hexmask.long.byte (0x10+0x0C) 16.--23. 1. " FRAME_THRES_RX0_14 ,Threshold value for USB0 endpoint 14"
textline " "
hexmask.long.byte (0x10+0x0C) 8.--15. 1. " FRAME_THRES_RX0_13 ,Threshold value for USB0 endpoint 13"
hexmask.long.byte (0x10+0x0C) 0.--7. 1. " FRAME_THRES_RX0_12 ,Threshold value for USB0 endpoint 12"
line.long (0x20+0x00) "IRQFRAMETHOLDTX10,IRQ FRAME Threshold TX1 0 Register"
hexmask.long.byte (0x20+0x00) 24.--31. 1. " FRAME_THRES_TX1_3 ,Threshold value for USB1 endpoint 3"
hexmask.long.byte (0x20+0x00) 16.--23. 1. " FRAME_THRES_TX1_2 ,Threshold value for USB1 endpoint 2"
textline " "
hexmask.long.byte (0x20+0x00) 8.--15. 1. " FRAME_THRES_TX1_1 ,Threshold value for USB1 endpoint 1"
line.long (0x20+0x04) "IRQFRAMETHOLDTX11,IRQ FRAME Threshold TX1 1 Register"
hexmask.long.byte (0x20+0x04) 24.--31. 1. " FRAME_THRES_TX1_7 ,Threshold value for USB1 endpoint 7"
hexmask.long.byte (0x20+0x04) 16.--23. 1. " FRAME_THRES_TX1_6 ,Threshold value for USB1 endpoint 6"
textline " "
hexmask.long.byte (0x20+0x04) 8.--15. 1. " FRAME_THRES_TX1_5 ,Threshold value for USB1 endpoint 5"
hexmask.long.byte (0x20+0x04) 0.--7. 1. " FRAME_THRES_TX1_4 ,Threshold value for USB1 endpoint 4"
line.long (0x20+0x08) "IRQFRAMETHOLDTX12,IRQ FRAME Threshold TX1 2 Register"
hexmask.long.byte (0x20+0x08) 24.--31. 1. " FRAME_THRES_TX1_11 ,Threshold value for USB1 endpoint 11"
hexmask.long.byte (0x20+0x08) 16.--23. 1. " FRAME_THRES_TX1_10 ,Threshold value for USB1 endpoint 10"
textline " "
hexmask.long.byte (0x20+0x08) 8.--15. 1. " FRAME_THRES_TX1_9 ,Threshold value for USB1 endpoint 9"
hexmask.long.byte (0x20+0x08) 0.--7. 1. " FRAME_THRES_TX1_8 ,Threshold value for USB1 endpoint 8"
line.long (0x20+0x0C) "IRQFRAMETHOLDTX13,IRQ FRAME Threshold TX1 3 Register"
hexmask.long.byte (0x20+0x0C) 24.--31. 1. " FRAME_THRES_TX1_15 ,Threshold value for USB1 endpoint 15"
hexmask.long.byte (0x20+0x0C) 16.--23. 1. " FRAME_THRES_TX1_14 ,Threshold value for USB1 endpoint 14"
textline " "
hexmask.long.byte (0x20+0x0C) 8.--15. 1. " FRAME_THRES_TX1_13 ,Threshold value for USB1 endpoint 13"
hexmask.long.byte (0x20+0x0C) 0.--7. 1. " FRAME_THRES_TX1_12 ,Threshold value for USB1 endpoint 12"
line.long (0x30+0x00) "IRQFRAMETHOLDRX10,IRQ FRAME Threshold RX1 0 Register"
hexmask.long.byte (0x30+0x00) 24.--31. 1. " FRAME_THRES_RX1_3 ,Threshold value for USB1 endpoint 3"
hexmask.long.byte (0x30+0x00) 16.--23. 1. " FRAME_THRES_RX1_2 ,Threshold value for USB1 endpoint 2"
textline " "
hexmask.long.byte (0x30+0x00) 8.--15. 1. " FRAME_THRES_RX1_1 ,Threshold value for USB1 endpoint 1"
line.long (0x30+0x04) "IRQFRAMETHOLDRX11,IRQ FRAME Threshold RX1 1 Register"
hexmask.long.byte (0x30+0x04) 24.--31. 1. " FRAME_THRES_RX1_7 ,Threshold value for USB1 endpoint 7"
hexmask.long.byte (0x30+0x04) 16.--23. 1. " FRAME_THRES_RX1_6 ,Threshold value for USB1 endpoint 6"
textline " "
hexmask.long.byte (0x30+0x04) 8.--15. 1. " FRAME_THRES_RX1_5 ,Threshold value for USB1 endpoint 5"
hexmask.long.byte (0x30+0x04) 0.--7. 1. " FRAME_THRES_RX1_4 ,Threshold value for USB1 endpoint 4"
line.long (0x30+0x08) "IRQFRAMETHOLDRX12,IRQ FRAME Threshold RX1 2 Register"
hexmask.long.byte (0x30+0x08) 24.--31. 1. " FRAME_THRES_RX1_11 ,Threshold value for USB1 endpoint 11"
hexmask.long.byte (0x30+0x08) 16.--23. 1. " FRAME_THRES_RX1_10 ,Threshold value for USB1 endpoint 10"
textline " "
hexmask.long.byte (0x30+0x08) 8.--15. 1. " FRAME_THRES_RX1_9 ,Threshold value for USB1 endpoint 9"
hexmask.long.byte (0x30+0x08) 0.--7. 1. " FRAME_THRES_RX1_8 ,Threshold value for USB1 endpoint 8"
line.long (0x30+0x0C) "IRQFRAMETHOLDRX13,IRQ FRAME Threshold RX1 3 Register"
hexmask.long.byte (0x30+0x0C) 24.--31. 1. " FRAME_THRES_RX1_15 ,Threshold value for USB1 endpoint 15"
hexmask.long.byte (0x30+0x0C) 16.--23. 1. " FRAME_THRES_RX1_14 ,Threshold value for USB1 endpoint 14"
textline " "
hexmask.long.byte (0x30+0x0C) 8.--15. 1. " FRAME_THRES_RX1_13 ,Threshold value for USB1 endpoint 13"
hexmask.long.byte (0x30+0x0C) 0.--7. 1. " FRAME_THRES_RX1_12 ,Threshold value for USB1 endpoint 12"
line.long 0x40 "IRQFRAMEENABLE0,IRQ FRAME Enable 0 Register"
bitfld.long 0x40 31. " FRAME_EN_RX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x40 30. " FRAME_EN_RX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
bitfld.long 0x40 29. " FRAME_EN_RX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x40 28. " FRAME_EN_RX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
bitfld.long 0x40 27. " FRAME_EN_RX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
bitfld.long 0x40 26. " FRAME_EN_RX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x40 25. " FRAME_EN_RX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
bitfld.long 0x40 24. " FRAME_EN_RX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
bitfld.long 0x40 23. " FRAME_EN_RX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x40 22. " FRAME_EN_RX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
bitfld.long 0x40 21. " FRAME_EN_RX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
bitfld.long 0x40 20. " FRAME_EN_RX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x40 19. " FRAME_EN_RX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
bitfld.long 0x40 18. " FRAME_EN_RX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x40 17. " FRAME_EN_RX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
textline " "
bitfld.long 0x40 15. " FRAME_EN_TX0_15 ,Threshold enable value for USB0 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x40 14. " FRAME_EN_TX0_14 ,Threshold enable value for USB0 endpoint 14" "Disabled,Enabled"
bitfld.long 0x40 13. " FRAME_EN_TX0_13 ,Threshold enable value for USB0 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x40 12. " FRAME_EN_TX0_12 ,Threshold enable value for USB0 endpoint 12" "Disabled,Enabled"
bitfld.long 0x40 11. " FRAME_EN_TX0_11 ,Threshold enable value for USB0 endpoint 11" "Disabled,Enabled"
bitfld.long 0x40 10. " FRAME_EN_TX0_10 ,Threshold enable value for USB0 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x40 9. " FRAME_EN_TX0_9 ,Threshold enable value for USB0 endpoint 9" "Disabled,Enabled"
bitfld.long 0x40 8. " FRAME_EN_TX0_8 ,Threshold enable value for USB0 endpoint 8" "Disabled,Enabled"
bitfld.long 0x40 7. " FRAME_EN_TX0_7 ,Threshold enable value for USB0 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x40 6. " FRAME_EN_TX0_6 ,Threshold enable value for USB0 endpoint 6" "Disabled,Enabled"
bitfld.long 0x40 5. " FRAME_EN_TX0_5 ,Threshold enable value for USB0 endpoint 5" "Disabled,Enabled"
bitfld.long 0x40 4. " FRAME_EN_TX0_4 ,Threshold enable value for USB0 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x40 3. " FRAME_EN_TX0_3 ,Threshold enable value for USB0 endpoint 3" "Disabled,Enabled"
bitfld.long 0x40 2. " FRAME_EN_TX0_2 ,Threshold enable value for USB0 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x40 1. " FRAME_EN_TX0_1 ,Threshold enable value for USB0 endpoint 1" "Disabled,Enabled"
line.long 0x44 "IRQFRAMEENABLE1,IRQ FRAME Enable 1 Register"
bitfld.long 0x44 31. " FRAME_EN_RX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x44 30. " FRAME_EN_RX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
bitfld.long 0x44 29. " FRAME_EN_RX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x44 28. " FRAME_EN_RX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
bitfld.long 0x44 27. " FRAME_EN_RX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
bitfld.long 0x44 26. " FRAME_EN_RX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x44 25. " FRAME_EN_RX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
bitfld.long 0x44 24. " FRAME_EN_RX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
bitfld.long 0x44 23. " FRAME_EN_RX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x44 22. " FRAME_EN_RX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
bitfld.long 0x44 21. " FRAME_EN_RX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
bitfld.long 0x44 20. " FRAME_EN_RX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x44 19. " FRAME_EN_RX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
bitfld.long 0x44 18. " FRAME_EN_RX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x44 17. " FRAME_EN_RX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
textline " "
bitfld.long 0x44 15. " FRAME_EN_TX1_15 ,Threshold enable value for USB1 endpoint 15" "Disabled,Enabled"
sif (!cpuis("AM335*"))
bitfld.long 0x44 14. " FRAME_EN_TX1_14 ,Threshold enable value for USB1 endpoint 14" "Disabled,Enabled"
bitfld.long 0x44 13. " FRAME_EN_TX1_13 ,Threshold enable value for USB1 endpoint 13" "Disabled,Enabled"
textline " "
bitfld.long 0x44 12. " FRAME_EN_TX1_12 ,Threshold enable value for USB1 endpoint 12" "Disabled,Enabled"
bitfld.long 0x44 11. " FRAME_EN_TX1_11 ,Threshold enable value for USB1 endpoint 11" "Disabled,Enabled"
bitfld.long 0x44 10. " FRAME_EN_TX1_10 ,Threshold enable value for USB1 endpoint 10" "Disabled,Enabled"
textline " "
bitfld.long 0x44 9. " FRAME_EN_TX1_9 ,Threshold enable value for USB1 endpoint 9" "Disabled,Enabled"
bitfld.long 0x44 8. " FRAME_EN_TX1_8 ,Threshold enable value for USB1 endpoint 8" "Disabled,Enabled"
bitfld.long 0x44 7. " FRAME_EN_TX1_7 ,Threshold enable value for USB1 endpoint 7" "Disabled,Enabled"
textline " "
bitfld.long 0x44 6. " FRAME_EN_TX1_6 ,Threshold enable value for USB1 endpoint 6" "Disabled,Enabled"
bitfld.long 0x44 5. " FRAME_EN_TX1_5 ,Threshold enable value for USB1 endpoint 5" "Disabled,Enabled"
bitfld.long 0x44 4. " FRAME_EN_TX1_4 ,Threshold enable value for USB1 endpoint 4" "Disabled,Enabled"
textline " "
bitfld.long 0x44 3. " FRAME_EN_TX1_3 ,Threshold enable value for USB1 endpoint 3" "Disabled,Enabled"
bitfld.long 0x44 2. " FRAME_EN_TX1_2 ,Threshold enable value for USB1 endpoint 2" "Disabled,Enabled"
endif
bitfld.long 0x44 1. " FRAME_EN_TX1_1 ,Threshold enable value for USB1 endpoint 1" "Disabled,Enabled"
tree.end
width 11.
tree.end
tree "USB Controller"
tree "USB0 Controller Registers"
base ad:0x47401000
width 18.
rgroup.long 0x00++0x03
line.long 0x00 "USB0REV,USB0 Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "USB0CONTROL,USB0 Control Register"
bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes"
bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes"
textline " "
sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled"
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
else
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB0" "No reset,Reset"
rgroup.long 0x18++0x03
line.long 0x00 "USB0STATUS,USB0 Status Register"
bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
rgroup.long 0x20++0x03
line.long 0x00 "USB0IRQMSTAT,USB0 IRQ Merged Status Register"
bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending"
sif (!cpuis("AM335*"))
group.long 0x24++03
line.long 0x00 "USB0IRQEOI,USB0 IRQ End of Interrupt Register"
bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High"
endif
group.long 0x28++0x1F
line.long 0x00 "USB0IRQSTATRAW0,USB0 IRQ Status Raw 0 Register"
bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
line.long 0x04 "USB0IRQSTATRAW1,USB0 IRQ Status Raw 1 Register"
bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending"
bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending"
textline " "
bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending"
textline " "
bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending"
line.long 0x08 "USB0IRQSTAT0,USB0 IRQ Status 0 Register"
eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
line.long 0x0C "USB0IRQSTAT1,USB0 IRQ Status 1 Register"
eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending"
eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending"
eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending"
eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending"
textline " "
eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending"
eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending"
textline " "
eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending"
eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending"
line.long 0x10 "USB0IRQENABLESET0,USB0 IRQ Enable Set 0 Register"
bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled"
line.long 0x14 "USB0IRQENABLESET1,USB0 IRQ Enable Set 1 Register"
bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled"
bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled"
line.long 0x18 "USB0IRQENABLECLR0,USB0 IRQ Enable Clear 0 Register"
eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled"
eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled"
line.long 0x1C "USB0IRQENABLECLR1,USB0 IRQ Enable Clear 1 Register"
eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled"
eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled"
group.long 0x70++0x07
line.long 0x00 "USB0TXMODE,USB0 Tx Mode Register"
bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
line.long 0x04 "USB0RXMODE,USB0 Rx Mode Register"
bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
group.long 0x80++0x3B
line.long 0x0 "USB0GENRNDISEP1,USB0 Generic RNDIS EP1 Size Register"
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1"
line.long 0x4 "USB0GENRNDISEP2,USB0 Generic RNDIS EP2 Size Register"
hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2"
line.long 0x8 "USB0GENRNDISEP3,USB0 Generic RNDIS EP3 Size Register"
hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3"
line.long 0xC "USB0GENRNDISEP4,USB0 Generic RNDIS EP4 Size Register"
hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4"
line.long 0x10 "USB0GENRNDISEP5,USB0 Generic RNDIS EP5 Size Register"
hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5"
line.long 0x14 "USB0GENRNDISEP6,USB0 Generic RNDIS EP6 Size Register"
hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6"
line.long 0x18 "USB0GENRNDISEP7,USB0 Generic RNDIS EP7 Size Register"
hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7"
line.long 0x1C "USB0GENRNDISEP8,USB0 Generic RNDIS EP8 Size Register"
hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8"
line.long 0x20 "USB0GENRNDISEP9,USB0 Generic RNDIS EP9 Size Register"
hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9"
line.long 0x24 "USB0GENRNDISEP10,USB0 Generic RNDIS EP10 Size Register"
hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10"
line.long 0x28 "USB0GENRNDISEP11,USB0 Generic RNDIS EP11 Size Register"
hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11"
line.long 0x2C "USB0GENRNDISEP12,USB0 Generic RNDIS EP12 Size Register"
hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12"
line.long 0x30 "USB0GENRNDISEP13,USB0 Generic RNDIS EP13 Size Register"
hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13"
line.long 0x34 "USB0GENRNDISEP14,USB0 Generic RNDIS EP14 Size Register"
hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14"
line.long 0x38 "USB0GENRNDISEP15,USB0 Generic RNDIS EP15 Size Register"
hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15"
group.long 0xD0++0xB
line.long 0x00 "USB0AUTOREQ,USB0 Auto Req Register"
bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
line.long 0x04 "USB0SRPFIXTIME,USB0 SRP Fix Time Register"
line.long 0x08 "USB0TDOWN,USB0 Teardown Register"
bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled"
bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled"
bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled"
bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled"
bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled"
bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled"
bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled"
bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled"
bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled"
bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled"
bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled"
bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled"
bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled"
bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled"
bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled"
bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled"
bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
sif cpuis("DM814?DSP")
group.long 0xDC++0x03
line.long 0x00 "USB0THRESXDMA,USB0 Threshold XDMA Idle Register"
hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter"
endif
group.long 0xE0++0x0B
line.long 0x00 "USB0UTMI,USB0 PHY UTMI Register"
bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High"
sif !cpuis("DM814?DSP")
bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High"
textline " "
bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High"
bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High"
textline " "
bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High"
endif
bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High"
sif !cpuis("DM814?DSP")
textline " "
bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High"
bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh"
bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High"
textline " "
bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High"
bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High"
endif
line.long 0x04 "USB0UTMILB,USB0 MGC UTMI Loopback Register"
sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
textline " "
rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
textline " "
rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
textline " "
rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
textline " "
rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
textline " "
rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
else
bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
textline " "
bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
textline " "
bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
textline " "
bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
textline " "
bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
textline " "
bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
endif
bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High"
textline " "
bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High"
bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High"
textline " "
bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High"
bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High"
textline " "
bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High"
bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3"
line.long 0x08 "USB0MODE,USB0 Mode Register"
bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type"
textline " "
sif (cpuis("AM335*"))
bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)"
textline " "
endif
bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled"
textline " "
bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled"
width 0xb
tree.end
tree "USB1 Controller Registers"
base ad:0x47401800
width 18.
rgroup.long 0x00++0x03
line.long 0x00 "USB1REV,USB1 Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Used to distinguish between old scheme and current" "Legacy ASP or WTBU,Highlander 0.8,?..."
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " R_RTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " X_MAJOR ,Major revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " CUSTOM ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. " Y_MINOR ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x03
line.long 0x00 "USB1CONTROL,USB1 Control Register"
bitfld.long 0x00 31. " DIS_DEB ,Disable the VBUS debouncer circuit fix" "No,Yes"
bitfld.long 0x00 30. " DIS_SRP ,Disable the SRP a_valid circuit fix" "No,Yes"
textline " "
sif ((cpuis("DM814?DSP"))||(cpuis("DRA6*"))||(cpuis("AM335*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872")||(cpu()=="DM8165")||(cpu()=="DM8166")||(cpu()=="DM8167")||(cpu()=="DM8168")||(cpu()=="DM8165DSP")||(cpu()=="DM8166DSP")||(cpu()=="DM8167DSP")||(cpu()=="DM8168DSP"))
bitfld.long 0x00 5. " SRI ,Soft reset isolation" "Disabled,Enabled"
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
else
bitfld.long 0x00 4. " RNDIS ,Global RNDIS mode enable for all endpoints" "Disabled,Enabled"
endif
textline " "
bitfld.long 0x00 3. " UINT ,USB non-Highlander interrupt enable" "Disabled,Enabled"
bitfld.long 0x00 1. " CLKFACK ,Clock stop fast ack enable" "Disabled,Enabled"
textline " "
bitfld.long 0x00 0. " SOFT_RESET ,Software reset of USB1" "No reset,Reset"
rgroup.long 0x18++0x03
line.long 0x00 "USB1STATUS,USB1 Status Register"
bitfld.long 0x00 0. " DRVVBUS ,Current DRVVBUS value" "Low,High"
rgroup.long 0x20++0x03
line.long 0x00 "USB1IRQMSTAT,USB1 IRQ Merged Status Register"
bitfld.long 0x00 1. " BANK1 ,Events from IRQ_STATUS_1" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " BANK0 ,Events from IRQ_STATUS_0" "Not pending,Pending"
sif (!cpuis("AM335*"))
group.long 0x24++03
line.long 0x00 "USB1IRQEOI,USB1 IRQ End of Interrupt Register"
bitfld.long 0x00 0. " EOI ,End of interrupt" "Low,High"
endif
group.long 0x28++0x1F
line.long 0x00 "USB1IRQSTATRAW0,USB1 IRQ Status Raw 0 Register"
bitfld.long 0x00 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
bitfld.long 0x00 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
bitfld.long 0x00 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
bitfld.long 0x00 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
bitfld.long 0x00 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
bitfld.long 0x00 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
bitfld.long 0x00 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
bitfld.long 0x00 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
bitfld.long 0x00 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
bitfld.long 0x00 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
bitfld.long 0x00 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
bitfld.long 0x00 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
bitfld.long 0x00 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
bitfld.long 0x00 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
bitfld.long 0x00 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
bitfld.long 0x00 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
textline " "
bitfld.long 0x00 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
line.long 0x04 "USB1IRQSTATRAW1,USB1 IRQ Status Raw 1 Register"
bitfld.long 0x04 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 9. " USB[9] , Mentor controller USB_INT generic interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 8. " USB[8] ,DRVVBUS level change interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 7. " USB[7] ,VBUS < VBUS valid threshold interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 6. " USB[6] ,SRP detected interrupt raw status" "Not pending,Pending"
textline " "
bitfld.long 0x04 5. " USB[5] ,Device disconnected interrupt raw status (host mode)" "Not pending,Pending"
bitfld.long 0x04 4. " USB[4] ,Device connected interrupt raw status (host mode)" "Not pending,Pending"
textline " "
bitfld.long 0x04 3. " USB[3] ,SOF started interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 2. " USB[2] ,Reset signaling/Babble detected interrupt raw status (peripheral/host mode)" "Not pending,Pending"
textline " "
bitfld.long 0x04 1. " USB[1] ,Resume signaling interrupt raw status" "Not pending,Pending"
bitfld.long 0x04 0. " USB[0] ,Suspend signaling interrupt raw status" "Not pending,Pending"
line.long 0x08 "USB1IRQSTAT0,USB1 IRQ Status 0 Register"
eventfld.long 0x08 31. " RX_EP15 ,RX EP15 interrupt status" "Not pending,Pending"
eventfld.long 0x08 30. " RX_EP14 ,RX EP14 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 29. " RX_EP13 ,RX EP13 interrupt status" "Not pending,Pending"
eventfld.long 0x08 28. " RX_EP12 ,RX EP12 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 27. " RX_EP11 ,RX EP11 interrupt status" "Not pending,Pending"
eventfld.long 0x08 26. " RX_EP10 ,RX EP10 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 25. " RX_EP9 ,RX EP9 interrupt status" "Not pending,Pending"
eventfld.long 0x08 24. " RX_EP8 ,RX EP8 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 23. " RX_EP7 ,RX EP7 interrupt status" "Not pending,Pending"
eventfld.long 0x08 22. " RX_EP6 ,RX EP6 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 21. " RX_EP5 ,RX EP5 interrupt status" "Not pending,Pending"
eventfld.long 0x08 20. " RX_EP4 ,RX EP4 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 19. " RX_EP3 ,RX EP3 interrupt status" "Not pending,Pending"
eventfld.long 0x08 18. " RX_EP2 ,RX EP2 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 17. " RX_EP1 ,RX EP1 interrupt status" "Not pending,Pending"
eventfld.long 0x08 15. " TX_EP15 ,TX EP15 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 14. " TX_EP14 ,TX EP14 interrupt status" "Not pending,Pending"
eventfld.long 0x08 13. " TX_EP13 ,TX EP13 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 12. " TX_EP12 ,TX EP12 interrupt status" "Not pending,Pending"
eventfld.long 0x08 11. " TX_EP11 ,TX EP11 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 10. " TX_EP10 ,TX EP10 interrupt status" "Not pending,Pending"
eventfld.long 0x08 9. " TX_EP9 ,TX EP9 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 8. " TX_EP8 ,TX EP8 interrupt status" "Not pending,Pending"
eventfld.long 0x08 7. " TX_EP7 ,TX EP7 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 6. " TX_EP6 ,TX EP6 interrupt status" "Not pending,Pending"
eventfld.long 0x08 5. " TX_EP5 ,TX EP5 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 4. " TX_EP4 ,TX EP4 interrupt status" "Not pending,Pending"
eventfld.long 0x08 3. " TX_EP3 ,TX EP3 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 2. " TX_EP2 ,TX EP2 interrupt status" "Not pending,Pending"
eventfld.long 0x08 1. " TX_EP1 ,TX EP1 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x08 0. " TX_EP0 ,TX EP0 interrupt status" "Not pending,Pending"
line.long 0x0C "USB1IRQSTAT1,USB1 IRQ Status 1 Register"
eventfld.long 0x0C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt status" "Not pending,Pending"
eventfld.long 0x0C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 9. " USB[9] , Mentor controller USB_INT generic interrupt status" "Not pending,Pending"
eventfld.long 0x0C 8. " USB[8] ,DRVVBUS level change interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt status" "Not pending,Pending"
eventfld.long 0x0C 6. " USB[6] ,SRP detected interrupt status" "Not pending,Pending"
textline " "
eventfld.long 0x0C 5. " USB[5] ,Device disconnected interrupt status (host mode)" "Not pending,Pending"
eventfld.long 0x0C 4. " USB[4] ,Device connected interrupt status (host mode)" "Not pending,Pending"
textline " "
eventfld.long 0x0C 3. " USB[3] ,SOF started interrupt status" "Not pending,Pending"
eventfld.long 0x0C 2. " USB[2] ,Reset signaling/Babble detected interrupt status (peripheral/host mode)" "Not pending,Pending"
textline " "
eventfld.long 0x0C 1. " USB[1] ,Resume signaling interrupt status" "Not pending,Pending"
eventfld.long 0x0C 0. " USB[0] ,Suspend signaling interrupt status" "Not pending,Pending"
line.long 0x10 "USB1IRQENABLESET0,USB1 IRQ Enable Set 0 Register"
bitfld.long 0x10 31. " RX_EP15 ,RX EP15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 30. " RX_EP14 ,RX EP14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 29. " RX_EP13 ,RX EP13 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 28. " RX_EP12 ,RX EP12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 27. " RX_EP11 ,RX EP11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 26. " RX_EP10 ,RX EP10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 25. " RX_EP9 ,RX EP9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 24. " RX_EP8 ,RX EP8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 23. " RX_EP7 ,RX EP7 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 22. " RX_EP6 ,RX EP6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 21. " RX_EP5 ,RX EP5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 20. " RX_EP4 ,RX EP4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 19. " RX_EP3 ,RX EP3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 18. " RX_EP2 ,RX EP2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 17. " RX_EP1 ,RX EP1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 15. " TX_EP15 ,TX EP15 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 14. " TX_EP14 ,TX EP14 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 13. " TX_EP13 ,TX EP13 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 12. " TX_EP12 ,TX EP12 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 11. " TX_EP11 ,TX EP11 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 10. " TX_EP10 ,TX EP10 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 9. " TX_EP9 ,TX EP9 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 8. " TX_EP8 ,TX EP8 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 7. " TX_EP7 ,TX EP7 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 6. " TX_EP6 ,TX EP6 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 5. " TX_EP5 ,TX EP5 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 4. " TX_EP4 ,TX EP4 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 3. " TX_EP3 ,TX EP3 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 2. " TX_EP2 ,TX EP2 interrupt enable" "Disabled,Enabled"
bitfld.long 0x10 1. " TX_EP1 ,TX EP1 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x10 0. " TX_EP0 ,TX EP0 interrupt enable" "Disabled,Enabled"
line.long 0x14 "USB1IRQENABLESET1,USB1 IRQ Enable Set 1 Register"
bitfld.long 0x14 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 9. " USB[9] , Mentor controller USB_INT generic interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 8. " USB[8] ,DRVVBUS level change interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 7. " USB[7] ,VBUS < VBUS valid threshold interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 6. " USB[6] ,SRP detected interrupt enable" "Disabled,Enabled"
textline " "
bitfld.long 0x14 5. " USB[5] ,Device disconnected interrupt enable status (host mode)" "Disabled,Enabled"
bitfld.long 0x14 4. " USB[4] ,Device connected interrupt enable status (host mode)" "Disabled,Enabled"
textline " "
bitfld.long 0x14 3. " USB[3] ,SOF started interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 2. " USB[2] ,Reset signaling/Babble detected interrupt enable status (peripheral/host mode)" "Disabled,Enabled"
textline " "
bitfld.long 0x14 1. " USB[1] ,Resume signaling interrupt enable" "Disabled,Enabled"
bitfld.long 0x14 0. " USB[0] ,Suspend signaling interrupt enable" "Disabled,Enabled"
line.long 0x18 "USB1IRQENABLECLR0,USB1 IRQ Enable Clear 0 Register"
eventfld.long 0x18 31. " RX_EP15 ,RX EP15 iinterrupt disable" "Disabled,Enabled"
eventfld.long 0x18 30. " RX_EP14 ,RX EP14 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 29. " RX_EP13 ,RX EP13 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 28. " RX_EP12 ,RX EP12 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 27. " RX_EP11 ,RX EP11 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 26. " RX_EP10 ,RX EP10 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 25. " RX_EP9 ,RX EP9 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 24. " RX_EP8 ,RX EP8 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 23. " RX_EP7 ,RX EP7 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 22. " RX_EP6 ,RX EP6 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 21. " RX_EP5 ,RX EP5 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 20. " RX_EP4 ,RX EP4 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 19. " RX_EP3 ,RX EP3 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 18. " RX_EP2 ,RX EP2 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 17. " RX_EP1 ,RX EP1 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 15. " TX_EP15 ,TX EP15 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 14. " TX_EP14 ,TX EP14 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 13. " TX_EP13 ,TX EP13 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 12. " TX_EP12 ,TX EP12 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 11. " TX_EP11 ,TX EP11 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 10. " TX_EP10 ,TX EP10 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 9. " TX_EP9 ,TX EP9 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 8. " TX_EP8 ,TX EP8 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 7. " TX_EP7 ,TX EP7 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 6. " TX_EP6 ,TX EP6 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 5. " TX_EP5 ,TX EP5 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 4. " TX_EP4 ,TX EP4 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 3. " TX_EP3 ,TX EP3 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 2. " TX_EP2 ,TX EP2 interrupt disable" "Disabled,Enabled"
eventfld.long 0x18 1. " TX_EP1 ,TX EP1 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x18 0. " TX_EP0 ,TX EP0 interrupt disable" "Disabled,Enabled"
line.long 0x1C "USB1IRQENABLECLR1,USB1 IRQ Enable Clear 1 Register"
eventfld.long 0x1C 31. " TX_FIFO15 ,TX FIFO endpoint 15 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 30. " TX_FIFO14 ,TX FIFO endpoint 14 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 29. " TX_FIFO13 ,TX FIFO endpoint 13 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 28. " TX_FIFO12 ,TX FIFO endpoint 12 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 27. " TX_FIFO11 ,TX FIFO endpoint 11 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 26. " TX_FIFO10 ,TX FIFO endpoint 10 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 25. " TX_FIFO9 ,TX FIFO endpoint 9 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 24. " TX_FIFO8 ,TX FIFO endpoint 8 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 23. " TX_FIFO7 ,TX FIFO endpoint 7 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 22. " TX_FIFO6 ,TX FIFO endpoint 6 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 21. " TX_FIFO5 ,TX FIFO endpoint 5 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 20. " TX_FIFO4 ,TX FIFO endpoint 4 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 19. " TX_FIFO3 ,TX FIFO endpoint 3 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 18. " TX_FIFO2 ,TX FIFO endpoint 2 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 17. " TX_FIFO1 ,TX FIFO endpoint 1 interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 16. " TX_FIFO0 ,TX FIFO endpoint 0 interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 9. " USB[9] , Mentor controller USB_INT generic interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 8. " USB[8] ,DRVVBUS level change interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 7. " USB[7] ,VBUS < VBUS valid threshold interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 6. " USB[6] ,SRP detected interrupt disable" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 5. " USB[5] ,Device disconnected interrupt disable (host mode)" "Disabled,Enabled"
eventfld.long 0x1C 4. " USB[4] ,Device connected interrupt disable (host mode)" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 3. " USB[3] ,SOF started interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 2. " USB[2] ,Reset signaling/Babble detected interrupt disable (peripheral/host mode)" "Disabled,Enabled"
textline " "
eventfld.long 0x1C 1. " USB[1] ,Resume signaling interrupt disable" "Disabled,Enabled"
eventfld.long 0x1C 0. " USB[0] ,Suspend signaling interrupt disable" "Disabled,Enabled"
group.long 0x70++0x07
line.long 0x00 "USB1TXMODE,USB1 Tx Mode Register"
bitfld.long 0x00 28.--29. " TX15_MODE ,Endpoint 15 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 26.--27. " TX14_MODE ,Endpoint 14 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 24.--25. " TX13_MODE ,Endpoint 13 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 22.--23. " TX12_MODE ,Endpoint 12 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 20.--21. " TX11_MODE ,Endpoint 11 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 18.--19. " TX10_MODE ,Endpoint 10 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 16.--17. " TX9_MODE ,Endpoint 9 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 14.--15. " TX8_MODE ,Endpoint 8 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 12.--13. " TX7_MODE ,Endpoint 7 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 10.--11. " TX6_MODE ,Endpoint 6 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 8.--9. " TX5_MODE ,Endpoint 5 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 6.--7. " TX4_MODE ,Endpoint 4 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 4.--5. " TX3_MODE ,Endpoint 3 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x00 2.--3. " TX2_MODE ,Endpoint 2 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x00 0.--1. " TX1_MODE ,Endpoint 1 Transmit Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
line.long 0x04 "USB1RXMODE,USB1 Rx Mode Register"
bitfld.long 0x04 28.--29. " RX15_MODE ,Endpoint 15 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 26.--27. " RX14_MODE ,Endpoint 14 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 24.--25. " RX13_MODE ,Endpoint 13 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 22.--23. " RX12_MODE ,Endpoint 12 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 20.--21. " RX11_MODE ,Endpoint 11 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 18.--19. " RX10_MODE ,Endpoint 10 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 16.--17. " RX9_MODE ,Endpoint 9 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 14.--15. " RX8_MODE ,Endpoint 8 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 12.--13. " RX7_MODE ,Endpoint 7 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 10.--11. " RX6_MODE ,Endpoint 6 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 8.--9. " RX5_MODE ,Endpoint 5 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 6.--7. " RX4_MODE ,Endpoint 4 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 4.--5. " RX3_MODE ,Endpoint 3 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
bitfld.long 0x04 2.--3. " RX2_MODE ,Endpoint 2 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
textline " "
bitfld.long 0x04 0.--1. " RX1_MODE ,Endpoint 1 Receive Mode" "Transparent,RNDIS,CDC,Generic RNDIS"
group.long 0x80++0x3B
line.long 0x0 "USB1GENRNDISEP1,USB1 Generic RNDIS EP1 Size Register"
hexmask.long.tbyte 0x0 0.--16. 1. " EP1_SIZE ,Generic RNDIS packeet size 1"
line.long 0x4 "USB1GENRNDISEP2,USB1 Generic RNDIS EP2 Size Register"
hexmask.long.tbyte 0x4 0.--16. 1. " EP2_SIZE ,Generic RNDIS packeet size 2"
line.long 0x8 "USB1GENRNDISEP3,USB1 Generic RNDIS EP3 Size Register"
hexmask.long.tbyte 0x8 0.--16. 1. " EP3_SIZE ,Generic RNDIS packeet size 3"
line.long 0xC "USB1GENRNDISEP4,USB1 Generic RNDIS EP4 Size Register"
hexmask.long.tbyte 0xC 0.--16. 1. " EP4_SIZE ,Generic RNDIS packeet size 4"
line.long 0x10 "USB1GENRNDISEP5,USB1 Generic RNDIS EP5 Size Register"
hexmask.long.tbyte 0x10 0.--16. 1. " EP5_SIZE ,Generic RNDIS packeet size 5"
line.long 0x14 "USB1GENRNDISEP6,USB1 Generic RNDIS EP6 Size Register"
hexmask.long.tbyte 0x14 0.--16. 1. " EP6_SIZE ,Generic RNDIS packeet size 6"
line.long 0x18 "USB1GENRNDISEP7,USB1 Generic RNDIS EP7 Size Register"
hexmask.long.tbyte 0x18 0.--16. 1. " EP7_SIZE ,Generic RNDIS packeet size 7"
line.long 0x1C "USB1GENRNDISEP8,USB1 Generic RNDIS EP8 Size Register"
hexmask.long.tbyte 0x1C 0.--16. 1. " EP8_SIZE ,Generic RNDIS packeet size 8"
line.long 0x20 "USB1GENRNDISEP9,USB1 Generic RNDIS EP9 Size Register"
hexmask.long.tbyte 0x20 0.--16. 1. " EP9_SIZE ,Generic RNDIS packeet size 9"
line.long 0x24 "USB1GENRNDISEP10,USB1 Generic RNDIS EP10 Size Register"
hexmask.long.tbyte 0x24 0.--16. 1. " EP10_SIZE ,Generic RNDIS packeet size 10"
line.long 0x28 "USB1GENRNDISEP11,USB1 Generic RNDIS EP11 Size Register"
hexmask.long.tbyte 0x28 0.--16. 1. " EP11_SIZE ,Generic RNDIS packeet size 11"
line.long 0x2C "USB1GENRNDISEP12,USB1 Generic RNDIS EP12 Size Register"
hexmask.long.tbyte 0x2C 0.--16. 1. " EP12_SIZE ,Generic RNDIS packeet size 12"
line.long 0x30 "USB1GENRNDISEP13,USB1 Generic RNDIS EP13 Size Register"
hexmask.long.tbyte 0x30 0.--16. 1. " EP13_SIZE ,Generic RNDIS packeet size 13"
line.long 0x34 "USB1GENRNDISEP14,USB1 Generic RNDIS EP14 Size Register"
hexmask.long.tbyte 0x34 0.--16. 1. " EP14_SIZE ,Generic RNDIS packeet size 14"
line.long 0x38 "USB1GENRNDISEP15,USB1 Generic RNDIS EP15 Size Register"
hexmask.long.tbyte 0x38 0.--16. 1. " EP15_SIZE ,Generic RNDIS packeet size 15"
group.long 0xD0++0xB
line.long 0x00 "USB1AUTOREQ,USB1 Auto Req Register"
bitfld.long 0x00 28.--29. " RX15_AUTOREQ ,RX endpoint 15 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 26.--27. " RX14_AUTOREQ ,RX endpoint 14 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 24.--25. " RX13_AUTOREQ ,RX endpoint 13 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 22.--23. " RX12_AUTOREQ ,RX endpoint 12 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 20.--21. " RX11_AUTOREQ ,RX endpoint 11 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 18.--19. " RX10_AUTOREQ ,RX endpoint 10 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 16.--17. " RX9_AUTOREQ ,RX endpoint 9 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 14.--15. " RX8_AUTOREQ ,RX endpoint 8 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 12.--13. " RX7_AUTOREQ ,RX endpoint 7 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 10.--11. " RX6_AUTOREQ ,RX endpoint 6 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 8.--9. " RX5_AUTOREQ ,RX endpoint 5 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 6.--7. " RX4_AUTOREQ ,RX endpoint 4 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 4.--5. " RX3_AUTOREQ ,RX endpoint 3 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
bitfld.long 0x00 2.--3. " RX2_AUTOREQ ,RX endpoint 2 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
textline " "
bitfld.long 0x00 0.--1. " RX1_AUTOREQ ,RX endpoint 1 automatic IN token request generation enable" "Disabled,Enabled except EOP,Reserved,Enabled"
line.long 0x04 "USB1SRPFIXTIME,USB1 SRP Fix Time Register"
line.long 0x08 "USB1TDOWN,USB1 Teardown Register"
bitfld.long 0x08 31. " TX_TDOWN15 ,Transmit endpoint 15 teardown" "Disabled,Enabled"
bitfld.long 0x08 30. " TX_TDOWN14 ,Transmit endpoint 14 teardown" "Disabled,Enabled"
bitfld.long 0x08 29. " TX_TDOWN13 ,Transmit endpoint 13 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 28. " TX_TDOWN12 ,Transmit endpoint 12 teardown" "Disabled,Enabled"
bitfld.long 0x08 27. " TX_TDOWN11 ,Transmit endpoint 11 teardown" "Disabled,Enabled"
bitfld.long 0x08 26. " TX_TDOWN10 ,Transmit endpoint 10 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 25. " TX_TDOWN9 ,Transmit endpoint 9 teardown" "Disabled,Enabled"
bitfld.long 0x08 24. " TX_TDOWN8 ,Transmit endpoint 8 teardown" "Disabled,Enabled"
bitfld.long 0x08 23. " TX_TDOWN7 ,Transmit endpoint 7 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 22. " TX_TDOWN6 ,Transmit endpoint 6 teardown" "Disabled,Enabled"
bitfld.long 0x08 21. " TX_TDOWN5 ,Transmit endpoint 5 teardown" "Disabled,Enabled"
bitfld.long 0x08 20. " TX_TDOWN4 ,Transmit endpoint 4 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 19. " TX_TDOWN3 ,Transmit endpoint 3 teardown" "Disabled,Enabled"
bitfld.long 0x08 18. " TX_TDOWN2 ,Transmit endpoint 2 teardown" "Disabled,Enabled"
bitfld.long 0x08 17. " TX_TDOWN1 ,Transmit endpoint 1 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 15. " RX_TDOWN15 ,Receive endpoint 15 teardown" "Disabled,Enabled"
bitfld.long 0x08 14. " RX_TDOWN14 ,Receive endpoint 14 teardown" "Disabled,Enabled"
bitfld.long 0x08 13. " RX_TDOWN13 ,Receive endpoint 13 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 12. " RX_TDOWN12 ,Receive endpoint 12 teardown" "Disabled,Enabled"
bitfld.long 0x08 11. " RX_TDOWN11 ,Receive endpoint 11 teardown" "Disabled,Enabled"
bitfld.long 0x08 10. " RX_TDOWN10 ,Receive endpoint 10 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 9. " RX_TDOWN9 ,Receive endpoint 9 teardown" "Disabled,Enabled"
bitfld.long 0x08 8. " RX_TDOWN8 ,Receive endpoint 8 teardown" "Disabled,Enabled"
bitfld.long 0x08 7. " RX_TDOWN7 ,Receive endpoint 7 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 6. " RX_TDOWN6 ,Receive endpoint 6 teardown" "Disabled,Enabled"
bitfld.long 0x08 5. " RX_TDOWN5 ,Receive endpoint 5 teardown" "Disabled,Enabled"
bitfld.long 0x08 4. " RX_TDOWN4 ,Receive endpoint 4 teardown" "Disabled,Enabled"
textline " "
bitfld.long 0x08 3. " RX_TDOWN3 ,Receive endpoint 3 teardown" "Disabled,Enabled"
bitfld.long 0x08 2. " RX_TDOWN2 ,Receive endpoint 2 teardown" "Disabled,Enabled"
bitfld.long 0x08 1. " RX_TDOWN1 ,Receive endpoint 1 teardown" "Disabled,Enabled"
sif cpuis("DM814?DSP")
group.long 0xDC++0x03
line.long 0x00 "USB1THRESXDMA,USB1 Threshold XDMA Idle Register"
hexmask.long.byte 0x00 0.--7. 0x1 " THRES_XDMA_IDLE ,Threshold XDMA Idle cycle parameter"
endif
group.long 0xE0++0x0B
line.long 0x00 "USB1UTMI,USB1 PHY UTMI Register"
bitfld.long 0x00 23. " TXBITSTUFFEN ,Input for signal txbitstuffen" "Low,High"
sif !cpuis("DM814?DSP")
bitfld.long 0x00 22. " TXBITSTUFFENH ,Input for signal txbitstuffenh" "Low,High"
textline " "
bitfld.long 0x00 21. " OTGDISABLE ,Input for signal otgdisable" "Low,High"
bitfld.long 0x00 20. " VBUSVLDEXTSEL ,Input for signal vbusvldextsel" "Low,High"
textline " "
bitfld.long 0x00 19. " VBUSVLDEXT ,Input for signal vbusvldext" "Low,High"
endif
bitfld.long 0x00 18. " TXENABLEN ,Input for signal txenablen" "Low,High"
sif !cpuis("DM814?DSP")
textline " "
bitfld.long 0x00 17. " FSXCVROWNER ,Input for signal fsxcvrowner" "Low,High"
bitfld.long 0x00 16. " TXVALIDH ,Input for signal txvalidh" "Low,High"
textline " "
hexmask.long.byte 0x00 8.--15. 1. " DATAINH ,Input for signal datainh"
bitfld.long 0x00 2. " WORDINTERFACE ,Input for signal wordinterface" "Low,High"
textline " "
bitfld.long 0x00 1. " FSDATAEXT ,Input for signal fsdataext" "Low,High"
bitfld.long 0x00 0. " FSSE0EXT ,Input for signal fsse0ext" "Low,High"
endif
line.long 0x04 "USB1UTMILB,USB1 MGC UTMI Loopback Register"
sif (cpuis("DM814?DSP")||cpuis("DRA62*")||cpuis("AM335*"))
rbitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
rbitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
textline " "
rbitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
rbitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
textline " "
rbitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
rbitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
textline " "
rbitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
rbitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
textline " "
rbitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
rbitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
textline " "
rbitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
else
bitfld.long 0x04 28. " SUSPENDM ,LB test value for suspendm" "Low,High"
bitfld.long 0x04 26.--27. " OPMODE ,LB test value for opmode" "0,1,2,3"
textline " "
bitfld.long 0x04 25. " TXVALID ,LB test value for txvalid" "Low,High"
bitfld.long 0x04 23.--24. " XCVRSEL ,LB test value for xcvrsel" "0,1,2,3"
textline " "
bitfld.long 0x04 22. " TERMSEL ,LB test value for termsel" "Low,High"
bitfld.long 0x04 21. " DRVVBUS ,LB test value for drvvbus" "Low,High"
textline " "
bitfld.long 0x04 20. " CHRGVBUS ,LB test value for chrgvbus" "Low,High"
bitfld.long 0x04 19. " DISCHRGVBUS ,LB test value for dischrgvbus" "Low,High"
textline " "
bitfld.long 0x04 18. " DPPULLDOWN ,LB test value for dppulldown" "Low,High"
bitfld.long 0x04 17. " DMPULLDOWN ,LB test value for dmpulldown" "Low,High"
textline " "
bitfld.long 0x04 16. " IDPULLUP ,LB test value for idpullup" "Low,High"
endif
bitfld.long 0x04 11. " IDDIG ,LB test value for iddig" "Low,High"
textline " "
bitfld.long 0x04 10. " HOSTDISCON ,LB test value for hostdiscon" "Low,High"
bitfld.long 0x04 9. " SESSEND ,LB test value for sessend" "Low,High"
textline " "
bitfld.long 0x04 8. " AVALID ,LB test value for avalid" "Low,High"
bitfld.long 0x04 7. " VBUSVALID ,LB test value for vbusvalid" "Low,High"
textline " "
bitfld.long 0x04 6. " RXERROR ,LB test value for rxerror" "Low,High"
bitfld.long 0x04 2.--3. " LINESTATE ,LB test value for linestate" "0,1,2,3"
line.long 0x08 "USB1MODE,USB1 Mode Register"
bitfld.long 0x08 8. " IDDIG ,MGC input value for IDDIG" "A-type,B-type"
textline " "
sif (cpuis("AM335*"))
bitfld.long 0x08 7. " IDDIG_MUX ,Multiplexer control for IDDIG signal going to the controller" "From PHY,From bit 8 (IDDIG)"
textline " "
endif
bitfld.long 0x08 1. " PHY_TEST ,PHY test" "Disabled,Enabled"
textline " "
bitfld.long 0x08 0. " LOOPBACK ,Loopback test mode" "Disabled,Enabled"
width 0xb
tree.end
tree.end
tree "CPPI DMA"
base ad:0x47402000
width 18.
tree "CPPI DMA Registers"
rgroup.long 0x00++0x3
line.long 0x0 "DMAREVID,CPPI DMA Revision Register"
hexmask.long.word 0x00 16.--29. 1. " MODID ,Module ID field"
bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7"
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision"
group.long 0x04++0x7
line.long 0x00 "TDFDQ,CPPI DMA Teardown Free Descriptor Queue Control Register"
bitfld.long 0x00 12.--13. " TD_DESC_QMGR ,Teardown descriptor queue menager select" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TD_DESC_QNUM ,Teardown descriptor queue number select"
line.long 0x04 "DMAEMU,CPPI DMA Emulation Control Register"
bitfld.long 0x04 1. " SOFT ,Force emulation pause request low" "Forced,Not forced"
bitfld.long 0x04 0. " FREE ,Emulation suspend enable" "Disabled,Enabled"
sif ((cpuis("DRA6*"))||(cpuis("C674*"))||(cpu()=="C6A8148")||(cpu()=="C6A8147")||(cpu()=="C6A8143")||(cpu()=="DM8148")||(cpu()=="DM8147")||(cpu()=="AM3874")||(cpu()=="AM3872"))
group.long 0x10++0x07
line.long 0x00 "DMAMEM1BA,CPPI Mem1 Base Address Register"
hexmask.long.word 0x00 16.--31. 1. " MEM1_BASE ,CPPI mem1 base address"
line.long 0x04 "DMAMEM1MASK,CPPI Mem1 Mask Address Register"
hexmask.long.word 0x04 16.--31. 1. " MEM1_MASK ,CPPI mem1 mask address"
endif
group.long 0x800++0x3
line.long 0x00 "TXGCR[0],CPPI DMA Transmit Channel 0 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x800+0x08)++0x3
line.long 0x00 "RXGCR[0],CPPI DMA Receive Channel 0 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x800+0x0C)++0x3
line.long 0x00 "RXHPCRA[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x800+0x10)++0x3
line.long 0x00 "RXHPCRB[0],CPPI DMA Receive Channel 0 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x820++0x3
line.long 0x00 "TXGCR[1],CPPI DMA Transmit Channel 1 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x820+0x08)++0x3
line.long 0x00 "RXGCR[1],CPPI DMA Receive Channel 1 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x820+0x0C)++0x3
line.long 0x00 "RXHPCRA[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x820+0x10)++0x3
line.long 0x00 "RXHPCRB[1],CPPI DMA Receive Channel 1 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x840++0x3
line.long 0x00 "TXGCR[2],CPPI DMA Transmit Channel 2 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x840+0x08)++0x3
line.long 0x00 "RXGCR[2],CPPI DMA Receive Channel 2 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x840+0x0C)++0x3
line.long 0x00 "RXHPCRA[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x840+0x10)++0x3
line.long 0x00 "RXHPCRB[2],CPPI DMA Receive Channel 2 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x860++0x3
line.long 0x00 "TXGCR[3],CPPI DMA Transmit Channel 3 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x860+0x08)++0x3
line.long 0x00 "RXGCR[3],CPPI DMA Receive Channel 3 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x860+0x0C)++0x3
line.long 0x00 "RXHPCRA[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x860+0x10)++0x3
line.long 0x00 "RXHPCRB[3],CPPI DMA Receive Channel 3 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x880++0x3
line.long 0x00 "TXGCR[4],CPPI DMA Transmit Channel 4 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x880+0x08)++0x3
line.long 0x00 "RXGCR[4],CPPI DMA Receive Channel 4 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x880+0x0C)++0x3
line.long 0x00 "RXHPCRA[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x880+0x10)++0x3
line.long 0x00 "RXHPCRB[4],CPPI DMA Receive Channel 4 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x8A0++0x3
line.long 0x00 "TXGCR[5],CPPI DMA Transmit Channel 5 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x8A0+0x08)++0x3
line.long 0x00 "RXGCR[5],CPPI DMA Receive Channel 5 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x8A0+0x0C)++0x3
line.long 0x00 "RXHPCRA[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x8A0+0x10)++0x3
line.long 0x00 "RXHPCRB[5],CPPI DMA Receive Channel 5 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x8C0++0x3
line.long 0x00 "TXGCR[6],CPPI DMA Transmit Channel 6 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x8C0+0x08)++0x3
line.long 0x00 "RXGCR[6],CPPI DMA Receive Channel 6 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x8C0+0x0C)++0x3
line.long 0x00 "RXHPCRA[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x8C0+0x10)++0x3
line.long 0x00 "RXHPCRB[6],CPPI DMA Receive Channel 6 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x8E0++0x3
line.long 0x00 "TXGCR[7],CPPI DMA Transmit Channel 7 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x8E0+0x08)++0x3
line.long 0x00 "RXGCR[7],CPPI DMA Receive Channel 7 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x8E0+0x0C)++0x3
line.long 0x00 "RXHPCRA[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x8E0+0x10)++0x3
line.long 0x00 "RXHPCRB[7],CPPI DMA Receive Channel 7 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x900++0x3
line.long 0x00 "TXGCR[8],CPPI DMA Transmit Channel 8 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x900+0x08)++0x3
line.long 0x00 "RXGCR[8],CPPI DMA Receive Channel 8 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x900+0x0C)++0x3
line.long 0x00 "RXHPCRA[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x900+0x10)++0x3
line.long 0x00 "RXHPCRB[8],CPPI DMA Receive Channel 8 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x920++0x3
line.long 0x00 "TXGCR[9],CPPI DMA Transmit Channel 9 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x920+0x08)++0x3
line.long 0x00 "RXGCR[9],CPPI DMA Receive Channel 9 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x920+0x0C)++0x3
line.long 0x00 "RXHPCRA[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x920+0x10)++0x3
line.long 0x00 "RXHPCRB[9],CPPI DMA Receive Channel 9 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x940++0x3
line.long 0x00 "TXGCR[10],CPPI DMA Transmit Channel 10 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x940+0x08)++0x3
line.long 0x00 "RXGCR[10],CPPI DMA Receive Channel 10 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x940+0x0C)++0x3
line.long 0x00 "RXHPCRA[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x940+0x10)++0x3
line.long 0x00 "RXHPCRB[10],CPPI DMA Receive Channel 10 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x960++0x3
line.long 0x00 "TXGCR[11],CPPI DMA Transmit Channel 11 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x960+0x08)++0x3
line.long 0x00 "RXGCR[11],CPPI DMA Receive Channel 11 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x960+0x0C)++0x3
line.long 0x00 "RXHPCRA[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x960+0x10)++0x3
line.long 0x00 "RXHPCRB[11],CPPI DMA Receive Channel 11 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x980++0x3
line.long 0x00 "TXGCR[12],CPPI DMA Transmit Channel 12 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x980+0x08)++0x3
line.long 0x00 "RXGCR[12],CPPI DMA Receive Channel 12 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x980+0x0C)++0x3
line.long 0x00 "RXHPCRA[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x980+0x10)++0x3
line.long 0x00 "RXHPCRB[12],CPPI DMA Receive Channel 12 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x9A0++0x3
line.long 0x00 "TXGCR[13],CPPI DMA Transmit Channel 13 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x9A0+0x08)++0x3
line.long 0x00 "RXGCR[13],CPPI DMA Receive Channel 13 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x9A0+0x0C)++0x3
line.long 0x00 "RXHPCRA[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x9A0+0x10)++0x3
line.long 0x00 "RXHPCRB[13],CPPI DMA Receive Channel 13 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x9C0++0x3
line.long 0x00 "TXGCR[14],CPPI DMA Transmit Channel 14 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x9C0+0x08)++0x3
line.long 0x00 "RXGCR[14],CPPI DMA Receive Channel 14 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x9C0+0x0C)++0x3
line.long 0x00 "RXHPCRA[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x9C0+0x10)++0x3
line.long 0x00 "RXHPCRB[14],CPPI DMA Receive Channel 14 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0x9E0++0x3
line.long 0x00 "TXGCR[15],CPPI DMA Transmit Channel 15 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0x9E0+0x08)++0x3
line.long 0x00 "RXGCR[15],CPPI DMA Receive Channel 15 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0x9E0+0x0C)++0x3
line.long 0x00 "RXHPCRA[15],CPPI DMA Receive Channel 15 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0x9E0+0x10)++0x3
line.long 0x00 "RXHPCRB[15],CPPI DMA Receive Channel 15 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xA00++0x3
line.long 0x00 "TXGCR[16],CPPI DMA Transmit Channel 16 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xA00+0x08)++0x3
line.long 0x00 "RXGCR[16],CPPI DMA Receive Channel 16 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xA00+0x0C)++0x3
line.long 0x00 "RXHPCRA[16],CPPI DMA Receive Channel 16 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xA00+0x10)++0x3
line.long 0x00 "RXHPCRB[16],CPPI DMA Receive Channel 16 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xA20++0x3
line.long 0x00 "TXGCR[17],CPPI DMA Transmit Channel 17 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xA20+0x08)++0x3
line.long 0x00 "RXGCR[17],CPPI DMA Receive Channel 17 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xA20+0x0C)++0x3
line.long 0x00 "RXHPCRA[17],CPPI DMA Receive Channel 17 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xA20+0x10)++0x3
line.long 0x00 "RXHPCRB[17],CPPI DMA Receive Channel 17 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xA40++0x3
line.long 0x00 "TXGCR[18],CPPI DMA Transmit Channel 18 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xA40+0x08)++0x3
line.long 0x00 "RXGCR[18],CPPI DMA Receive Channel 18 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xA40+0x0C)++0x3
line.long 0x00 "RXHPCRA[18],CPPI DMA Receive Channel 18 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xA40+0x10)++0x3
line.long 0x00 "RXHPCRB[18],CPPI DMA Receive Channel 18 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xA60++0x3
line.long 0x00 "TXGCR[19],CPPI DMA Transmit Channel 19 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xA60+0x08)++0x3
line.long 0x00 "RXGCR[19],CPPI DMA Receive Channel 19 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xA60+0x0C)++0x3
line.long 0x00 "RXHPCRA[19],CPPI DMA Receive Channel 19 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xA60+0x10)++0x3
line.long 0x00 "RXHPCRB[19],CPPI DMA Receive Channel 19 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xA80++0x3
line.long 0x00 "TXGCR[20],CPPI DMA Transmit Channel 20 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xA80+0x08)++0x3
line.long 0x00 "RXGCR[20],CPPI DMA Receive Channel 20 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xA80+0x0C)++0x3
line.long 0x00 "RXHPCRA[20],CPPI DMA Receive Channel 20 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xA80+0x10)++0x3
line.long 0x00 "RXHPCRB[20],CPPI DMA Receive Channel 20 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xAA0++0x3
line.long 0x00 "TXGCR[21],CPPI DMA Transmit Channel 21 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xAA0+0x08)++0x3
line.long 0x00 "RXGCR[21],CPPI DMA Receive Channel 21 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xAA0+0x0C)++0x3
line.long 0x00 "RXHPCRA[21],CPPI DMA Receive Channel 21 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xAA0+0x10)++0x3
line.long 0x00 "RXHPCRB[21],CPPI DMA Receive Channel 21 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xAC0++0x3
line.long 0x00 "TXGCR[22],CPPI DMA Transmit Channel 22 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xAC0+0x08)++0x3
line.long 0x00 "RXGCR[22],CPPI DMA Receive Channel 22 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xAC0+0x0C)++0x3
line.long 0x00 "RXHPCRA[22],CPPI DMA Receive Channel 22 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xAC0+0x10)++0x3
line.long 0x00 "RXHPCRB[22],CPPI DMA Receive Channel 22 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xAE0++0x3
line.long 0x00 "TXGCR[23],CPPI DMA Transmit Channel 23 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xAE0+0x08)++0x3
line.long 0x00 "RXGCR[23],CPPI DMA Receive Channel 23 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xAE0+0x0C)++0x3
line.long 0x00 "RXHPCRA[23],CPPI DMA Receive Channel 23 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xAE0+0x10)++0x3
line.long 0x00 "RXHPCRB[23],CPPI DMA Receive Channel 23 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xB00++0x3
line.long 0x00 "TXGCR[24],CPPI DMA Transmit Channel 24 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xB00+0x08)++0x3
line.long 0x00 "RXGCR[24],CPPI DMA Receive Channel 24 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xB00+0x0C)++0x3
line.long 0x00 "RXHPCRA[24],CPPI DMA Receive Channel 24 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xB00+0x10)++0x3
line.long 0x00 "RXHPCRB[24],CPPI DMA Receive Channel 24 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xB20++0x3
line.long 0x00 "TXGCR[25],CPPI DMA Transmit Channel 25 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xB20+0x08)++0x3
line.long 0x00 "RXGCR[25],CPPI DMA Receive Channel 25 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xB20+0x0C)++0x3
line.long 0x00 "RXHPCRA[25],CPPI DMA Receive Channel 25 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xB20+0x10)++0x3
line.long 0x00 "RXHPCRB[25],CPPI DMA Receive Channel 25 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xB40++0x3
line.long 0x00 "TXGCR[26],CPPI DMA Transmit Channel 26 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xB40+0x08)++0x3
line.long 0x00 "RXGCR[26],CPPI DMA Receive Channel 26 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xB40+0x0C)++0x3
line.long 0x00 "RXHPCRA[26],CPPI DMA Receive Channel 26 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xB40+0x10)++0x3
line.long 0x00 "RXHPCRB[26],CPPI DMA Receive Channel 26 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xB60++0x3
line.long 0x00 "TXGCR[27],CPPI DMA Transmit Channel 27 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xB60+0x08)++0x3
line.long 0x00 "RXGCR[27],CPPI DMA Receive Channel 27 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xB60+0x0C)++0x3
line.long 0x00 "RXHPCRA[27],CPPI DMA Receive Channel 27 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xB60+0x10)++0x3
line.long 0x00 "RXHPCRB[27],CPPI DMA Receive Channel 27 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xB80++0x3
line.long 0x00 "TXGCR[28],CPPI DMA Transmit Channel 28 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xB80+0x08)++0x3
line.long 0x00 "RXGCR[28],CPPI DMA Receive Channel 28 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xB80+0x0C)++0x3
line.long 0x00 "RXHPCRA[28],CPPI DMA Receive Channel 28 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xB80+0x10)++0x3
line.long 0x00 "RXHPCRB[28],CPPI DMA Receive Channel 28 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
group.long 0xBA0++0x3
line.long 0x00 "TXGCR[29],CPPI DMA Transmit Channel 29 Global Configuration Register"
bitfld.long 0x00 31. " TX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " TX_TEARDOWN ,Channel to be torn down requested" "Not requested,Requested"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " TX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
textline " "
endif
bitfld.long 0x00 12.--13. " TX_DEFAULT_QMGR ,Default queue manager number" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " TX_DEFAULT_QNUM ,Default queue number within the selected queue manager"
group.long (0xBA0+0x08)++0x3
line.long 0x00 "RXGCR[29],CPPI DMA Receive Channel 29 Global Configuration Register"
bitfld.long 0x00 31. " RX_ENABLE ,Channel control" "Disabled,Enabled"
bitfld.long 0x00 30. " RX_TEARDOWN ,Receive teardown operation is completed" "Not completed,Completed"
textline " "
sif cpuis("DM814?DSP")
bitfld.long 0x00 29. " RX_PAUSE ,Channel CPPI DMA suspend" "Not suspended,Suspended"
bitfld.long 0x00 26.--28. " RX_MAX_BUFFER_CNT ,Maximal buffer count" "Disabled,1 buffer,2 buffers,3 buffers,4 buffers,?..."
textline " "
endif
bitfld.long 0x00 24. " RX_ERROR_HANDLING ,Error handling mode for the channel" "Dropping packet and reclaiming,Subsequent retry"
textline " "
hexmask.long.byte 0x00 16.--23. 1. " RX_SOP_OFFSET ,Number of bytes that are to be skipped in the SOP buffer"
textline " "
bitfld.long 0x00 14.--15. " RX_DEFAULT_DESC_TYPE ,Default descriptor type to use" "Reserved,Host,?..."
bitfld.long 0x00 12.--13. " RX_DEFAULT_RQ_QMGR ,Default receive queue manager that this channel should use" "0,1,2,3"
textline " "
hexmask.long.word 0x00 0.--11. 1. " RX_DEFAULT_RQ_QNUM ,Default receive queue that this channel should use"
wgroup.long (0xBA0+0x0C)++0x3
line.long 0x00 "RXHPCRA[29],CPPI DMA Receive Channel 29 Host Packet Configuration Register A"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ1_QMGR ,Specifies which buffer manager should be used for the second receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ1_QNUM ,Specifies which free descriptor/buffer pool should be used for the second receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ0_QMGR ,Specifies which buffer manager should be used for the first receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ0_QNUM ,Specifies which free descriptor/buffer pool should be used for the first receive buffer"
wgroup.long (0xBA0+0x10)++0x3
line.long 0x00 "RXHPCRB[29],CPPI DMA Receive Channel 29 Host Packet Configuration Register B"
bitfld.long 0x00 28.--29. " RX_HOST_FDQ3_QMGR ,Specifies which buffer manager should be used for the fourth receive buffer" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " RX_HOST_FDQ3_QNUM ,Specifies which free descriptor/buffer pool should be used for the fourth receive buffer"
textline " "
bitfld.long 0x00 12.--13. " RX_HOST_FDQ2_QMGR ,Specifies which buffer manager should be used for the third receive buffer" "0,1,2,3"
hexmask.long.word 0x00 0.--11. 1. " RX_HOST_FDQ2_QNUM ,Specifies which free descriptor/buffer pool should be used for the third receive buffer"
tree.end
tree "CPPI DMA Scheduler Registers"
width 16.
group.long 0x1000++0x3
line.long 0x00 "DMA_SCHED_CTRL,CPPI DMA Scheduler Control Register"
bitfld.long 0x00 31. " ENABLE ,Scheduler enable" "Disabled,Enabled"
textline " "
hexmask.long.byte 0x00 0.--7. 1. " LAST_ENTRY ,Last valid entry in the scheduler table"
width 11.
wgroup.long 0x1800++0xff
line.long 0x0 "WORD[0],CPPI DMA Scheduler Table Word 0 Register"
bitfld.long 0x0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4 "WORD[1],CPPI DMA Scheduler Table Word 1 Register"
bitfld.long 0x4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x8 "WORD[2],CPPI DMA Scheduler Table Word 2 Register"
bitfld.long 0x8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC "WORD[3],CPPI DMA Scheduler Table Word 3 Register"
bitfld.long 0xC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "WORD[4],CPPI DMA Scheduler Table Word 4 Register"
bitfld.long 0x10 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x10 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x10 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x10 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x10 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x10 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x10 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x10 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "WORD[5],CPPI DMA Scheduler Table Word 5 Register"
bitfld.long 0x14 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x14 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x14 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x14 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x14 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x14 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x14 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x14 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "WORD[6],CPPI DMA Scheduler Table Word 6 Register"
bitfld.long 0x18 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x18 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x18 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x18 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x18 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x18 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x18 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x18 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "WORD[7],CPPI DMA Scheduler Table Word 7 Register"
bitfld.long 0x1C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x1C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x1C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x1C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x1C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x1C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x1C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x1C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x20 "WORD[8],CPPI DMA Scheduler Table Word 8 Register"
bitfld.long 0x20 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x20 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x20 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x20 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x20 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x20 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x20 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x20 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x24 "WORD[9],CPPI DMA Scheduler Table Word 9 Register"
bitfld.long 0x24 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x24 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x24 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x24 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x24 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x24 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x24 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x24 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x28 "WORD[10],CPPI DMA Scheduler Table Word 10 Register"
bitfld.long 0x28 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x28 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x28 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x28 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x28 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x28 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x28 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x28 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x2C "WORD[11],CPPI DMA Scheduler Table Word 11 Register"
bitfld.long 0x2C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x2C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x2C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x2C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x2C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x2C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x2C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x2C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "WORD[12],CPPI DMA Scheduler Table Word 12 Register"
bitfld.long 0x30 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x30 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x30 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x30 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x30 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x30 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x30 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x30 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "WORD[13],CPPI DMA Scheduler Table Word 13 Register"
bitfld.long 0x34 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x34 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x34 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x34 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x34 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x34 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x34 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x34 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "WORD[14],CPPI DMA Scheduler Table Word 14 Register"
bitfld.long 0x38 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x38 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x38 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x38 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x38 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x38 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x38 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x38 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "WORD[15],CPPI DMA Scheduler Table Word 15 Register"
bitfld.long 0x3C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x3C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x3C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x3C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x3C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x3C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x3C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x3C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "WORD[16],CPPI DMA Scheduler Table Word 16 Register"
bitfld.long 0x40 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x40 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x40 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x40 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x40 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x40 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x40 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x40 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "WORD[17],CPPI DMA Scheduler Table Word 17 Register"
bitfld.long 0x44 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x44 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x44 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x44 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x44 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x44 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x44 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x44 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x48 "WORD[18],CPPI DMA Scheduler Table Word 18 Register"
bitfld.long 0x48 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x48 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x48 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x48 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x48 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x48 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x48 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x48 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x4C "WORD[19],CPPI DMA Scheduler Table Word 19 Register"
bitfld.long 0x4C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x4C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x4C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x50 "WORD[20],CPPI DMA Scheduler Table Word 20 Register"
bitfld.long 0x50 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x50 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x50 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x50 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x50 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x50 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x50 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x50 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x54 "WORD[21],CPPI DMA Scheduler Table Word 21 Register"
bitfld.long 0x54 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x54 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x54 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x54 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x54 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x54 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x54 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x54 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x58 "WORD[22],CPPI DMA Scheduler Table Word 22 Register"
bitfld.long 0x58 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x58 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x58 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x58 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x58 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x58 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x58 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x58 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x5C "WORD[23],CPPI DMA Scheduler Table Word 23 Register"
bitfld.long 0x5C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x5C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x5C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x5C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x5C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x5C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x5C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x5C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "WORD[24],CPPI DMA Scheduler Table Word 24 Register"
bitfld.long 0x60 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x60 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x60 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x60 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x60 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x60 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x60 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x60 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "WORD[25],CPPI DMA Scheduler Table Word 25 Register"
bitfld.long 0x64 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x64 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x64 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x64 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x64 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x64 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x64 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x64 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "WORD[26],CPPI DMA Scheduler Table Word 26 Register"
bitfld.long 0x68 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x68 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x68 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x68 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x68 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x68 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x68 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x68 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "WORD[27],CPPI DMA Scheduler Table Word 27 Register"
bitfld.long 0x6C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x6C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x6C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x6C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x6C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x6C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x6C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x6C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "WORD[28],CPPI DMA Scheduler Table Word 28 Register"
bitfld.long 0x70 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x70 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x70 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x70 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x70 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x70 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x70 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x70 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "WORD[29],CPPI DMA Scheduler Table Word 29 Register"
bitfld.long 0x74 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x74 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x74 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x74 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x74 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x74 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x74 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x74 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "WORD[30],CPPI DMA Scheduler Table Word 30 Register"
bitfld.long 0x78 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x78 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x78 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x78 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x78 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x78 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x78 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x78 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x7C "WORD[31],CPPI DMA Scheduler Table Word 31 Register"
bitfld.long 0x7C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x7C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x7C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x7C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x7C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x7C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x7C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x7C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "WORD[32],CPPI DMA Scheduler Table Word 32 Register"
bitfld.long 0x80 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x80 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x80 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x80 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x80 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x80 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x80 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x80 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "WORD[33],CPPI DMA Scheduler Table Word 33 Register"
bitfld.long 0x84 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x84 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x84 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x84 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x84 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x84 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x84 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x84 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x88 "WORD[34],CPPI DMA Scheduler Table Word 34 Register"
bitfld.long 0x88 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x88 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x88 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x88 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x88 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x88 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x88 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x88 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x8C "WORD[35],CPPI DMA Scheduler Table Word 35 Register"
bitfld.long 0x8C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x8C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x8C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x90 "WORD[36],CPPI DMA Scheduler Table Word 36 Register"
bitfld.long 0x90 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x90 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x90 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x90 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x90 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x90 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x90 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x90 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x94 "WORD[37],CPPI DMA Scheduler Table Word 37 Register"
bitfld.long 0x94 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x94 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x94 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x94 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x94 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x94 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x94 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x94 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x98 "WORD[38],CPPI DMA Scheduler Table Word 38 Register"
bitfld.long 0x98 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x98 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x98 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x98 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x98 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x98 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x98 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x98 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x9C "WORD[39],CPPI DMA Scheduler Table Word 39 Register"
bitfld.long 0x9C 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x9C 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x9C 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x9C 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x9C 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x9C 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0x9C 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0x9C 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "WORD[40],CPPI DMA Scheduler Table Word 40 Register"
bitfld.long 0xA0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "WORD[41],CPPI DMA Scheduler Table Word 41 Register"
bitfld.long 0xA4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA8 "WORD[42],CPPI DMA Scheduler Table Word 42 Register"
bitfld.long 0xA8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xA8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xA8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xAC "WORD[43],CPPI DMA Scheduler Table Word 43 Register"
bitfld.long 0xAC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xAC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xAC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xAC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xAC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xAC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xAC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xAC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xB0 "WORD[44],CPPI DMA Scheduler Table Word 44 Register"
bitfld.long 0xB0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xB4 "WORD[45],CPPI DMA Scheduler Table Word 45 Register"
bitfld.long 0xB4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xB8 "WORD[46],CPPI DMA Scheduler Table Word 46 Register"
bitfld.long 0xB8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xB8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xB8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xBC "WORD[47],CPPI DMA Scheduler Table Word 47 Register"
bitfld.long 0xBC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xBC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xBC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xBC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xBC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xBC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xBC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xBC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "WORD[48],CPPI DMA Scheduler Table Word 48 Register"
bitfld.long 0xC0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "WORD[49],CPPI DMA Scheduler Table Word 49 Register"
bitfld.long 0xC4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC8 "WORD[50],CPPI DMA Scheduler Table Word 50 Register"
bitfld.long 0xC8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xC8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xC8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xCC "WORD[51],CPPI DMA Scheduler Table Word 51 Register"
bitfld.long 0xCC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xCC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xCC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xCC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xCC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xCC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xCC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xCC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xD0 "WORD[52],CPPI DMA Scheduler Table Word 52 Register"
bitfld.long 0xD0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xD4 "WORD[53],CPPI DMA Scheduler Table Word 53 Register"
bitfld.long 0xD4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xD8 "WORD[54],CPPI DMA Scheduler Table Word 54 Register"
bitfld.long 0xD8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xD8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xD8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xDC "WORD[55],CPPI DMA Scheduler Table Word 55 Register"
bitfld.long 0xDC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xDC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xDC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xDC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xDC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xDC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xDC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xDC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "WORD[56],CPPI DMA Scheduler Table Word 56 Register"
bitfld.long 0xE0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "WORD[57],CPPI DMA Scheduler Table Word 57 Register"
bitfld.long 0xE4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE8 "WORD[58],CPPI DMA Scheduler Table Word 58 Register"
bitfld.long 0xE8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xE8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xE8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xEC "WORD[59],CPPI DMA Scheduler Table Word 59 Register"
bitfld.long 0xEC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xEC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xEC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xEC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xEC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xEC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xEC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xEC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF0 "WORD[60],CPPI DMA Scheduler Table Word 60 Register"
bitfld.long 0xF0 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF0 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF0 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF0 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF0 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF0 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF0 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF0 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF4 "WORD[61],CPPI DMA Scheduler Table Word 61 Register"
bitfld.long 0xF4 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF4 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF4 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF4 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF4 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF4 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF4 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF4 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF8 "WORD[62],CPPI DMA Scheduler Table Word 62 Register"
bitfld.long 0xF8 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF8 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF8 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF8 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF8 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF8 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xF8 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xF8 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xFC "WORD[63],CPPI DMA Scheduler Table Word 63 Register"
bitfld.long 0xFC 31. " ENTRY3_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xFC 24.--28. " ENTRY3_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xFC 23. " ENTRY2_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xFC 16.--20. " ENTRY2_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xFC 15. " ENTRY1_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xFC 8.--12. " ENTRY1_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
bitfld.long 0xFC 7. " ENTRY0_RXTX ,This entry is for a transmit or a receive channel" "Transmit,Receive"
bitfld.long 0xFC 0.--4. " ENTRY0_CHANNEL ,Channel number that is to be given an opportunity to transfer data" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
tree.end
width 14.
tree "CPPI DMA Queue Manager Registers"
rgroup.long 0x2000++0x03
line.long 0x00 "QMGRREVID,Queue Manager Revision Register"
bitfld.long 0x00 30.--31. " SCHEME ,Scheme that this register is compliant with" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. " FUNC ,Software compatible module family function"
textline " "
bitfld.long 0x00 11.--15. " REVRTL ,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 6.--7. " REVCUSTOM ,Custom revision" "0,1,2,3"
bitfld.long 0x00 0.--5. " RVMIN ,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
sif ((!cpuis("DM814?DSP"))&&(cpu()!="DM8165")&&(cpu()!="DM8166")&&(cpu()!="DM8167")&&(cpu()!="DM8168")&&(cpu()!="DM8165DSP")&&(cpu()!="DM8166DSP")&&(cpu()!="DM8167DSP")&&(cpu()!="DM8168DSP"))
group.long 0x2004++0x03
line.long 0x00 "QMGRRST,Queue Manager Reset Register"
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
textline " "
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
textline " "
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
endif
wgroup.long 0x2008++0x03
line.long 0x00 "DIVERSION,Queue Manager Queue Diversion Register"
bitfld.long 0x00 31. " HEAD_TAIL ,Contents should be merged on to the head or tail" "Head,Tail"
textline " "
hexmask.long.word 0x00 16.--29. 1. " DEST_QNUM ,Destination Queue Number"
textline " "
hexmask.long.word 0x00 0.--13. 1. " SOURCE_QNUM ,Source Queue Number"
hgroup.long 0x2020++0x03
hide.long 0x00 "FDBSC0,Queue Manager Free Descriptor/Buffer Starvation Count Register 0"
in
hgroup.long 0x2024++0x03
hide.long 0x00 "FDBSC1,Queue Manager Free Descriptor/Buffer Starvation Count Register 1"
in
hgroup.long 0x2028++0x03
hide.long 0x00 "FDBSC2,Queue Manager Free Descriptor/Buffer Starvation Count Register 2"
in
hgroup.long 0x202c++0x03
hide.long 0x00 "FDBSC3,Queue Manager Free Descriptor/Buffer Starvation Count Register 3"
in
hgroup.long 0x2030++0x03
hide.long 0x00 "FDBSC4,Queue Manager Free Descriptor/Buffer Starvation Count Register 4"
in
hgroup.long 0x2034++0x03
hide.long 0x00 "FDBSC5,Queue Manager Free Descriptor/Buffer Starvation Count Register 5"
in
hgroup.long 0x2038++0x03
hide.long 0x00 "FDBSC6,Queue Manager Free Descriptor/Buffer Starvation Count Register 6"
in
hgroup.long 0x203c++0x03
hide.long 0x00 "FDBSC7,Queue Manager Free Descriptor/Buffer Starvation Count Register 7"
in
group.long 0x2080++0xb
line.long 0x00 "LRAM0BASE,Queue Manager Linking RAM Region 0 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 2.--31. 0x4 " REGION0_BASE ,Linking RAM first region base address"
endif
line.long 0x04 "LRAM0SIZE,Queue Manager Linking RAM Region 0 Size Register"
sif (cpuis("DRA62*")||cpuis("DM814?DSP"))
hexmask.long.word 0x04 0.--13. 1. " REGION0_SIZE , Number of entries that are contained in the linking RAM region 0"
endif
line.long 0x08 "LRAM1BASE,Queue Manager Linking RAM Region 1 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x08 2.--31. 0x4 " REGION1_BASE ,Linking RAM second region base address"
endif
rgroup.long 0x2090++0xb
line.long 0x00 "PEND0,Queue Manager Queue Pending Register 0"
bitfld.long 0x00 31. " QPEND31 ,Queue 31 pending status" "Not pending,Pending"
bitfld.long 0x00 30. " QPEND30 ,Queue 30 pending status" "Not pending,Pending"
bitfld.long 0x00 29. " QPEND29 ,Queue 29 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 28. " QPEND28 ,Queue 28 pending status" "Not pending,Pending"
bitfld.long 0x00 27. " QPEND27 ,Queue 27 pending status" "Not pending,Pending"
bitfld.long 0x00 26. " QPEND26 ,Queue 26 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 25. " QPEND25 ,Queue 25 pending status" "Not pending,Pending"
bitfld.long 0x00 24. " QPEND24 ,Queue 24 pending status" "Not pending,Pending"
bitfld.long 0x00 23. " QPEND23 ,Queue 23 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 22. " QPEND22 ,Queue 22 pending status" "Not pending,Pending"
bitfld.long 0x00 21. " QPEND21 ,Queue 21 pending status" "Not pending,Pending"
bitfld.long 0x00 20. " QPEND20 ,Queue 20 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " QPEND19 ,Queue 19 pending status" "Not pending,Pending"
bitfld.long 0x00 18. " QPEND18 ,Queue 18 pending status" "Not pending,Pending"
bitfld.long 0x00 17. " QPEND17 ,Queue 17 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 16. " QPEND16 ,Queue 16 pending status" "Not pending,Pending"
bitfld.long 0x00 15. " QPEND15 ,Queue 15 pending status" "Not pending,Pending"
bitfld.long 0x00 14. " QPEND14 ,Queue 14 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 13. " QPEND13 ,Queue 13 pending status" "Not pending,Pending"
bitfld.long 0x00 12. " QPEND12 ,Queue 12 pending status" "Not pending,Pending"
bitfld.long 0x00 11. " QPEND11 ,Queue 11 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 10. " QPEND10 ,Queue 10 pending status" "Not pending,Pending"
bitfld.long 0x00 9. " QPEND9 ,Queue 9 pending status" "Not pending,Pending"
bitfld.long 0x00 8. " QPEND8 ,Queue 8 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 7. " QPEND7 ,Queue 7 pending status" "Not pending,Pending"
bitfld.long 0x00 6. " QPEND6 ,Queue 6 pending status" "Not pending,Pending"
bitfld.long 0x00 5. " QPEND5 ,Queue 5 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 4. " QPEND4 ,Queue 4 pending status" "Not pending,Pending"
bitfld.long 0x00 3. " QPEND3 ,Queue 3 pending status" "Not pending,Pending"
bitfld.long 0x00 2. " QPEND2 ,Queue 2 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 1. " QPEND1 ,Queue 1 pending status" "Not pending,Pending"
bitfld.long 0x00 0. " QPEND0 ,Queue 0 pending status" "Not pending,Pending"
line.long 0x04 "PEND1,Queue Manager Queue Pending Register 1"
bitfld.long 0x04 31. " QPEND63 ,Queue 63 pending status" "Not pending,Pending"
bitfld.long 0x04 30. " QPEND62 ,Queue 62 pending status" "Not pending,Pending"
bitfld.long 0x04 29. " QPEND61 ,Queue 61 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 28. " QPEND60 ,Queue 60 pending status" "Not pending,Pending"
bitfld.long 0x04 27. " QPEND59 ,Queue 59 pending status" "Not pending,Pending"
bitfld.long 0x04 26. " QPEND58 ,Queue 58 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 25. " QPEND57 ,Queue 57 pending status" "Not pending,Pending"
bitfld.long 0x04 24. " QPEND56 ,Queue 56 pending status" "Not pending,Pending"
bitfld.long 0x04 23. " QPEND55 ,Queue 55 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 22. " QPEND54 ,Queue 54 pending status" "Not pending,Pending"
bitfld.long 0x04 21. " QPEND53 ,Queue 53 pending status" "Not pending,Pending"
bitfld.long 0x04 20. " QPEND52 ,Queue 52 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 19. " QPEND51 ,Queue 51 pending status" "Not pending,Pending"
bitfld.long 0x04 18. " QPEND50 ,Queue 50 pending status" "Not pending,Pending"
bitfld.long 0x04 17. " QPEND49 ,Queue 49 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 16. " QPEND48 ,Queue 48 pending status" "Not pending,Pending"
bitfld.long 0x04 15. " QPEND47 ,Queue 47 pending status" "Not pending,Pending"
bitfld.long 0x04 14. " QPEND46 ,Queue 46 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 13. " QPEND45 ,Queue 45 pending status" "Not pending,Pending"
bitfld.long 0x04 12. " QPEND44 ,Queue 44 pending status" "Not pending,Pending"
bitfld.long 0x04 11. " QPEND43 ,Queue 43 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 10. " QPEND42 ,Queue 42 pending status" "Not pending,Pending"
bitfld.long 0x04 9. " QPEND41 ,Queue 41 pending status" "Not pending,Pending"
bitfld.long 0x04 8. " QPEND40 ,Queue 40 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 7. " QPEND39 ,Queue 39 pending status" "Not pending,Pending"
bitfld.long 0x04 6. " QPEND38 ,Queue 38 pending status" "Not pending,Pending"
bitfld.long 0x04 5. " QPEND37 ,Queue 37 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 4. " QPEND36 ,Queue 36 pending status" "Not pending,Pending"
bitfld.long 0x04 3. " QPEND35 ,Queue 35 pending status" "Not pending,Pending"
bitfld.long 0x04 2. " QPEND34 ,Queue 34 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 1. " QPEND33 ,Queue 33 pending status" "Not pending,Pending"
bitfld.long 0x04 0. " QPEND32 ,Queue 32 pending status" "Not pending,Pending"
line.long 0x08 "PEND2,Queue Manager Queue Pending Register 2"
bitfld.long 0x08 31. " QPEND95 ,Queue 95 pending status" "Not pending,Pending"
bitfld.long 0x08 30. " QPEND94 ,Queue 94 pending status" "Not pending,Pending"
bitfld.long 0x08 29. " QPEND93 ,Queue 93 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 28. " QPEND92 ,Queue 92 pending status" "Not pending,Pending"
bitfld.long 0x08 27. " QPEND91 ,Queue 91 pending status" "Not pending,Pending"
bitfld.long 0x08 26. " QPEND90 ,Queue 90 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 25. " QPEND89 ,Queue 89 pending status" "Not pending,Pending"
bitfld.long 0x08 24. " QPEND88 ,Queue 88 pending status" "Not pending,Pending"
bitfld.long 0x08 23. " QPEND87 ,Queue 87 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 22. " QPEND86 ,Queue 86 pending status" "Not pending,Pending"
bitfld.long 0x08 21. " QPEND85 ,Queue 85 pending status" "Not pending,Pending"
bitfld.long 0x08 20. " QPEND84 ,Queue 84 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 19. " QPEND83 ,Queue 83 pending status" "Not pending,Pending"
bitfld.long 0x08 18. " QPEND82 ,Queue 82 pending status" "Not pending,Pending"
bitfld.long 0x08 17. " QPEND81 ,Queue 81 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 16. " QPEND80 ,Queue 80 pending status" "Not pending,Pending"
bitfld.long 0x08 15. " QPEND79 ,Queue 79 pending status" "Not pending,Pending"
bitfld.long 0x08 14. " QPEND78 ,Queue 78 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 13. " QPEND77 ,Queue 77 pending status" "Not pending,Pending"
bitfld.long 0x08 12. " QPEND76 ,Queue 76 pending status" "Not pending,Pending"
bitfld.long 0x08 11. " QPEND75 ,Queue 75 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 10. " QPEND74 ,Queue 74 pending status" "Not pending,Pending"
bitfld.long 0x08 9. " QPEND73 ,Queue 73 pending status" "Not pending,Pending"
bitfld.long 0x08 8. " QPEND72 ,Queue 72 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 7. " QPEND71 ,Queue 71 pending status" "Not pending,Pending"
bitfld.long 0x08 6. " QPEND70 ,Queue 70 pending status" "Not pending,Pending"
bitfld.long 0x08 5. " QPEND69 ,Queue 69 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 4. " QPEND68 ,Queue 68 pending status" "Not pending,Pending"
bitfld.long 0x08 3. " QPEND67 ,Queue 67 pending status" "Not pending,Pending"
bitfld.long 0x08 2. " QPEND66 ,Queue 66 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x08 1. " QPEND65 ,Queue 65 pending status" "Not pending,Pending"
bitfld.long 0x08 0. " QPEND64 ,Queue 64 pending status" "Not pending,Pending"
sif ((!cpuis("DRA6*")||cpuis("DRA62*"))&&(!cpuis("C674*"))&&(cpu()!="C6A8148")&&(cpu()!="C6A8147")&&(cpu()!="C6A8143")&&(cpu()!="DM8148")&&(cpu()!="DM8147")&&(cpu()!="AM3874")&&(cpu()!="AM3872"))
rgroup.long 0x209c++0x7
line.long 0x00 "PEND3,Queue Manager Queue Pending Register 3"
bitfld.long 0x00 31. " QPEND127 ,Queue 127 pending status" "Not pending,Pending"
bitfld.long 0x00 30. " QPEND126 ,Queue 126 pending status" "Not pending,Pending"
bitfld.long 0x00 29. " QPEND125 ,Queue 125 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 28. " QPEND124 ,Queue 124 pending status" "Not pending,Pending"
bitfld.long 0x00 27. " QPEND123 ,Queue 123 pending status" "Not pending,Pending"
bitfld.long 0x00 26. " QPEND122 ,Queue 122 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 25. " QPEND121 ,Queue 121 pending status" "Not pending,Pending"
bitfld.long 0x00 24. " QPEND120 ,Queue 120 pending status" "Not pending,Pending"
bitfld.long 0x00 23. " QPEND119 ,Queue 119 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 22. " QPEND118 ,Queue 118 pending status" "Not pending,Pending"
bitfld.long 0x00 21. " QPEND117 ,Queue 117 pending status" "Not pending,Pending"
bitfld.long 0x00 20. " QPEND116 ,Queue 116 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 19. " QPEND115 ,Queue 115 pending status" "Not pending,Pending"
bitfld.long 0x00 18. " QPEND114 ,Queue 114 pending status" "Not pending,Pending"
bitfld.long 0x00 17. " QPEND113 ,Queue 113 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 16. " QPEND112 ,Queue 112 pending status" "Not pending,Pending"
bitfld.long 0x00 15. " QPEND111 ,Queue 111 pending status" "Not pending,Pending"
bitfld.long 0x00 14. " QPEND110 ,Queue 110 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 13. " QPEND109 ,Queue 109 pending status" "Not pending,Pending"
bitfld.long 0x00 12. " QPEND108 ,Queue 108 pending status" "Not pending,Pending"
bitfld.long 0x00 11. " QPEND107 ,Queue 107 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 10. " QPEND106 ,Queue 106 pending status" "Not pending,Pending"
bitfld.long 0x00 9. " QPEND105 ,Queue 105 pending status" "Not pending,Pending"
bitfld.long 0x00 8. " QPEND104 ,Queue 104 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 7. " QPEND103 ,Queue 103 pending status" "Not pending,Pending"
bitfld.long 0x00 6. " QPEND102 ,Queue 102 pending status" "Not pending,Pending"
bitfld.long 0x00 5. " QPEND101 ,Queue 101 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 4. " QPEND100 ,Queue 100 pending status" "Not pending,Pending"
bitfld.long 0x00 3. " QPEND99 ,Queue 99 pending status" "Not pending,Pending"
bitfld.long 0x00 2. " QPEND98 ,Queue 98 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x00 1. " QPEND97 ,Queue 97 pending status" "Not pending,Pending"
bitfld.long 0x00 0. " QPEND96 ,Queue 96 pending status" "Not pending,Pending"
line.long 0x04 "PEND4,Queue Manager Queue Pending Register 4"
sif cpu()=="DM8147DSP"||cpu()=="DM8148DSP"
bitfld.long 0x04 27. " QPEND155 ,Queue 155 pending status" "Not pending,Pending"
else
bitfld.long 0x04 31. " QPEND159 ,Queue 159 pending status" "Not pending,Pending"
bitfld.long 0x04 30. " QPEND158 ,Queue 158 pending status" "Not pending,Pending"
bitfld.long 0x04 29. " QPEND157 ,Queue 157 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 28. " QPEND156 ,Queue 156 pending status" "Not pending,Pending"
bitfld.long 0x04 27. " QPEND155 ,Queue 155 pending status" "Not pending,Pending"
endif
bitfld.long 0x04 26. " QPEND154 ,Queue 154 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 25. " QPEND153 ,Queue 153 pending status" "Not pending,Pending"
bitfld.long 0x04 24. " QPEND152 ,Queue 152 pending status" "Not pending,Pending"
bitfld.long 0x04 23. " QPEND151 ,Queue 151 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 22. " QPEND150 ,Queue 150 pending status" "Not pending,Pending"
bitfld.long 0x04 21. " QPEND149 ,Queue 149 pending status" "Not pending,Pending"
bitfld.long 0x04 20. " QPEND148 ,Queue 148 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 19. " QPEND147 ,Queue 147 pending status" "Not pending,Pending"
bitfld.long 0x04 18. " QPEND146 ,Queue 146 pending status" "Not pending,Pending"
bitfld.long 0x04 17. " QPEND145 ,Queue 145 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 16. " QPEND144 ,Queue 144 pending status" "Not pending,Pending"
bitfld.long 0x04 15. " QPEND143 ,Queue 143 pending status" "Not pending,Pending"
bitfld.long 0x04 14. " QPEND142 ,Queue 142 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 13. " QPEND141 ,Queue 141 pending status" "Not pending,Pending"
bitfld.long 0x04 12. " QPEND140 ,Queue 140 pending status" "Not pending,Pending"
bitfld.long 0x04 11. " QPEND139 ,Queue 139 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 10. " QPEND138 ,Queue 138 pending status" "Not pending,Pending"
bitfld.long 0x04 9. " QPEND137 ,Queue 137 pending status" "Not pending,Pending"
bitfld.long 0x04 8. " QPEND136 ,Queue 136 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 7. " QPEND135 ,Queue 135 pending status" "Not pending,Pending"
bitfld.long 0x04 6. " QPEND134 ,Queue 134 pending status" "Not pending,Pending"
bitfld.long 0x04 5. " QPEND133 ,Queue 133 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 4. " QPEND132 ,Queue 132 pending status" "Not pending,Pending"
bitfld.long 0x04 3. " QPEND131 ,Queue 131 pending status" "Not pending,Pending"
bitfld.long 0x04 2. " QPEND130 ,Queue 130 pending status" "Not pending,Pending"
textline " "
bitfld.long 0x04 1. " QPEND129 ,Queue 129 pending status" "Not pending,Pending"
bitfld.long 0x04 0. " QPEND128 ,Queue 128 pending status" "Not pending,Pending"
endif
group.long 0x3000++0x7
line.long 0x00 "QMEMRBASE[0],Queue Manager Memory Region 0 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 0 base address"
endif
line.long 0x04 "QMEMRCTRL[0],Queue Manager Memory Region 0 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 0 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3010++0x7
line.long 0x00 "QMEMRBASE[1],Queue Manager Memory Region 1 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 1 base address"
endif
line.long 0x04 "QMEMRCTRL[1],Queue Manager Memory Region 1 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 1 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3020++0x7
line.long 0x00 "QMEMRBASE[2],Queue Manager Memory Region 2 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 2 base address"
endif
line.long 0x04 "QMEMRCTRL[2],Queue Manager Memory Region 2 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 2 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3030++0x7
line.long 0x00 "QMEMRBASE[3],Queue Manager Memory Region 3 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 3 base address"
endif
line.long 0x04 "QMEMRCTRL[3],Queue Manager Memory Region 3 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 3 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3040++0x7
line.long 0x00 "QMEMRBASE[4],Queue Manager Memory Region 4 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 4 base address"
endif
line.long 0x04 "QMEMRCTRL[4],Queue Manager Memory Region 4 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 4 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3050++0x7
line.long 0x00 "QMEMRBASE[5],Queue Manager Memory Region 5 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 5 base address"
endif
line.long 0x04 "QMEMRCTRL[5],Queue Manager Memory Region 5 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 5 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3060++0x7
line.long 0x00 "QMEMRBASE[6],Queue Manager Memory Region 6 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 6 base address"
endif
line.long 0x04 "QMEMRCTRL[6],Queue Manager Memory Region 6 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 6 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3070++0x7
line.long 0x00 "QMEMRBASE[7],Queue Manager Memory Region 7 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 7 base address"
endif
line.long 0x04 "QMEMRCTRL[7],Queue Manager Memory Region 7 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 7 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3080++0x7
line.long 0x00 "QMEMRBASE[8],Queue Manager Memory Region 8 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 8 base address"
endif
line.long 0x04 "QMEMRCTRL[8],Queue Manager Memory Region 8 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 8 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x3090++0x7
line.long 0x00 "QMEMRBASE[9],Queue Manager Memory Region 9 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 9 base address"
endif
line.long 0x04 "QMEMRCTRL[9],Queue Manager Memory Region 9 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 9 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30A0++0x7
line.long 0x00 "QMEMRBASE[10],Queue Manager Memory Region 10 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 10 base address"
endif
line.long 0x04 "QMEMRCTRL[10],Queue Manager Memory Region 10 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 10 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30B0++0x7
line.long 0x00 "QMEMRBASE[11],Queue Manager Memory Region 11 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 11 base address"
endif
line.long 0x04 "QMEMRCTRL[11],Queue Manager Memory Region 11 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 11 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30C0++0x7
line.long 0x00 "QMEMRBASE[12],Queue Manager Memory Region 12 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 12 base address"
endif
line.long 0x04 "QMEMRCTRL[12],Queue Manager Memory Region 12 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 12 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30D0++0x7
line.long 0x00 "QMEMRBASE[13],Queue Manager Memory Region 13 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 13 base address"
endif
line.long 0x04 "QMEMRCTRL[13],Queue Manager Memory Region 13 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 13 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30E0++0x7
line.long 0x00 "QMEMRBASE[14],Queue Manager Memory Region 14 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 14 base address"
endif
line.long 0x04 "QMEMRCTRL[14],Queue Manager Memory Region 14 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 14 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
group.long 0x30F0++0x7
line.long 0x00 "QMEMRBASE[15],Queue Manager Memory Region 15 Base Address Register"
sif cpuis("DM814?DSP")
hexmask.long 0x00 5.--31. 0x20 " REG ,Memory region 15 base address"
endif
line.long 0x04 "QMEMRCTRL[15],Queue Manager Memory Region 15 Control Register"
hexmask.long.word 0x04 16.--29. 1. " START_INDEX ,Memory region 15 start index"
textline " "
bitfld.long 0x04 8.--11. " DESC_SIZE ,Size of each descriptor in this memory region" "32,64,128,256,512,1K,2K,4K,8K,?..."
bitfld.long 0x04 0.--2. " REG_SIZE ,Size of the memory region" "32,64,128,256,512,1K,2K,4K"
tree "Queues"
tree "Queue 0 Registers"
rgroup.long 0x4000++0xB
line.long 0x00 "CTRLA[0],Queue Manager Queue 0 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[0],Queue Manager Queue 0 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[0],Queue Manager Queue 0 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4000+0x0C)++0x3
line.long 0x00 "CTRLD[0],Queue Manager Queue 0 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5000++0xB
line.long 0x00 "QSTATA[0],Queue Manager Queue 0 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[0],Queue Manager Queue 0 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[0],Queue Manager Queue 0 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 1 Registers"
rgroup.long 0x4010++0xB
line.long 0x00 "CTRLA[1],Queue Manager Queue 1 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[1],Queue Manager Queue 1 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[1],Queue Manager Queue 1 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4010+0x0C)++0x3
line.long 0x00 "CTRLD[1],Queue Manager Queue 1 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5010++0xB
line.long 0x00 "QSTATA[1],Queue Manager Queue 1 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[1],Queue Manager Queue 1 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[1],Queue Manager Queue 1 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 2 Registers"
rgroup.long 0x4020++0xB
line.long 0x00 "CTRLA[2],Queue Manager Queue 2 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[2],Queue Manager Queue 2 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[2],Queue Manager Queue 2 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4020+0x0C)++0x3
line.long 0x00 "CTRLD[2],Queue Manager Queue 2 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5020++0xB
line.long 0x00 "QSTATA[2],Queue Manager Queue 2 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[2],Queue Manager Queue 2 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[2],Queue Manager Queue 2 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 3 Registers"
rgroup.long 0x4030++0xB
line.long 0x00 "CTRLA[3],Queue Manager Queue 3 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[3],Queue Manager Queue 3 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[3],Queue Manager Queue 3 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4030+0x0C)++0x3
line.long 0x00 "CTRLD[3],Queue Manager Queue 3 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5030++0xB
line.long 0x00 "QSTATA[3],Queue Manager Queue 3 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[3],Queue Manager Queue 3 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[3],Queue Manager Queue 3 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 4 Registers"
rgroup.long 0x4040++0xB
line.long 0x00 "CTRLA[4],Queue Manager Queue 4 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[4],Queue Manager Queue 4 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[4],Queue Manager Queue 4 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4040+0x0C)++0x3
line.long 0x00 "CTRLD[4],Queue Manager Queue 4 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5040++0xB
line.long 0x00 "QSTATA[4],Queue Manager Queue 4 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[4],Queue Manager Queue 4 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[4],Queue Manager Queue 4 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 5 Registers"
rgroup.long 0x4050++0xB
line.long 0x00 "CTRLA[5],Queue Manager Queue 5 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[5],Queue Manager Queue 5 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[5],Queue Manager Queue 5 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4050+0x0C)++0x3
line.long 0x00 "CTRLD[5],Queue Manager Queue 5 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5050++0xB
line.long 0x00 "QSTATA[5],Queue Manager Queue 5 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[5],Queue Manager Queue 5 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[5],Queue Manager Queue 5 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 6 Registers"
rgroup.long 0x4060++0xB
line.long 0x00 "CTRLA[6],Queue Manager Queue 6 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[6],Queue Manager Queue 6 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[6],Queue Manager Queue 6 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4060+0x0C)++0x3
line.long 0x00 "CTRLD[6],Queue Manager Queue 6 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5060++0xB
line.long 0x00 "QSTATA[6],Queue Manager Queue 6 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[6],Queue Manager Queue 6 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[6],Queue Manager Queue 6 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 7 Registers"
rgroup.long 0x4070++0xB
line.long 0x00 "CTRLA[7],Queue Manager Queue 7 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[7],Queue Manager Queue 7 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[7],Queue Manager Queue 7 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4070+0x0C)++0x3
line.long 0x00 "CTRLD[7],Queue Manager Queue 7 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5070++0xB
line.long 0x00 "QSTATA[7],Queue Manager Queue 7 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[7],Queue Manager Queue 7 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[7],Queue Manager Queue 7 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 8 Registers"
rgroup.long 0x4080++0xB
line.long 0x00 "CTRLA[8],Queue Manager Queue 8 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[8],Queue Manager Queue 8 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[8],Queue Manager Queue 8 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4080+0x0C)++0x3
line.long 0x00 "CTRLD[8],Queue Manager Queue 8 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5080++0xB
line.long 0x00 "QSTATA[8],Queue Manager Queue 8 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[8],Queue Manager Queue 8 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[8],Queue Manager Queue 8 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 9 Registers"
rgroup.long 0x4090++0xB
line.long 0x00 "CTRLA[9],Queue Manager Queue 9 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[9],Queue Manager Queue 9 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[9],Queue Manager Queue 9 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4090+0x0C)++0x3
line.long 0x00 "CTRLD[9],Queue Manager Queue 9 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5090++0xB
line.long 0x00 "QSTATA[9],Queue Manager Queue 9 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[9],Queue Manager Queue 9 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[9],Queue Manager Queue 9 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 10 Registers"
rgroup.long 0x40A0++0xB
line.long 0x00 "CTRLA[10],Queue Manager Queue 10 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[10],Queue Manager Queue 10 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[10],Queue Manager Queue 10 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40A0+0x0C)++0x3
line.long 0x00 "CTRLD[10],Queue Manager Queue 10 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50A0++0xB
line.long 0x00 "QSTATA[10],Queue Manager Queue 10 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[10],Queue Manager Queue 10 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[10],Queue Manager Queue 10 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 11 Registers"
rgroup.long 0x40B0++0xB
line.long 0x00 "CTRLA[11],Queue Manager Queue 11 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[11],Queue Manager Queue 11 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[11],Queue Manager Queue 11 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40B0+0x0C)++0x3
line.long 0x00 "CTRLD[11],Queue Manager Queue 11 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50B0++0xB
line.long 0x00 "QSTATA[11],Queue Manager Queue 11 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[11],Queue Manager Queue 11 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[11],Queue Manager Queue 11 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 12 Registers"
rgroup.long 0x40C0++0xB
line.long 0x00 "CTRLA[12],Queue Manager Queue 12 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[12],Queue Manager Queue 12 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[12],Queue Manager Queue 12 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40C0+0x0C)++0x3
line.long 0x00 "CTRLD[12],Queue Manager Queue 12 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50C0++0xB
line.long 0x00 "QSTATA[12],Queue Manager Queue 12 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[12],Queue Manager Queue 12 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[12],Queue Manager Queue 12 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 13 Registers"
rgroup.long 0x40D0++0xB
line.long 0x00 "CTRLA[13],Queue Manager Queue 13 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[13],Queue Manager Queue 13 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[13],Queue Manager Queue 13 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40D0+0x0C)++0x3
line.long 0x00 "CTRLD[13],Queue Manager Queue 13 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50D0++0xB
line.long 0x00 "QSTATA[13],Queue Manager Queue 13 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[13],Queue Manager Queue 13 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[13],Queue Manager Queue 13 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 14 Registers"
rgroup.long 0x40E0++0xB
line.long 0x00 "CTRLA[14],Queue Manager Queue 14 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[14],Queue Manager Queue 14 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[14],Queue Manager Queue 14 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40E0+0x0C)++0x3
line.long 0x00 "CTRLD[14],Queue Manager Queue 14 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50E0++0xB
line.long 0x00 "QSTATA[14],Queue Manager Queue 14 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[14],Queue Manager Queue 14 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[14],Queue Manager Queue 14 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 15 Registers"
rgroup.long 0x40F0++0xB
line.long 0x00 "CTRLA[15],Queue Manager Queue 15 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[15],Queue Manager Queue 15 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[15],Queue Manager Queue 15 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x40F0+0x0C)++0x3
line.long 0x00 "CTRLD[15],Queue Manager Queue 15 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x50F0++0xB
line.long 0x00 "QSTATA[15],Queue Manager Queue 15 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[15],Queue Manager Queue 15 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[15],Queue Manager Queue 15 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 16 Registers"
rgroup.long 0x4100++0xB
line.long 0x00 "CTRLA[16],Queue Manager Queue 16 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[16],Queue Manager Queue 16 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[16],Queue Manager Queue 16 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4100+0x0C)++0x3
line.long 0x00 "CTRLD[16],Queue Manager Queue 16 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5100++0xB
line.long 0x00 "QSTATA[16],Queue Manager Queue 16 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[16],Queue Manager Queue 16 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[16],Queue Manager Queue 16 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 17 Registers"
rgroup.long 0x4110++0xB
line.long 0x00 "CTRLA[17],Queue Manager Queue 17 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[17],Queue Manager Queue 17 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[17],Queue Manager Queue 17 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4110+0x0C)++0x3
line.long 0x00 "CTRLD[17],Queue Manager Queue 17 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5110++0xB
line.long 0x00 "QSTATA[17],Queue Manager Queue 17 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[17],Queue Manager Queue 17 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[17],Queue Manager Queue 17 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 18 Registers"
rgroup.long 0x4120++0xB
line.long 0x00 "CTRLA[18],Queue Manager Queue 18 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[18],Queue Manager Queue 18 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[18],Queue Manager Queue 18 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4120+0x0C)++0x3
line.long 0x00 "CTRLD[18],Queue Manager Queue 18 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5120++0xB
line.long 0x00 "QSTATA[18],Queue Manager Queue 18 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[18],Queue Manager Queue 18 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[18],Queue Manager Queue 18 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 19 Registers"
rgroup.long 0x4130++0xB
line.long 0x00 "CTRLA[19],Queue Manager Queue 19 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[19],Queue Manager Queue 19 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[19],Queue Manager Queue 19 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4130+0x0C)++0x3
line.long 0x00 "CTRLD[19],Queue Manager Queue 19 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5130++0xB
line.long 0x00 "QSTATA[19],Queue Manager Queue 19 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[19],Queue Manager Queue 19 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[19],Queue Manager Queue 19 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 20 Registers"
rgroup.long 0x4140++0xB
line.long 0x00 "CTRLA[20],Queue Manager Queue 20 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[20],Queue Manager Queue 20 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[20],Queue Manager Queue 20 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4140+0x0C)++0x3
line.long 0x00 "CTRLD[20],Queue Manager Queue 20 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5140++0xB
line.long 0x00 "QSTATA[20],Queue Manager Queue 20 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[20],Queue Manager Queue 20 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[20],Queue Manager Queue 20 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 21 Registers"
rgroup.long 0x4150++0xB
line.long 0x00 "CTRLA[21],Queue Manager Queue 21 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[21],Queue Manager Queue 21 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[21],Queue Manager Queue 21 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4150+0x0C)++0x3
line.long 0x00 "CTRLD[21],Queue Manager Queue 21 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5150++0xB
line.long 0x00 "QSTATA[21],Queue Manager Queue 21 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[21],Queue Manager Queue 21 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[21],Queue Manager Queue 21 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 22 Registers"
rgroup.long 0x4160++0xB
line.long 0x00 "CTRLA[22],Queue Manager Queue 22 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[22],Queue Manager Queue 22 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[22],Queue Manager Queue 22 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4160+0x0C)++0x3
line.long 0x00 "CTRLD[22],Queue Manager Queue 22 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5160++0xB
line.long 0x00 "QSTATA[22],Queue Manager Queue 22 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[22],Queue Manager Queue 22 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[22],Queue Manager Queue 22 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 23 Registers"
rgroup.long 0x4170++0xB
line.long 0x00 "CTRLA[23],Queue Manager Queue 23 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[23],Queue Manager Queue 23 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[23],Queue Manager Queue 23 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4170+0x0C)++0x3
line.long 0x00 "CTRLD[23],Queue Manager Queue 23 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5170++0xB
line.long 0x00 "QSTATA[23],Queue Manager Queue 23 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[23],Queue Manager Queue 23 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[23],Queue Manager Queue 23 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 24 Registers"
rgroup.long 0x4180++0xB
line.long 0x00 "CTRLA[24],Queue Manager Queue 24 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[24],Queue Manager Queue 24 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[24],Queue Manager Queue 24 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4180+0x0C)++0x3
line.long 0x00 "CTRLD[24],Queue Manager Queue 24 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5180++0xB
line.long 0x00 "QSTATA[24],Queue Manager Queue 24 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[24],Queue Manager Queue 24 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[24],Queue Manager Queue 24 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 25 Registers"
rgroup.long 0x4190++0xB
line.long 0x00 "CTRLA[25],Queue Manager Queue 25 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[25],Queue Manager Queue 25 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[25],Queue Manager Queue 25 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4190+0x0C)++0x3
line.long 0x00 "CTRLD[25],Queue Manager Queue 25 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5190++0xB
line.long 0x00 "QSTATA[25],Queue Manager Queue 25 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[25],Queue Manager Queue 25 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[25],Queue Manager Queue 25 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 26 Registers"
rgroup.long 0x41A0++0xB
line.long 0x00 "CTRLA[26],Queue Manager Queue 26 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[26],Queue Manager Queue 26 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[26],Queue Manager Queue 26 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41A0+0x0C)++0x3
line.long 0x00 "CTRLD[26],Queue Manager Queue 26 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51A0++0xB
line.long 0x00 "QSTATA[26],Queue Manager Queue 26 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[26],Queue Manager Queue 26 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[26],Queue Manager Queue 26 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 27 Registers"
rgroup.long 0x41B0++0xB
line.long 0x00 "CTRLA[27],Queue Manager Queue 27 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[27],Queue Manager Queue 27 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[27],Queue Manager Queue 27 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41B0+0x0C)++0x3
line.long 0x00 "CTRLD[27],Queue Manager Queue 27 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51B0++0xB
line.long 0x00 "QSTATA[27],Queue Manager Queue 27 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[27],Queue Manager Queue 27 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[27],Queue Manager Queue 27 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 28 Registers"
rgroup.long 0x41C0++0xB
line.long 0x00 "CTRLA[28],Queue Manager Queue 28 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[28],Queue Manager Queue 28 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[28],Queue Manager Queue 28 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41C0+0x0C)++0x3
line.long 0x00 "CTRLD[28],Queue Manager Queue 28 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51C0++0xB
line.long 0x00 "QSTATA[28],Queue Manager Queue 28 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[28],Queue Manager Queue 28 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[28],Queue Manager Queue 28 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 29 Registers"
rgroup.long 0x41D0++0xB
line.long 0x00 "CTRLA[29],Queue Manager Queue 29 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[29],Queue Manager Queue 29 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[29],Queue Manager Queue 29 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41D0+0x0C)++0x3
line.long 0x00 "CTRLD[29],Queue Manager Queue 29 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51D0++0xB
line.long 0x00 "QSTATA[29],Queue Manager Queue 29 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[29],Queue Manager Queue 29 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[29],Queue Manager Queue 29 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 30 Registers"
rgroup.long 0x41E0++0xB
line.long 0x00 "CTRLA[30],Queue Manager Queue 30 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[30],Queue Manager Queue 30 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[30],Queue Manager Queue 30 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41E0+0x0C)++0x3
line.long 0x00 "CTRLD[30],Queue Manager Queue 30 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51E0++0xB
line.long 0x00 "QSTATA[30],Queue Manager Queue 30 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[30],Queue Manager Queue 30 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[30],Queue Manager Queue 30 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 31 Registers"
rgroup.long 0x41F0++0xB
line.long 0x00 "CTRLA[31],Queue Manager Queue 31 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[31],Queue Manager Queue 31 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[31],Queue Manager Queue 31 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x41F0+0x0C)++0x3
line.long 0x00 "CTRLD[31],Queue Manager Queue 31 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x51F0++0xB
line.long 0x00 "QSTATA[31],Queue Manager Queue 31 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[31],Queue Manager Queue 31 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[31],Queue Manager Queue 31 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 32 Registers"
rgroup.long 0x4200++0xB
line.long 0x00 "CTRLA[32],Queue Manager Queue 32 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[32],Queue Manager Queue 32 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[32],Queue Manager Queue 32 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4200+0x0C)++0x3
line.long 0x00 "CTRLD[32],Queue Manager Queue 32 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5200++0xB
line.long 0x00 "QSTATA[32],Queue Manager Queue 32 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[32],Queue Manager Queue 32 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[32],Queue Manager Queue 32 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 33 Registers"
rgroup.long 0x4210++0xB
line.long 0x00 "CTRLA[33],Queue Manager Queue 33 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[33],Queue Manager Queue 33 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[33],Queue Manager Queue 33 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4210+0x0C)++0x3
line.long 0x00 "CTRLD[33],Queue Manager Queue 33 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5210++0xB
line.long 0x00 "QSTATA[33],Queue Manager Queue 33 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[33],Queue Manager Queue 33 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[33],Queue Manager Queue 33 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 34 Registers"
rgroup.long 0x4220++0xB
line.long 0x00 "CTRLA[34],Queue Manager Queue 34 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[34],Queue Manager Queue 34 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[34],Queue Manager Queue 34 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4220+0x0C)++0x3
line.long 0x00 "CTRLD[34],Queue Manager Queue 34 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5220++0xB
line.long 0x00 "QSTATA[34],Queue Manager Queue 34 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[34],Queue Manager Queue 34 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[34],Queue Manager Queue 34 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 35 Registers"
rgroup.long 0x4230++0xB
line.long 0x00 "CTRLA[35],Queue Manager Queue 35 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[35],Queue Manager Queue 35 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[35],Queue Manager Queue 35 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4230+0x0C)++0x3
line.long 0x00 "CTRLD[35],Queue Manager Queue 35 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5230++0xB
line.long 0x00 "QSTATA[35],Queue Manager Queue 35 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[35],Queue Manager Queue 35 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[35],Queue Manager Queue 35 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 36 Registers"
rgroup.long 0x4240++0xB
line.long 0x00 "CTRLA[36],Queue Manager Queue 36 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[36],Queue Manager Queue 36 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[36],Queue Manager Queue 36 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4240+0x0C)++0x3
line.long 0x00 "CTRLD[36],Queue Manager Queue 36 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5240++0xB
line.long 0x00 "QSTATA[36],Queue Manager Queue 36 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[36],Queue Manager Queue 36 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[36],Queue Manager Queue 36 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 37 Registers"
rgroup.long 0x4250++0xB
line.long 0x00 "CTRLA[37],Queue Manager Queue 37 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[37],Queue Manager Queue 37 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[37],Queue Manager Queue 37 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4250+0x0C)++0x3
line.long 0x00 "CTRLD[37],Queue Manager Queue 37 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5250++0xB
line.long 0x00 "QSTATA[37],Queue Manager Queue 37 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[37],Queue Manager Queue 37 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[37],Queue Manager Queue 37 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 38 Registers"
rgroup.long 0x4260++0xB
line.long 0x00 "CTRLA[38],Queue Manager Queue 38 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[38],Queue Manager Queue 38 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[38],Queue Manager Queue 38 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4260+0x0C)++0x3
line.long 0x00 "CTRLD[38],Queue Manager Queue 38 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5260++0xB
line.long 0x00 "QSTATA[38],Queue Manager Queue 38 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[38],Queue Manager Queue 38 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[38],Queue Manager Queue 38 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 39 Registers"
rgroup.long 0x4270++0xB
line.long 0x00 "CTRLA[39],Queue Manager Queue 39 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[39],Queue Manager Queue 39 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[39],Queue Manager Queue 39 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4270+0x0C)++0x3
line.long 0x00 "CTRLD[39],Queue Manager Queue 39 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5270++0xB
line.long 0x00 "QSTATA[39],Queue Manager Queue 39 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[39],Queue Manager Queue 39 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[39],Queue Manager Queue 39 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 40 Registers"
rgroup.long 0x4280++0xB
line.long 0x00 "CTRLA[40],Queue Manager Queue 40 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[40],Queue Manager Queue 40 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[40],Queue Manager Queue 40 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4280+0x0C)++0x3
line.long 0x00 "CTRLD[40],Queue Manager Queue 40 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5280++0xB
line.long 0x00 "QSTATA[40],Queue Manager Queue 40 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[40],Queue Manager Queue 40 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[40],Queue Manager Queue 40 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 41 Registers"
rgroup.long 0x4290++0xB
line.long 0x00 "CTRLA[41],Queue Manager Queue 41 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[41],Queue Manager Queue 41 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[41],Queue Manager Queue 41 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4290+0x0C)++0x3
line.long 0x00 "CTRLD[41],Queue Manager Queue 41 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5290++0xB
line.long 0x00 "QSTATA[41],Queue Manager Queue 41 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[41],Queue Manager Queue 41 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[41],Queue Manager Queue 41 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 42 Registers"
rgroup.long 0x42A0++0xB
line.long 0x00 "CTRLA[42],Queue Manager Queue 42 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[42],Queue Manager Queue 42 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[42],Queue Manager Queue 42 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42A0+0x0C)++0x3
line.long 0x00 "CTRLD[42],Queue Manager Queue 42 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52A0++0xB
line.long 0x00 "QSTATA[42],Queue Manager Queue 42 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[42],Queue Manager Queue 42 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[42],Queue Manager Queue 42 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 43 Registers"
rgroup.long 0x42B0++0xB
line.long 0x00 "CTRLA[43],Queue Manager Queue 43 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[43],Queue Manager Queue 43 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[43],Queue Manager Queue 43 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42B0+0x0C)++0x3
line.long 0x00 "CTRLD[43],Queue Manager Queue 43 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52B0++0xB
line.long 0x00 "QSTATA[43],Queue Manager Queue 43 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[43],Queue Manager Queue 43 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[43],Queue Manager Queue 43 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 44 Registers"
rgroup.long 0x42C0++0xB
line.long 0x00 "CTRLA[44],Queue Manager Queue 44 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[44],Queue Manager Queue 44 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[44],Queue Manager Queue 44 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42C0+0x0C)++0x3
line.long 0x00 "CTRLD[44],Queue Manager Queue 44 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52C0++0xB
line.long 0x00 "QSTATA[44],Queue Manager Queue 44 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[44],Queue Manager Queue 44 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[44],Queue Manager Queue 44 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 45 Registers"
rgroup.long 0x42D0++0xB
line.long 0x00 "CTRLA[45],Queue Manager Queue 45 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[45],Queue Manager Queue 45 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[45],Queue Manager Queue 45 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42D0+0x0C)++0x3
line.long 0x00 "CTRLD[45],Queue Manager Queue 45 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52D0++0xB
line.long 0x00 "QSTATA[45],Queue Manager Queue 45 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[45],Queue Manager Queue 45 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[45],Queue Manager Queue 45 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 46 Registers"
rgroup.long 0x42E0++0xB
line.long 0x00 "CTRLA[46],Queue Manager Queue 46 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[46],Queue Manager Queue 46 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[46],Queue Manager Queue 46 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42E0+0x0C)++0x3
line.long 0x00 "CTRLD[46],Queue Manager Queue 46 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52E0++0xB
line.long 0x00 "QSTATA[46],Queue Manager Queue 46 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[46],Queue Manager Queue 46 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[46],Queue Manager Queue 46 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 47 Registers"
rgroup.long 0x42F0++0xB
line.long 0x00 "CTRLA[47],Queue Manager Queue 47 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[47],Queue Manager Queue 47 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[47],Queue Manager Queue 47 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x42F0+0x0C)++0x3
line.long 0x00 "CTRLD[47],Queue Manager Queue 47 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x52F0++0xB
line.long 0x00 "QSTATA[47],Queue Manager Queue 47 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[47],Queue Manager Queue 47 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[47],Queue Manager Queue 47 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 48 Registers"
rgroup.long 0x4300++0xB
line.long 0x00 "CTRLA[48],Queue Manager Queue 48 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[48],Queue Manager Queue 48 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[48],Queue Manager Queue 48 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4300+0x0C)++0x3
line.long 0x00 "CTRLD[48],Queue Manager Queue 48 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5300++0xB
line.long 0x00 "QSTATA[48],Queue Manager Queue 48 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[48],Queue Manager Queue 48 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[48],Queue Manager Queue 48 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 49 Registers"
rgroup.long 0x4310++0xB
line.long 0x00 "CTRLA[49],Queue Manager Queue 49 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[49],Queue Manager Queue 49 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[49],Queue Manager Queue 49 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4310+0x0C)++0x3
line.long 0x00 "CTRLD[49],Queue Manager Queue 49 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5310++0xB
line.long 0x00 "QSTATA[49],Queue Manager Queue 49 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[49],Queue Manager Queue 49 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[49],Queue Manager Queue 49 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 50 Registers"
rgroup.long 0x4320++0xB
line.long 0x00 "CTRLA[50],Queue Manager Queue 50 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[50],Queue Manager Queue 50 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[50],Queue Manager Queue 50 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4320+0x0C)++0x3
line.long 0x00 "CTRLD[50],Queue Manager Queue 50 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5320++0xB
line.long 0x00 "QSTATA[50],Queue Manager Queue 50 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[50],Queue Manager Queue 50 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[50],Queue Manager Queue 50 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 51 Registers"
rgroup.long 0x4330++0xB
line.long 0x00 "CTRLA[51],Queue Manager Queue 51 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[51],Queue Manager Queue 51 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[51],Queue Manager Queue 51 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4330+0x0C)++0x3
line.long 0x00 "CTRLD[51],Queue Manager Queue 51 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5330++0xB
line.long 0x00 "QSTATA[51],Queue Manager Queue 51 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[51],Queue Manager Queue 51 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[51],Queue Manager Queue 51 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 52 Registers"
rgroup.long 0x4340++0xB
line.long 0x00 "CTRLA[52],Queue Manager Queue 52 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[52],Queue Manager Queue 52 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[52],Queue Manager Queue 52 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4340+0x0C)++0x3
line.long 0x00 "CTRLD[52],Queue Manager Queue 52 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5340++0xB
line.long 0x00 "QSTATA[52],Queue Manager Queue 52 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[52],Queue Manager Queue 52 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[52],Queue Manager Queue 52 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 53 Registers"
rgroup.long 0x4350++0xB
line.long 0x00 "CTRLA[53],Queue Manager Queue 53 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[53],Queue Manager Queue 53 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[53],Queue Manager Queue 53 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4350+0x0C)++0x3
line.long 0x00 "CTRLD[53],Queue Manager Queue 53 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5350++0xB
line.long 0x00 "QSTATA[53],Queue Manager Queue 53 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[53],Queue Manager Queue 53 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[53],Queue Manager Queue 53 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 54 Registers"
rgroup.long 0x4360++0xB
line.long 0x00 "CTRLA[54],Queue Manager Queue 54 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[54],Queue Manager Queue 54 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[54],Queue Manager Queue 54 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4360+0x0C)++0x3
line.long 0x00 "CTRLD[54],Queue Manager Queue 54 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5360++0xB
line.long 0x00 "QSTATA[54],Queue Manager Queue 54 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[54],Queue Manager Queue 54 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[54],Queue Manager Queue 54 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 55 Registers"
rgroup.long 0x4370++0xB
line.long 0x00 "CTRLA[55],Queue Manager Queue 55 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[55],Queue Manager Queue 55 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[55],Queue Manager Queue 55 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4370+0x0C)++0x3
line.long 0x00 "CTRLD[55],Queue Manager Queue 55 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5370++0xB
line.long 0x00 "QSTATA[55],Queue Manager Queue 55 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[55],Queue Manager Queue 55 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[55],Queue Manager Queue 55 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 56 Registers"
rgroup.long 0x4380++0xB
line.long 0x00 "CTRLA[56],Queue Manager Queue 56 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[56],Queue Manager Queue 56 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[56],Queue Manager Queue 56 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4380+0x0C)++0x3
line.long 0x00 "CTRLD[56],Queue Manager Queue 56 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5380++0xB
line.long 0x00 "QSTATA[56],Queue Manager Queue 56 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[56],Queue Manager Queue 56 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[56],Queue Manager Queue 56 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 57 Registers"
rgroup.long 0x4390++0xB
line.long 0x00 "CTRLA[57],Queue Manager Queue 57 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[57],Queue Manager Queue 57 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[57],Queue Manager Queue 57 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4390+0x0C)++0x3
line.long 0x00 "CTRLD[57],Queue Manager Queue 57 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5390++0xB
line.long 0x00 "QSTATA[57],Queue Manager Queue 57 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[57],Queue Manager Queue 57 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[57],Queue Manager Queue 57 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 58 Registers"
rgroup.long 0x43A0++0xB
line.long 0x00 "CTRLA[58],Queue Manager Queue 58 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[58],Queue Manager Queue 58 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[58],Queue Manager Queue 58 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43A0+0x0C)++0x3
line.long 0x00 "CTRLD[58],Queue Manager Queue 58 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53A0++0xB
line.long 0x00 "QSTATA[58],Queue Manager Queue 58 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[58],Queue Manager Queue 58 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[58],Queue Manager Queue 58 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 59 Registers"
rgroup.long 0x43B0++0xB
line.long 0x00 "CTRLA[59],Queue Manager Queue 59 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[59],Queue Manager Queue 59 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[59],Queue Manager Queue 59 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43B0+0x0C)++0x3
line.long 0x00 "CTRLD[59],Queue Manager Queue 59 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53B0++0xB
line.long 0x00 "QSTATA[59],Queue Manager Queue 59 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[59],Queue Manager Queue 59 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[59],Queue Manager Queue 59 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 60 Registers"
rgroup.long 0x43C0++0xB
line.long 0x00 "CTRLA[60],Queue Manager Queue 60 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[60],Queue Manager Queue 60 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[60],Queue Manager Queue 60 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43C0+0x0C)++0x3
line.long 0x00 "CTRLD[60],Queue Manager Queue 60 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53C0++0xB
line.long 0x00 "QSTATA[60],Queue Manager Queue 60 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[60],Queue Manager Queue 60 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[60],Queue Manager Queue 60 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 61 Registers"
rgroup.long 0x43D0++0xB
line.long 0x00 "CTRLA[61],Queue Manager Queue 61 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[61],Queue Manager Queue 61 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[61],Queue Manager Queue 61 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43D0+0x0C)++0x3
line.long 0x00 "CTRLD[61],Queue Manager Queue 61 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53D0++0xB
line.long 0x00 "QSTATA[61],Queue Manager Queue 61 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[61],Queue Manager Queue 61 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[61],Queue Manager Queue 61 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 62 Registers"
rgroup.long 0x43E0++0xB
line.long 0x00 "CTRLA[62],Queue Manager Queue 62 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[62],Queue Manager Queue 62 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[62],Queue Manager Queue 62 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43E0+0x0C)++0x3
line.long 0x00 "CTRLD[62],Queue Manager Queue 62 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53E0++0xB
line.long 0x00 "QSTATA[62],Queue Manager Queue 62 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[62],Queue Manager Queue 62 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[62],Queue Manager Queue 62 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 63 Registers"
rgroup.long 0x43F0++0xB
line.long 0x00 "CTRLA[63],Queue Manager Queue 63 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[63],Queue Manager Queue 63 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[63],Queue Manager Queue 63 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x43F0+0x0C)++0x3
line.long 0x00 "CTRLD[63],Queue Manager Queue 63 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x53F0++0xB
line.long 0x00 "QSTATA[63],Queue Manager Queue 63 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[63],Queue Manager Queue 63 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[63],Queue Manager Queue 63 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 64 Registers"
rgroup.long 0x4400++0xB
line.long 0x00 "CTRLA[64],Queue Manager Queue 64 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[64],Queue Manager Queue 64 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[64],Queue Manager Queue 64 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4400+0x0C)++0x3
line.long 0x00 "CTRLD[64],Queue Manager Queue 64 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5400++0xB
line.long 0x00 "QSTATA[64],Queue Manager Queue 64 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[64],Queue Manager Queue 64 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[64],Queue Manager Queue 64 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 65 Registers"
rgroup.long 0x4410++0xB
line.long 0x00 "CTRLA[65],Queue Manager Queue 65 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[65],Queue Manager Queue 65 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[65],Queue Manager Queue 65 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4410+0x0C)++0x3
line.long 0x00 "CTRLD[65],Queue Manager Queue 65 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5410++0xB
line.long 0x00 "QSTATA[65],Queue Manager Queue 65 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[65],Queue Manager Queue 65 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[65],Queue Manager Queue 65 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 66 Registers"
rgroup.long 0x4420++0xB
line.long 0x00 "CTRLA[66],Queue Manager Queue 66 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[66],Queue Manager Queue 66 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[66],Queue Manager Queue 66 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4420+0x0C)++0x3
line.long 0x00 "CTRLD[66],Queue Manager Queue 66 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5420++0xB
line.long 0x00 "QSTATA[66],Queue Manager Queue 66 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[66],Queue Manager Queue 66 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[66],Queue Manager Queue 66 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 67 Registers"
rgroup.long 0x4430++0xB
line.long 0x00 "CTRLA[67],Queue Manager Queue 67 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[67],Queue Manager Queue 67 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[67],Queue Manager Queue 67 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4430+0x0C)++0x3
line.long 0x00 "CTRLD[67],Queue Manager Queue 67 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5430++0xB
line.long 0x00 "QSTATA[67],Queue Manager Queue 67 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[67],Queue Manager Queue 67 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[67],Queue Manager Queue 67 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 68 Registers"
rgroup.long 0x4440++0xB
line.long 0x00 "CTRLA[68],Queue Manager Queue 68 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[68],Queue Manager Queue 68 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[68],Queue Manager Queue 68 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4440+0x0C)++0x3
line.long 0x00 "CTRLD[68],Queue Manager Queue 68 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5440++0xB
line.long 0x00 "QSTATA[68],Queue Manager Queue 68 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[68],Queue Manager Queue 68 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[68],Queue Manager Queue 68 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 69 Registers"
rgroup.long 0x4450++0xB
line.long 0x00 "CTRLA[69],Queue Manager Queue 69 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[69],Queue Manager Queue 69 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[69],Queue Manager Queue 69 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4450+0x0C)++0x3
line.long 0x00 "CTRLD[69],Queue Manager Queue 69 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5450++0xB
line.long 0x00 "QSTATA[69],Queue Manager Queue 69 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[69],Queue Manager Queue 69 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[69],Queue Manager Queue 69 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 70 Registers"
rgroup.long 0x4460++0xB
line.long 0x00 "CTRLA[70],Queue Manager Queue 70 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[70],Queue Manager Queue 70 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[70],Queue Manager Queue 70 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4460+0x0C)++0x3
line.long 0x00 "CTRLD[70],Queue Manager Queue 70 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5460++0xB
line.long 0x00 "QSTATA[70],Queue Manager Queue 70 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[70],Queue Manager Queue 70 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[70],Queue Manager Queue 70 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 71 Registers"
rgroup.long 0x4470++0xB
line.long 0x00 "CTRLA[71],Queue Manager Queue 71 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[71],Queue Manager Queue 71 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[71],Queue Manager Queue 71 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4470+0x0C)++0x3
line.long 0x00 "CTRLD[71],Queue Manager Queue 71 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5470++0xB
line.long 0x00 "QSTATA[71],Queue Manager Queue 71 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[71],Queue Manager Queue 71 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[71],Queue Manager Queue 71 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 72 Registers"
rgroup.long 0x4480++0xB
line.long 0x00 "CTRLA[72],Queue Manager Queue 72 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[72],Queue Manager Queue 72 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[72],Queue Manager Queue 72 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4480+0x0C)++0x3
line.long 0x00 "CTRLD[72],Queue Manager Queue 72 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5480++0xB
line.long 0x00 "QSTATA[72],Queue Manager Queue 72 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[72],Queue Manager Queue 72 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[72],Queue Manager Queue 72 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 73 Registers"
rgroup.long 0x4490++0xB
line.long 0x00 "CTRLA[73],Queue Manager Queue 73 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[73],Queue Manager Queue 73 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[73],Queue Manager Queue 73 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4490+0x0C)++0x3
line.long 0x00 "CTRLD[73],Queue Manager Queue 73 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5490++0xB
line.long 0x00 "QSTATA[73],Queue Manager Queue 73 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[73],Queue Manager Queue 73 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[73],Queue Manager Queue 73 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 74 Registers"
rgroup.long 0x44A0++0xB
line.long 0x00 "CTRLA[74],Queue Manager Queue 74 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[74],Queue Manager Queue 74 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[74],Queue Manager Queue 74 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44A0+0x0C)++0x3
line.long 0x00 "CTRLD[74],Queue Manager Queue 74 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54A0++0xB
line.long 0x00 "QSTATA[74],Queue Manager Queue 74 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[74],Queue Manager Queue 74 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[74],Queue Manager Queue 74 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 75 Registers"
rgroup.long 0x44B0++0xB
line.long 0x00 "CTRLA[75],Queue Manager Queue 75 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[75],Queue Manager Queue 75 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[75],Queue Manager Queue 75 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44B0+0x0C)++0x3
line.long 0x00 "CTRLD[75],Queue Manager Queue 75 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54B0++0xB
line.long 0x00 "QSTATA[75],Queue Manager Queue 75 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[75],Queue Manager Queue 75 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[75],Queue Manager Queue 75 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 76 Registers"
rgroup.long 0x44C0++0xB
line.long 0x00 "CTRLA[76],Queue Manager Queue 76 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[76],Queue Manager Queue 76 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[76],Queue Manager Queue 76 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44C0+0x0C)++0x3
line.long 0x00 "CTRLD[76],Queue Manager Queue 76 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54C0++0xB
line.long 0x00 "QSTATA[76],Queue Manager Queue 76 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[76],Queue Manager Queue 76 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[76],Queue Manager Queue 76 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 77 Registers"
rgroup.long 0x44D0++0xB
line.long 0x00 "CTRLA[77],Queue Manager Queue 77 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[77],Queue Manager Queue 77 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[77],Queue Manager Queue 77 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44D0+0x0C)++0x3
line.long 0x00 "CTRLD[77],Queue Manager Queue 77 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54D0++0xB
line.long 0x00 "QSTATA[77],Queue Manager Queue 77 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[77],Queue Manager Queue 77 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[77],Queue Manager Queue 77 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 78 Registers"
rgroup.long 0x44E0++0xB
line.long 0x00 "CTRLA[78],Queue Manager Queue 78 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[78],Queue Manager Queue 78 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[78],Queue Manager Queue 78 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44E0+0x0C)++0x3
line.long 0x00 "CTRLD[78],Queue Manager Queue 78 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54E0++0xB
line.long 0x00 "QSTATA[78],Queue Manager Queue 78 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[78],Queue Manager Queue 78 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[78],Queue Manager Queue 78 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 79 Registers"
rgroup.long 0x44F0++0xB
line.long 0x00 "CTRLA[79],Queue Manager Queue 79 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[79],Queue Manager Queue 79 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[79],Queue Manager Queue 79 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x44F0+0x0C)++0x3
line.long 0x00 "CTRLD[79],Queue Manager Queue 79 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x54F0++0xB
line.long 0x00 "QSTATA[79],Queue Manager Queue 79 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[79],Queue Manager Queue 79 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[79],Queue Manager Queue 79 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 80 Registers"
rgroup.long 0x4500++0xB
line.long 0x00 "CTRLA[80],Queue Manager Queue 80 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[80],Queue Manager Queue 80 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[80],Queue Manager Queue 80 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4500+0x0C)++0x3
line.long 0x00 "CTRLD[80],Queue Manager Queue 80 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5500++0xB
line.long 0x00 "QSTATA[80],Queue Manager Queue 80 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[80],Queue Manager Queue 80 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[80],Queue Manager Queue 80 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 81 Registers"
rgroup.long 0x4510++0xB
line.long 0x00 "CTRLA[81],Queue Manager Queue 81 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[81],Queue Manager Queue 81 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[81],Queue Manager Queue 81 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4510+0x0C)++0x3
line.long 0x00 "CTRLD[81],Queue Manager Queue 81 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5510++0xB
line.long 0x00 "QSTATA[81],Queue Manager Queue 81 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[81],Queue Manager Queue 81 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[81],Queue Manager Queue 81 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 82 Registers"
rgroup.long 0x4520++0xB
line.long 0x00 "CTRLA[82],Queue Manager Queue 82 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[82],Queue Manager Queue 82 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[82],Queue Manager Queue 82 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4520+0x0C)++0x3
line.long 0x00 "CTRLD[82],Queue Manager Queue 82 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5520++0xB
line.long 0x00 "QSTATA[82],Queue Manager Queue 82 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[82],Queue Manager Queue 82 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[82],Queue Manager Queue 82 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 83 Registers"
rgroup.long 0x4530++0xB
line.long 0x00 "CTRLA[83],Queue Manager Queue 83 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[83],Queue Manager Queue 83 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[83],Queue Manager Queue 83 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4530+0x0C)++0x3
line.long 0x00 "CTRLD[83],Queue Manager Queue 83 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5530++0xB
line.long 0x00 "QSTATA[83],Queue Manager Queue 83 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[83],Queue Manager Queue 83 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[83],Queue Manager Queue 83 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 84 Registers"
rgroup.long 0x4540++0xB
line.long 0x00 "CTRLA[84],Queue Manager Queue 84 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[84],Queue Manager Queue 84 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[84],Queue Manager Queue 84 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4540+0x0C)++0x3
line.long 0x00 "CTRLD[84],Queue Manager Queue 84 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5540++0xB
line.long 0x00 "QSTATA[84],Queue Manager Queue 84 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[84],Queue Manager Queue 84 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[84],Queue Manager Queue 84 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 85 Registers"
rgroup.long 0x4550++0xB
line.long 0x00 "CTRLA[85],Queue Manager Queue 85 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[85],Queue Manager Queue 85 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[85],Queue Manager Queue 85 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4550+0x0C)++0x3
line.long 0x00 "CTRLD[85],Queue Manager Queue 85 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5550++0xB
line.long 0x00 "QSTATA[85],Queue Manager Queue 85 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[85],Queue Manager Queue 85 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[85],Queue Manager Queue 85 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 86 Registers"
rgroup.long 0x4560++0xB
line.long 0x00 "CTRLA[86],Queue Manager Queue 86 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[86],Queue Manager Queue 86 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[86],Queue Manager Queue 86 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4560+0x0C)++0x3
line.long 0x00 "CTRLD[86],Queue Manager Queue 86 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5560++0xB
line.long 0x00 "QSTATA[86],Queue Manager Queue 86 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[86],Queue Manager Queue 86 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[86],Queue Manager Queue 86 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 87 Registers"
rgroup.long 0x4570++0xB
line.long 0x00 "CTRLA[87],Queue Manager Queue 87 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[87],Queue Manager Queue 87 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[87],Queue Manager Queue 87 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4570+0x0C)++0x3
line.long 0x00 "CTRLD[87],Queue Manager Queue 87 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5570++0xB
line.long 0x00 "QSTATA[87],Queue Manager Queue 87 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[87],Queue Manager Queue 87 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[87],Queue Manager Queue 87 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 88 Registers"
rgroup.long 0x4580++0xB
line.long 0x00 "CTRLA[88],Queue Manager Queue 88 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[88],Queue Manager Queue 88 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[88],Queue Manager Queue 88 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4580+0x0C)++0x3
line.long 0x00 "CTRLD[88],Queue Manager Queue 88 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5580++0xB
line.long 0x00 "QSTATA[88],Queue Manager Queue 88 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[88],Queue Manager Queue 88 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[88],Queue Manager Queue 88 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 89 Registers"
rgroup.long 0x4590++0xB
line.long 0x00 "CTRLA[89],Queue Manager Queue 89 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[89],Queue Manager Queue 89 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[89],Queue Manager Queue 89 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4590+0x0C)++0x3
line.long 0x00 "CTRLD[89],Queue Manager Queue 89 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5590++0xB
line.long 0x00 "QSTATA[89],Queue Manager Queue 89 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[89],Queue Manager Queue 89 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[89],Queue Manager Queue 89 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 90 Registers"
rgroup.long 0x45A0++0xB
line.long 0x00 "CTRLA[90],Queue Manager Queue 90 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[90],Queue Manager Queue 90 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[90],Queue Manager Queue 90 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45A0+0x0C)++0x3
line.long 0x00 "CTRLD[90],Queue Manager Queue 90 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55A0++0xB
line.long 0x00 "QSTATA[90],Queue Manager Queue 90 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[90],Queue Manager Queue 90 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[90],Queue Manager Queue 90 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 91 Registers"
rgroup.long 0x45B0++0xB
line.long 0x00 "CTRLA[91],Queue Manager Queue 91 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[91],Queue Manager Queue 91 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[91],Queue Manager Queue 91 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45B0+0x0C)++0x3
line.long 0x00 "CTRLD[91],Queue Manager Queue 91 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55B0++0xB
line.long 0x00 "QSTATA[91],Queue Manager Queue 91 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[91],Queue Manager Queue 91 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[91],Queue Manager Queue 91 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 92 Registers"
rgroup.long 0x45C0++0xB
line.long 0x00 "CTRLA[92],Queue Manager Queue 92 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[92],Queue Manager Queue 92 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[92],Queue Manager Queue 92 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45C0+0x0C)++0x3
line.long 0x00 "CTRLD[92],Queue Manager Queue 92 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55C0++0xB
line.long 0x00 "QSTATA[92],Queue Manager Queue 92 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[92],Queue Manager Queue 92 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[92],Queue Manager Queue 92 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 93 Registers"
rgroup.long 0x45D0++0xB
line.long 0x00 "CTRLA[93],Queue Manager Queue 93 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[93],Queue Manager Queue 93 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[93],Queue Manager Queue 93 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45D0+0x0C)++0x3
line.long 0x00 "CTRLD[93],Queue Manager Queue 93 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55D0++0xB
line.long 0x00 "QSTATA[93],Queue Manager Queue 93 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[93],Queue Manager Queue 93 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[93],Queue Manager Queue 93 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 94 Registers"
rgroup.long 0x45E0++0xB
line.long 0x00 "CTRLA[94],Queue Manager Queue 94 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[94],Queue Manager Queue 94 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[94],Queue Manager Queue 94 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45E0+0x0C)++0x3
line.long 0x00 "CTRLD[94],Queue Manager Queue 94 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55E0++0xB
line.long 0x00 "QSTATA[94],Queue Manager Queue 94 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[94],Queue Manager Queue 94 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[94],Queue Manager Queue 94 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 95 Registers"
rgroup.long 0x45F0++0xB
line.long 0x00 "CTRLA[95],Queue Manager Queue 95 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[95],Queue Manager Queue 95 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[95],Queue Manager Queue 95 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x45F0+0x0C)++0x3
line.long 0x00 "CTRLD[95],Queue Manager Queue 95 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x55F0++0xB
line.long 0x00 "QSTATA[95],Queue Manager Queue 95 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[95],Queue Manager Queue 95 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[95],Queue Manager Queue 95 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 96 Registers"
rgroup.long 0x4600++0xB
line.long 0x00 "CTRLA[96],Queue Manager Queue 96 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[96],Queue Manager Queue 96 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[96],Queue Manager Queue 96 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4600+0x0C)++0x3
line.long 0x00 "CTRLD[96],Queue Manager Queue 96 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5600++0xB
line.long 0x00 "QSTATA[96],Queue Manager Queue 96 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[96],Queue Manager Queue 96 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[96],Queue Manager Queue 96 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 97 Registers"
rgroup.long 0x4610++0xB
line.long 0x00 "CTRLA[97],Queue Manager Queue 97 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[97],Queue Manager Queue 97 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[97],Queue Manager Queue 97 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4610+0x0C)++0x3
line.long 0x00 "CTRLD[97],Queue Manager Queue 97 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5610++0xB
line.long 0x00 "QSTATA[97],Queue Manager Queue 97 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[97],Queue Manager Queue 97 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[97],Queue Manager Queue 97 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 98 Registers"
rgroup.long 0x4620++0xB
line.long 0x00 "CTRLA[98],Queue Manager Queue 98 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[98],Queue Manager Queue 98 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[98],Queue Manager Queue 98 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4620+0x0C)++0x3
line.long 0x00 "CTRLD[98],Queue Manager Queue 98 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5620++0xB
line.long 0x00 "QSTATA[98],Queue Manager Queue 98 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[98],Queue Manager Queue 98 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[98],Queue Manager Queue 98 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 99 Registers"
rgroup.long 0x4630++0xB
line.long 0x00 "CTRLA[99],Queue Manager Queue 99 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[99],Queue Manager Queue 99 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[99],Queue Manager Queue 99 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4630+0x0C)++0x3
line.long 0x00 "CTRLD[99],Queue Manager Queue 99 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5630++0xB
line.long 0x00 "QSTATA[99],Queue Manager Queue 99 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[99],Queue Manager Queue 99 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[99],Queue Manager Queue 99 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 100 Registers"
rgroup.long 0x4640++0xB
line.long 0x00 "CTRLA[100],Queue Manager Queue 100 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[100],Queue Manager Queue 100 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[100],Queue Manager Queue 100 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4640+0x0C)++0x3
line.long 0x00 "CTRLD[100],Queue Manager Queue 100 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5640++0xB
line.long 0x00 "QSTATA[100],Queue Manager Queue 100 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[100],Queue Manager Queue 100 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[100],Queue Manager Queue 100 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 101 Registers"
rgroup.long 0x4650++0xB
line.long 0x00 "CTRLA[101],Queue Manager Queue 101 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[101],Queue Manager Queue 101 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[101],Queue Manager Queue 101 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4650+0x0C)++0x3
line.long 0x00 "CTRLD[101],Queue Manager Queue 101 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5650++0xB
line.long 0x00 "QSTATA[101],Queue Manager Queue 101 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[101],Queue Manager Queue 101 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[101],Queue Manager Queue 101 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 102 Registers"
rgroup.long 0x4660++0xB
line.long 0x00 "CTRLA[102],Queue Manager Queue 102 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[102],Queue Manager Queue 102 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[102],Queue Manager Queue 102 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4660+0x0C)++0x3
line.long 0x00 "CTRLD[102],Queue Manager Queue 102 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5660++0xB
line.long 0x00 "QSTATA[102],Queue Manager Queue 102 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[102],Queue Manager Queue 102 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[102],Queue Manager Queue 102 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 103 Registers"
rgroup.long 0x4670++0xB
line.long 0x00 "CTRLA[103],Queue Manager Queue 103 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[103],Queue Manager Queue 103 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[103],Queue Manager Queue 103 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4670+0x0C)++0x3
line.long 0x00 "CTRLD[103],Queue Manager Queue 103 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5670++0xB
line.long 0x00 "QSTATA[103],Queue Manager Queue 103 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[103],Queue Manager Queue 103 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[103],Queue Manager Queue 103 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 104 Registers"
rgroup.long 0x4680++0xB
line.long 0x00 "CTRLA[104],Queue Manager Queue 104 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[104],Queue Manager Queue 104 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[104],Queue Manager Queue 104 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4680+0x0C)++0x3
line.long 0x00 "CTRLD[104],Queue Manager Queue 104 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5680++0xB
line.long 0x00 "QSTATA[104],Queue Manager Queue 104 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[104],Queue Manager Queue 104 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[104],Queue Manager Queue 104 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 105 Registers"
rgroup.long 0x4690++0xB
line.long 0x00 "CTRLA[105],Queue Manager Queue 105 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[105],Queue Manager Queue 105 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[105],Queue Manager Queue 105 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4690+0x0C)++0x3
line.long 0x00 "CTRLD[105],Queue Manager Queue 105 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5690++0xB
line.long 0x00 "QSTATA[105],Queue Manager Queue 105 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[105],Queue Manager Queue 105 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[105],Queue Manager Queue 105 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 106 Registers"
rgroup.long 0x46A0++0xB
line.long 0x00 "CTRLA[106],Queue Manager Queue 106 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[106],Queue Manager Queue 106 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[106],Queue Manager Queue 106 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46A0+0x0C)++0x3
line.long 0x00 "CTRLD[106],Queue Manager Queue 106 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56A0++0xB
line.long 0x00 "QSTATA[106],Queue Manager Queue 106 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[106],Queue Manager Queue 106 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[106],Queue Manager Queue 106 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 107 Registers"
rgroup.long 0x46B0++0xB
line.long 0x00 "CTRLA[107],Queue Manager Queue 107 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[107],Queue Manager Queue 107 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[107],Queue Manager Queue 107 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46B0+0x0C)++0x3
line.long 0x00 "CTRLD[107],Queue Manager Queue 107 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56B0++0xB
line.long 0x00 "QSTATA[107],Queue Manager Queue 107 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[107],Queue Manager Queue 107 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[107],Queue Manager Queue 107 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 108 Registers"
rgroup.long 0x46C0++0xB
line.long 0x00 "CTRLA[108],Queue Manager Queue 108 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[108],Queue Manager Queue 108 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[108],Queue Manager Queue 108 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46C0+0x0C)++0x3
line.long 0x00 "CTRLD[108],Queue Manager Queue 108 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56C0++0xB
line.long 0x00 "QSTATA[108],Queue Manager Queue 108 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[108],Queue Manager Queue 108 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[108],Queue Manager Queue 108 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 109 Registers"
rgroup.long 0x46D0++0xB
line.long 0x00 "CTRLA[109],Queue Manager Queue 109 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[109],Queue Manager Queue 109 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[109],Queue Manager Queue 109 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46D0+0x0C)++0x3
line.long 0x00 "CTRLD[109],Queue Manager Queue 109 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56D0++0xB
line.long 0x00 "QSTATA[109],Queue Manager Queue 109 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[109],Queue Manager Queue 109 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[109],Queue Manager Queue 109 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 110 Registers"
rgroup.long 0x46E0++0xB
line.long 0x00 "CTRLA[110],Queue Manager Queue 110 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[110],Queue Manager Queue 110 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[110],Queue Manager Queue 110 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46E0+0x0C)++0x3
line.long 0x00 "CTRLD[110],Queue Manager Queue 110 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56E0++0xB
line.long 0x00 "QSTATA[110],Queue Manager Queue 110 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[110],Queue Manager Queue 110 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[110],Queue Manager Queue 110 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 111 Registers"
rgroup.long 0x46F0++0xB
line.long 0x00 "CTRLA[111],Queue Manager Queue 111 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[111],Queue Manager Queue 111 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[111],Queue Manager Queue 111 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x46F0+0x0C)++0x3
line.long 0x00 "CTRLD[111],Queue Manager Queue 111 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x56F0++0xB
line.long 0x00 "QSTATA[111],Queue Manager Queue 111 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[111],Queue Manager Queue 111 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[111],Queue Manager Queue 111 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 112 Registers"
rgroup.long 0x4700++0xB
line.long 0x00 "CTRLA[112],Queue Manager Queue 112 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[112],Queue Manager Queue 112 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[112],Queue Manager Queue 112 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4700+0x0C)++0x3
line.long 0x00 "CTRLD[112],Queue Manager Queue 112 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5700++0xB
line.long 0x00 "QSTATA[112],Queue Manager Queue 112 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[112],Queue Manager Queue 112 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[112],Queue Manager Queue 112 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 113 Registers"
rgroup.long 0x4710++0xB
line.long 0x00 "CTRLA[113],Queue Manager Queue 113 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[113],Queue Manager Queue 113 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[113],Queue Manager Queue 113 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4710+0x0C)++0x3
line.long 0x00 "CTRLD[113],Queue Manager Queue 113 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5710++0xB
line.long 0x00 "QSTATA[113],Queue Manager Queue 113 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[113],Queue Manager Queue 113 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[113],Queue Manager Queue 113 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 114 Registers"
rgroup.long 0x4720++0xB
line.long 0x00 "CTRLA[114],Queue Manager Queue 114 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[114],Queue Manager Queue 114 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[114],Queue Manager Queue 114 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4720+0x0C)++0x3
line.long 0x00 "CTRLD[114],Queue Manager Queue 114 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5720++0xB
line.long 0x00 "QSTATA[114],Queue Manager Queue 114 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[114],Queue Manager Queue 114 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[114],Queue Manager Queue 114 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 115 Registers"
rgroup.long 0x4730++0xB
line.long 0x00 "CTRLA[115],Queue Manager Queue 115 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[115],Queue Manager Queue 115 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[115],Queue Manager Queue 115 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4730+0x0C)++0x3
line.long 0x00 "CTRLD[115],Queue Manager Queue 115 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5730++0xB
line.long 0x00 "QSTATA[115],Queue Manager Queue 115 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[115],Queue Manager Queue 115 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[115],Queue Manager Queue 115 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 116 Registers"
rgroup.long 0x4740++0xB
line.long 0x00 "CTRLA[116],Queue Manager Queue 116 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[116],Queue Manager Queue 116 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[116],Queue Manager Queue 116 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4740+0x0C)++0x3
line.long 0x00 "CTRLD[116],Queue Manager Queue 116 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5740++0xB
line.long 0x00 "QSTATA[116],Queue Manager Queue 116 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[116],Queue Manager Queue 116 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[116],Queue Manager Queue 116 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 117 Registers"
rgroup.long 0x4750++0xB
line.long 0x00 "CTRLA[117],Queue Manager Queue 117 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[117],Queue Manager Queue 117 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[117],Queue Manager Queue 117 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4750+0x0C)++0x3
line.long 0x00 "CTRLD[117],Queue Manager Queue 117 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5750++0xB
line.long 0x00 "QSTATA[117],Queue Manager Queue 117 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[117],Queue Manager Queue 117 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[117],Queue Manager Queue 117 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 118 Registers"
rgroup.long 0x4760++0xB
line.long 0x00 "CTRLA[118],Queue Manager Queue 118 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[118],Queue Manager Queue 118 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[118],Queue Manager Queue 118 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4760+0x0C)++0x3
line.long 0x00 "CTRLD[118],Queue Manager Queue 118 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5760++0xB
line.long 0x00 "QSTATA[118],Queue Manager Queue 118 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[118],Queue Manager Queue 118 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[118],Queue Manager Queue 118 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 119 Registers"
rgroup.long 0x4770++0xB
line.long 0x00 "CTRLA[119],Queue Manager Queue 119 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[119],Queue Manager Queue 119 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[119],Queue Manager Queue 119 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4770+0x0C)++0x3
line.long 0x00 "CTRLD[119],Queue Manager Queue 119 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5770++0xB
line.long 0x00 "QSTATA[119],Queue Manager Queue 119 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[119],Queue Manager Queue 119 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[119],Queue Manager Queue 119 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 120 Registers"
rgroup.long 0x4780++0xB
line.long 0x00 "CTRLA[120],Queue Manager Queue 120 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[120],Queue Manager Queue 120 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[120],Queue Manager Queue 120 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4780+0x0C)++0x3
line.long 0x00 "CTRLD[120],Queue Manager Queue 120 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5780++0xB
line.long 0x00 "QSTATA[120],Queue Manager Queue 120 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[120],Queue Manager Queue 120 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[120],Queue Manager Queue 120 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 121 Registers"
rgroup.long 0x4790++0xB
line.long 0x00 "CTRLA[121],Queue Manager Queue 121 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[121],Queue Manager Queue 121 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[121],Queue Manager Queue 121 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4790+0x0C)++0x3
line.long 0x00 "CTRLD[121],Queue Manager Queue 121 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5790++0xB
line.long 0x00 "QSTATA[121],Queue Manager Queue 121 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[121],Queue Manager Queue 121 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[121],Queue Manager Queue 121 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 122 Registers"
rgroup.long 0x47A0++0xB
line.long 0x00 "CTRLA[122],Queue Manager Queue 122 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[122],Queue Manager Queue 122 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[122],Queue Manager Queue 122 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47A0+0x0C)++0x3
line.long 0x00 "CTRLD[122],Queue Manager Queue 122 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57A0++0xB
line.long 0x00 "QSTATA[122],Queue Manager Queue 122 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[122],Queue Manager Queue 122 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[122],Queue Manager Queue 122 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 123 Registers"
rgroup.long 0x47B0++0xB
line.long 0x00 "CTRLA[123],Queue Manager Queue 123 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[123],Queue Manager Queue 123 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[123],Queue Manager Queue 123 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47B0+0x0C)++0x3
line.long 0x00 "CTRLD[123],Queue Manager Queue 123 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57B0++0xB
line.long 0x00 "QSTATA[123],Queue Manager Queue 123 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[123],Queue Manager Queue 123 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[123],Queue Manager Queue 123 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 124 Registers"
rgroup.long 0x47C0++0xB
line.long 0x00 "CTRLA[124],Queue Manager Queue 124 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[124],Queue Manager Queue 124 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[124],Queue Manager Queue 124 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47C0+0x0C)++0x3
line.long 0x00 "CTRLD[124],Queue Manager Queue 124 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57C0++0xB
line.long 0x00 "QSTATA[124],Queue Manager Queue 124 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[124],Queue Manager Queue 124 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[124],Queue Manager Queue 124 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 125 Registers"
rgroup.long 0x47D0++0xB
line.long 0x00 "CTRLA[125],Queue Manager Queue 125 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[125],Queue Manager Queue 125 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[125],Queue Manager Queue 125 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47D0+0x0C)++0x3
line.long 0x00 "CTRLD[125],Queue Manager Queue 125 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57D0++0xB
line.long 0x00 "QSTATA[125],Queue Manager Queue 125 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[125],Queue Manager Queue 125 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[125],Queue Manager Queue 125 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 126 Registers"
rgroup.long 0x47E0++0xB
line.long 0x00 "CTRLA[126],Queue Manager Queue 126 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[126],Queue Manager Queue 126 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[126],Queue Manager Queue 126 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47E0+0x0C)++0x3
line.long 0x00 "CTRLD[126],Queue Manager Queue 126 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57E0++0xB
line.long 0x00 "QSTATA[126],Queue Manager Queue 126 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[126],Queue Manager Queue 126 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[126],Queue Manager Queue 126 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 127 Registers"
rgroup.long 0x47F0++0xB
line.long 0x00 "CTRLA[127],Queue Manager Queue 127 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[127],Queue Manager Queue 127 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[127],Queue Manager Queue 127 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x47F0+0x0C)++0x3
line.long 0x00 "CTRLD[127],Queue Manager Queue 127 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x57F0++0xB
line.long 0x00 "QSTATA[127],Queue Manager Queue 127 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[127],Queue Manager Queue 127 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[127],Queue Manager Queue 127 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 128 Registers"
rgroup.long 0x4800++0xB
line.long 0x00 "CTRLA[128],Queue Manager Queue 128 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[128],Queue Manager Queue 128 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[128],Queue Manager Queue 128 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4800+0x0C)++0x3
line.long 0x00 "CTRLD[128],Queue Manager Queue 128 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5800++0xB
line.long 0x00 "QSTATA[128],Queue Manager Queue 128 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[128],Queue Manager Queue 128 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[128],Queue Manager Queue 128 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 129 Registers"
rgroup.long 0x4810++0xB
line.long 0x00 "CTRLA[129],Queue Manager Queue 129 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[129],Queue Manager Queue 129 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[129],Queue Manager Queue 129 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4810+0x0C)++0x3
line.long 0x00 "CTRLD[129],Queue Manager Queue 129 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5810++0xB
line.long 0x00 "QSTATA[129],Queue Manager Queue 129 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[129],Queue Manager Queue 129 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[129],Queue Manager Queue 129 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 130 Registers"
rgroup.long 0x4820++0xB
line.long 0x00 "CTRLA[130],Queue Manager Queue 130 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[130],Queue Manager Queue 130 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[130],Queue Manager Queue 130 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4820+0x0C)++0x3
line.long 0x00 "CTRLD[130],Queue Manager Queue 130 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5820++0xB
line.long 0x00 "QSTATA[130],Queue Manager Queue 130 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[130],Queue Manager Queue 130 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[130],Queue Manager Queue 130 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 131 Registers"
rgroup.long 0x4830++0xB
line.long 0x00 "CTRLA[131],Queue Manager Queue 131 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[131],Queue Manager Queue 131 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[131],Queue Manager Queue 131 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4830+0x0C)++0x3
line.long 0x00 "CTRLD[131],Queue Manager Queue 131 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5830++0xB
line.long 0x00 "QSTATA[131],Queue Manager Queue 131 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[131],Queue Manager Queue 131 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[131],Queue Manager Queue 131 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 132 Registers"
rgroup.long 0x4840++0xB
line.long 0x00 "CTRLA[132],Queue Manager Queue 132 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[132],Queue Manager Queue 132 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[132],Queue Manager Queue 132 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4840+0x0C)++0x3
line.long 0x00 "CTRLD[132],Queue Manager Queue 132 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5840++0xB
line.long 0x00 "QSTATA[132],Queue Manager Queue 132 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[132],Queue Manager Queue 132 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[132],Queue Manager Queue 132 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 133 Registers"
rgroup.long 0x4850++0xB
line.long 0x00 "CTRLA[133],Queue Manager Queue 133 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[133],Queue Manager Queue 133 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[133],Queue Manager Queue 133 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4850+0x0C)++0x3
line.long 0x00 "CTRLD[133],Queue Manager Queue 133 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5850++0xB
line.long 0x00 "QSTATA[133],Queue Manager Queue 133 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[133],Queue Manager Queue 133 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[133],Queue Manager Queue 133 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 134 Registers"
rgroup.long 0x4860++0xB
line.long 0x00 "CTRLA[134],Queue Manager Queue 134 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[134],Queue Manager Queue 134 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[134],Queue Manager Queue 134 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4860+0x0C)++0x3
line.long 0x00 "CTRLD[134],Queue Manager Queue 134 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5860++0xB
line.long 0x00 "QSTATA[134],Queue Manager Queue 134 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[134],Queue Manager Queue 134 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[134],Queue Manager Queue 134 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 135 Registers"
rgroup.long 0x4870++0xB
line.long 0x00 "CTRLA[135],Queue Manager Queue 135 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[135],Queue Manager Queue 135 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[135],Queue Manager Queue 135 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4870+0x0C)++0x3
line.long 0x00 "CTRLD[135],Queue Manager Queue 135 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5870++0xB
line.long 0x00 "QSTATA[135],Queue Manager Queue 135 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[135],Queue Manager Queue 135 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[135],Queue Manager Queue 135 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 136 Registers"
rgroup.long 0x4880++0xB
line.long 0x00 "CTRLA[136],Queue Manager Queue 136 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[136],Queue Manager Queue 136 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[136],Queue Manager Queue 136 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4880+0x0C)++0x3
line.long 0x00 "CTRLD[136],Queue Manager Queue 136 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5880++0xB
line.long 0x00 "QSTATA[136],Queue Manager Queue 136 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[136],Queue Manager Queue 136 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[136],Queue Manager Queue 136 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 137 Registers"
rgroup.long 0x4890++0xB
line.long 0x00 "CTRLA[137],Queue Manager Queue 137 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[137],Queue Manager Queue 137 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[137],Queue Manager Queue 137 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4890+0x0C)++0x3
line.long 0x00 "CTRLD[137],Queue Manager Queue 137 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5890++0xB
line.long 0x00 "QSTATA[137],Queue Manager Queue 137 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[137],Queue Manager Queue 137 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[137],Queue Manager Queue 137 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 138 Registers"
rgroup.long 0x48A0++0xB
line.long 0x00 "CTRLA[138],Queue Manager Queue 138 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[138],Queue Manager Queue 138 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[138],Queue Manager Queue 138 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48A0+0x0C)++0x3
line.long 0x00 "CTRLD[138],Queue Manager Queue 138 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58A0++0xB
line.long 0x00 "QSTATA[138],Queue Manager Queue 138 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[138],Queue Manager Queue 138 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[138],Queue Manager Queue 138 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 139 Registers"
rgroup.long 0x48B0++0xB
line.long 0x00 "CTRLA[139],Queue Manager Queue 139 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[139],Queue Manager Queue 139 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[139],Queue Manager Queue 139 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48B0+0x0C)++0x3
line.long 0x00 "CTRLD[139],Queue Manager Queue 139 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58B0++0xB
line.long 0x00 "QSTATA[139],Queue Manager Queue 139 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[139],Queue Manager Queue 139 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[139],Queue Manager Queue 139 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 140 Registers"
rgroup.long 0x48C0++0xB
line.long 0x00 "CTRLA[140],Queue Manager Queue 140 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[140],Queue Manager Queue 140 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[140],Queue Manager Queue 140 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48C0+0x0C)++0x3
line.long 0x00 "CTRLD[140],Queue Manager Queue 140 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58C0++0xB
line.long 0x00 "QSTATA[140],Queue Manager Queue 140 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[140],Queue Manager Queue 140 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[140],Queue Manager Queue 140 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 141 Registers"
rgroup.long 0x48D0++0xB
line.long 0x00 "CTRLA[141],Queue Manager Queue 141 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[141],Queue Manager Queue 141 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[141],Queue Manager Queue 141 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48D0+0x0C)++0x3
line.long 0x00 "CTRLD[141],Queue Manager Queue 141 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58D0++0xB
line.long 0x00 "QSTATA[141],Queue Manager Queue 141 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[141],Queue Manager Queue 141 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[141],Queue Manager Queue 141 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 142 Registers"
rgroup.long 0x48E0++0xB
line.long 0x00 "CTRLA[142],Queue Manager Queue 142 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[142],Queue Manager Queue 142 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[142],Queue Manager Queue 142 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48E0+0x0C)++0x3
line.long 0x00 "CTRLD[142],Queue Manager Queue 142 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58E0++0xB
line.long 0x00 "QSTATA[142],Queue Manager Queue 142 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[142],Queue Manager Queue 142 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[142],Queue Manager Queue 142 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 143 Registers"
rgroup.long 0x48F0++0xB
line.long 0x00 "CTRLA[143],Queue Manager Queue 143 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[143],Queue Manager Queue 143 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[143],Queue Manager Queue 143 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x48F0+0x0C)++0x3
line.long 0x00 "CTRLD[143],Queue Manager Queue 143 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x58F0++0xB
line.long 0x00 "QSTATA[143],Queue Manager Queue 143 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[143],Queue Manager Queue 143 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[143],Queue Manager Queue 143 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 144 Registers"
rgroup.long 0x4900++0xB
line.long 0x00 "CTRLA[144],Queue Manager Queue 144 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[144],Queue Manager Queue 144 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[144],Queue Manager Queue 144 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4900+0x0C)++0x3
line.long 0x00 "CTRLD[144],Queue Manager Queue 144 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5900++0xB
line.long 0x00 "QSTATA[144],Queue Manager Queue 144 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[144],Queue Manager Queue 144 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[144],Queue Manager Queue 144 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 145 Registers"
rgroup.long 0x4910++0xB
line.long 0x00 "CTRLA[145],Queue Manager Queue 145 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[145],Queue Manager Queue 145 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[145],Queue Manager Queue 145 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4910+0x0C)++0x3
line.long 0x00 "CTRLD[145],Queue Manager Queue 145 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5910++0xB
line.long 0x00 "QSTATA[145],Queue Manager Queue 145 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[145],Queue Manager Queue 145 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[145],Queue Manager Queue 145 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 146 Registers"
rgroup.long 0x4920++0xB
line.long 0x00 "CTRLA[146],Queue Manager Queue 146 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[146],Queue Manager Queue 146 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[146],Queue Manager Queue 146 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4920+0x0C)++0x3
line.long 0x00 "CTRLD[146],Queue Manager Queue 146 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5920++0xB
line.long 0x00 "QSTATA[146],Queue Manager Queue 146 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[146],Queue Manager Queue 146 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[146],Queue Manager Queue 146 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 147 Registers"
rgroup.long 0x4930++0xB
line.long 0x00 "CTRLA[147],Queue Manager Queue 147 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[147],Queue Manager Queue 147 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[147],Queue Manager Queue 147 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4930+0x0C)++0x3
line.long 0x00 "CTRLD[147],Queue Manager Queue 147 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5930++0xB
line.long 0x00 "QSTATA[147],Queue Manager Queue 147 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[147],Queue Manager Queue 147 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[147],Queue Manager Queue 147 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 148 Registers"
rgroup.long 0x4940++0xB
line.long 0x00 "CTRLA[148],Queue Manager Queue 148 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[148],Queue Manager Queue 148 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[148],Queue Manager Queue 148 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4940+0x0C)++0x3
line.long 0x00 "CTRLD[148],Queue Manager Queue 148 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5940++0xB
line.long 0x00 "QSTATA[148],Queue Manager Queue 148 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[148],Queue Manager Queue 148 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[148],Queue Manager Queue 148 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 149 Registers"
rgroup.long 0x4950++0xB
line.long 0x00 "CTRLA[149],Queue Manager Queue 149 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[149],Queue Manager Queue 149 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[149],Queue Manager Queue 149 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4950+0x0C)++0x3
line.long 0x00 "CTRLD[149],Queue Manager Queue 149 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5950++0xB
line.long 0x00 "QSTATA[149],Queue Manager Queue 149 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[149],Queue Manager Queue 149 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[149],Queue Manager Queue 149 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 150 Registers"
rgroup.long 0x4960++0xB
line.long 0x00 "CTRLA[150],Queue Manager Queue 150 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[150],Queue Manager Queue 150 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[150],Queue Manager Queue 150 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4960+0x0C)++0x3
line.long 0x00 "CTRLD[150],Queue Manager Queue 150 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5960++0xB
line.long 0x00 "QSTATA[150],Queue Manager Queue 150 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[150],Queue Manager Queue 150 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[150],Queue Manager Queue 150 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 151 Registers"
rgroup.long 0x4970++0xB
line.long 0x00 "CTRLA[151],Queue Manager Queue 151 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[151],Queue Manager Queue 151 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[151],Queue Manager Queue 151 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4970+0x0C)++0x3
line.long 0x00 "CTRLD[151],Queue Manager Queue 151 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5970++0xB
line.long 0x00 "QSTATA[151],Queue Manager Queue 151 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[151],Queue Manager Queue 151 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[151],Queue Manager Queue 151 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 152 Registers"
rgroup.long 0x4980++0xB
line.long 0x00 "CTRLA[152],Queue Manager Queue 152 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[152],Queue Manager Queue 152 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[152],Queue Manager Queue 152 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4980+0x0C)++0x3
line.long 0x00 "CTRLD[152],Queue Manager Queue 152 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5980++0xB
line.long 0x00 "QSTATA[152],Queue Manager Queue 152 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[152],Queue Manager Queue 152 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[152],Queue Manager Queue 152 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 153 Registers"
rgroup.long 0x4990++0xB
line.long 0x00 "CTRLA[153],Queue Manager Queue 153 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[153],Queue Manager Queue 153 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[153],Queue Manager Queue 153 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x4990+0x0C)++0x3
line.long 0x00 "CTRLD[153],Queue Manager Queue 153 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x5990++0xB
line.long 0x00 "QSTATA[153],Queue Manager Queue 153 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[153],Queue Manager Queue 153 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[153],Queue Manager Queue 153 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 154 Registers"
rgroup.long 0x49A0++0xB
line.long 0x00 "CTRLA[154],Queue Manager Queue 154 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[154],Queue Manager Queue 154 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[154],Queue Manager Queue 154 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x49A0+0x0C)++0x3
line.long 0x00 "CTRLD[154],Queue Manager Queue 154 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x59A0++0xB
line.long 0x00 "QSTATA[154],Queue Manager Queue 154 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[154],Queue Manager Queue 154 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[154],Queue Manager Queue 154 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree "Queue 155 Registers"
rgroup.long 0x49B0++0xB
line.long 0x00 "CTRLA[155],Queue Manager Queue 155 Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "CTRLB[155],Queue Manager Queue 155 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Number of bytes total are contained in all of the packets"
line.long 0x08 "CTRLC[155],Queue Manager Queue 155 Status Register C"
sif cpuis("DM814?DSP")
bitfld.long 0x08 31. " HEAD_TAIL ,Head/Tail Push Control" "Tail,Head"
textline " "
endif
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size for packet pop operation"
group.long (0x49B0+0x0C)++0x3
line.long 0x00 "CTRLD[155],Queue Manager Queue 155 Control Register D"
hexmask.long 0x00 5.--31. 0x20 " DESC_PTR ,Descriptor Pointer"
bitfld.long 0x00 0.--4. " DESC_SIZE ,Descriptor Size (bytes)" "24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,148"
rgroup.long 0x59B0++0xB
line.long 0x00 "QSTATA[155],Queue Manager Queue 155 Status Register A"
hexmask.long.word 0x00 0.--13. 1. " QUEUE_ENTRY_COUNT ,Number of packets currently queued on the queue"
line.long 0x04 "QSTATB[155],Queue Manager Queue 155 Status Register B"
hexmask.long 0x04 0.--27. 1. " QUEUE_BYTE_COUNT ,Total number of bytes contained in all of the queued packets"
line.long 0x08 "QSTATC[155],Queue Manager Queue 155 Status Register C"
hexmask.long.word 0x08 0.--13. 1. " PACKET_SIZE ,Packet size of the head element of a queue"
tree.end
tree.end
tree.end
width 11.
tree.end
tree "USB Mentor Core"
tree "USB 0 Mentor Core and FIFO Registers"
base ad:0x47401400
width 0xa
tree "Common USB Registers"
wgroup.byte 0x00++0x0
line.byte 0x0 "FADDR,Function Address Register"
hexmask.byte 0x0 0.--6. 1. " FUNCADDR ,7_bit address of the peripheral part of the transaction"
group.byte 0x01++0x00
line.byte 0x0 "POWER,Power Management Register"
bitfld.byte 0x0 7. " ISOUPDATE ,Waiting for SOF token" "No wait,Wait"
bitfld.byte 0x0 6. " SOFTCONN ,Soft Connect/Disconnect feature" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 5. " HSEN ,High-speed mode negotiation enable" "Disabled,Enabled"
bitfld.byte 0x0 4. " HSMODE ,High-speed mode" "Full speed,High speed"
textline " "
bitfld.byte 0x0 3. " RESET ,Reset" "No reset,Reset"
bitfld.byte 0x0 2. " RESUME ,Resume in suspend mode" "No resume,Resume"
textline " "
bitfld.byte 0x0 1. " SUSPENDM ,Suspend mode" "No effect,Suspend mode"
bitfld.byte 0x0 0. " ENSUSPM ,SUSPENDM output enable" "Disabled,Enabled"
rgroup.word 0x02++0x7
line.word 0x0 "INTRTX,Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 15"
bitfld.word 0x0 15. " EP15TX ,Tx Endpoint 15 interrupt active" "Not active,Active"
bitfld.word 0x0 14. " EP14TX ,Tx Endpoint 14 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 13. " EP13TX ,Tx Endpoint 13 interrupt active" "Not active,Active"
bitfld.word 0x0 2. " EP12TX ,Tx Endpoint 12 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 11. " EP11TX ,Tx Endpoint 11 interrupt active" "Not active,Active"
bitfld.word 0x0 10. " EP10TX ,Tx Endpoint 10 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 9. " EP9TX ,Tx Endpoint 9 interrupt active" "Not active,Active"
bitfld.word 0x0 8. " EP8TX ,Tx Endpoint 8 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 7. " EP7TX ,Tx Endpoint 7 interrupt active" "Not active,Active"
bitfld.word 0x0 6. " EP6TX ,Tx Endpoint 6 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 5. " EP5TX ,Tx Endpoint 5 interrupt active" "Not active,Active"
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
line.word 0x2 "INTRRX,Interrupt Register for Receive Endpoints 1 to 15"
bitfld.word 0x02 15. " EP15RX ,Rx Endpoint 15 interrupt active" "Not active,Active"
bitfld.word 0x02 14. " EP14RX ,Rx Endpoint 14 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 13. " EP13RX ,Rx Endpoint 13 interrupt active" "Not active,Active"
bitfld.word 0x02 2. " EP12RX ,Rx Endpoint 12 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 11. " EP11RX ,Rx Endpoint 11 interrupt active" "Not active,Active"
bitfld.word 0x02 10. " EP10RX ,Rx Endpoint 10 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 9. " EP9RX ,Rx Endpoint 9 interrupt active" "Not active,Active"
bitfld.word 0x02 8. " EP8RX ,Rx Endpoint 8 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 7. " EP7RX ,Rx Endpoint 7 interrupt active" "Not active,Active"
bitfld.word 0x02 6. " EP6RX ,Rx Endpoint 6 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 5. " EP5RX ,Rx Endpoint 5 interrupt active" "Not active,Active"
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
line.word 0x04 "INTRTXE,Interrupt Enable Register for INTRTX"
bitfld.word 0x04 15. " EP15TX ,Tx Endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 14. " EP14TX ,Tx Endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 13. " EP13TX ,Tx Endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 2. " EP12TX ,Tx Endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 11. " EP11TX ,Tx Endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 10. " EP10TX ,Tx Endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 9. " EP9TX ,Tx Endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 8. " EP8TX ,Tx Endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 7. " EP7TX ,Tx Endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 6. " EP6TX ,Tx Endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 5. " EP5TX ,Tx Endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 4. " EP4TX ,Tx Endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 3. " EP3TX ,Tx Endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 2. " EP2TX ,Tx Endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 1. " EP1TX ,Tx Endpoint 1 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 0. " EP0 ,Endpoint 0 interrupt enable" "Disabled,Enabled"
line.word 0x06 "INTRRXE,Interrupt Enable Register for INTRRX"
bitfld.word 0x06 15. " EP15RX ,Rx Endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 14. " EP14RX ,Rx Endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 13. " EP13RX ,Rx Endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 2. " EP12RX ,Rx Endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 11. " EP11RX ,Rx Endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 10. " EP10RX ,Rx Endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 9. " EP9RX ,Rx Endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 8. " EP8RX ,Rx Endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 7. " EP7RX ,Rx Endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 6. " EP6RX ,Rx Endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 5. " EP5RX ,Rx Endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 4. " EP4RX ,Receive Endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 3. " EP3RX ,Receive Endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 2. " EP2RX ,Receive Endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 1. " EP1RX ,Receive Endpoint 1 interrupt enable" "Disabled,Enabled"
hgroup.byte 0x0a++0x0
hide.byte 0x0 "INTRUSB,Interrupt Register for Common USB Interrupts"
in
group.byte 0x0b++0x0
line.byte 0x0 "INTRUSBE,Interrupt Enable Register for INTRUSB"
bitfld.byte 0x0 7. " VBUSERR ,Vbus error interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 6. " SESSREQ ,Session request interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 5. " DISCON ,Disconnect interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 4. " CONN ,Connect interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 3. " SOF ,Start of frame interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 2. " RESET_BABBLE ,Reset interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 1. " RESUME ,Resume interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 0. " SUSPEND ,Suspend interrupt enable" "Disabled,Enabled"
rgroup.word 0x0c++0x1
line.word 0x0 "FRAME,Frame Number Register"
hexmask.word 0x0 0.--10. 1. " FRAMENUMBER ,Last received frame number"
group.byte 0x0e++0x1
line.byte 0x0 "INDEX,Index Register for Selecting the Endpoint Status and Control Registers"
bitfld.byte 0x0 0.--3. " EPSEL ,Endpoint control/status register select" "EP 0,EP 1,EP 2,EP 3,EP 4,EP 5,EP 6,EP 7,EP 8,EP 9,EP 10,EP 11,EP 12,EP 13,EP 14,EP 15"
line.byte 0x1 "TESTMODE,Register to Enable the USB 2.0 Test Modes"
bitfld.byte 0x1 7. " FORCE_HOST ,Force Host mode" "Normal,Host"
bitfld.byte 0x1 6. " FIFO_ACCESS ,Transfer packet EP0 Tx FIFO to EP0 Receive FIFO" "Not transferred,Transferred"
textline " "
bitfld.byte 0x1 5. " FORCE_FS ,Force full-speed mode" "Normal,Full speed"
bitfld.byte 0x1 4. " FORCE_HS ,Force high-speed mode" "Normal,High speed"
textline " "
bitfld.byte 0x1 3. " TEST_PACKET ,Test_Packet test mode" "Normal,Test_Packet"
bitfld.byte 0x1 2. " TEST_K ,Test_K test mode" "Normal,Test_K"
textline " "
bitfld.byte 0x1 1. " TEST_J ,Test_J test mode" "Normal,Test_J"
bitfld.byte 0x1 0. " TEST_SE0_NAK ,Test_SE0_NAK test mode" "Normal,Test_SE0_NAK"
tree.end
width 17.
tree "Indexed Region Registers"
if ((((d.b(ad:0x47401400+0x60))&0x4)==0x4)&&(((d.b(ad:0x47401400+0x0e))&0xf)==0x0))
group.word 0x12++0x1
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
textline " "
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
textline " "
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
group.byte 0x1a++0x0
line.byte 0x00 "HOST_TYPE0,Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
group.byte 0x1b++0x0
line.byte 0x00 "HOST_NAKLIMIT0,NAKLIMIT0 Register"
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
rgroup.byte 0x1f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
elif ((((d.b(ad:0x47401400+0x60))&0x4)==0x0)&&(((d.b(ad:0x47401400+0x0e))&0xf)==0x0))
group.word 0x12++0x1
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
textline " "
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
textline " "
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
textline " "
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
rgroup.byte 0x1f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
elif ((((d.b(ad:0x47401400+0x60))&0x4)==0x4)&&((((d.b(ad:0x47401400+0x0e))&0xf)!=0x0)))
group.word 0x10++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word 0x12++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not received,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word 0x14++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word 0x16++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte 0x1a++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1b++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte 0x1c++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1d++0x0
line.byte 0x00 "HOST_RXINTERVAL,Recieve Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word 0x10++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word 0x12++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
textline " "
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word 0x14++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word 0x16++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
width 12.
tree "FIFOs"
hgroup.long 0x20++0x3
hide.long 0x00 "FIFO0,Transmit and Receive FIFO Register for Endpoint 0"
in
hgroup.long 0x24++0x3
hide.long 0x00 "FIFO1,Transmit and Receive FIFO Register for Endpoint 1"
in
hgroup.long 0x28++0x3
hide.long 0x00 "FIFO2,Transmit and Receive FIFO Register for Endpoint 2"
in
hgroup.long 0x2C++0x3
hide.long 0x00 "FIFO3,Transmit and Receive FIFO Register for Endpoint 3"
in
hgroup.long 0x30++0x3
hide.long 0x00 "FIFO4,Transmit and Receive FIFO Register for Endpoint 4"
in
hgroup.long 0x34++0x3
hide.long 0x00 "FIFO5,Transmit and Receive FIFO Register for Endpoint 5"
in
hgroup.long 0x38++0x3
hide.long 0x00 "FIFO6,Transmit and Receive FIFO Register for Endpoint 6"
in
hgroup.long 0x3C++0x3
hide.long 0x00 "FIFO7,Transmit and Receive FIFO Register for Endpoint 7"
in
hgroup.long 0x40++0x3
hide.long 0x00 "FIFO8,Transmit and Receive FIFO Register for Endpoint 8"
in
hgroup.long 0x44++0x3
hide.long 0x00 "FIFO9,Transmit and Receive FIFO Register for Endpoint 9"
in
hgroup.long 0x48++0x3
hide.long 0x00 "FIFO10,Transmit and Receive FIFO Register for Endpoint 10"
in
hgroup.long 0x4C++0x3
hide.long 0x00 "FIFO11,Transmit and Receive FIFO Register for Endpoint 11"
in
hgroup.long 0x50++0x3
hide.long 0x00 "FIFO12,Transmit and Receive FIFO Register for Endpoint 12"
in
hgroup.long 0x54++0x3
hide.long 0x00 "FIFO13,Transmit and Receive FIFO Register for Endpoint 13"
in
hgroup.long 0x58++0x3
hide.long 0x00 "FIFO14,Transmit and Receive FIFO Register for Endpoint 14"
in
hgroup.long 0x5C++0x3
hide.long 0x00 "FIFO15,Transmit and Receive FIFO Register for Endpoint 15"
in
tree.end
tree "Additional Control and Configuration Registers"
if ((((data.byte(ad:0x47401400+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x80))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
textline " "
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
textline " "
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
elif ((((data.byte(ad:0x47401400+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x00))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
textline " "
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
elif ((((data.byte(ad:0x47401400+0x60))&0x04)==0x00)&&(((data.byte(ad:0x47401400+0x60))&0x80)==0x80))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
textline " "
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
else
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
endif
sif (cpuis("DM814?DSP")||cpuis("DRA62*"))
if (((data.byte(ad:0x47401400+0x62))&(0x10))==0x0)
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
else
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
endif
else
if (((data.byte(ad:0x47401400+0x62))&(0x10))==0x0)
group.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
else
group.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
endif
endif
if (((data.byte(ad:0x47401400+0x63))&0x10)==0x0)
group.byte 0x63++0x0
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
else
group.byte 0x63++0x0
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
endif
group.word 0x64++0x1
line.word 0x00 "TXFIFOADDR,Transmit Endpoint FIFO Address"
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
group.word 0x66++0x1
line.word 0x00 "RXFIFOADDR,Receive Endpoint FIFO Address"
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
group.word 0x6C++0x1
line.word 0x00 "HWVERS,Hardware Version Register"
bitfld.word 0x00 15. " RC ,RTL version from which the core hardware was generated" "Release candidate,Full release"
bitfld.word 0x00 10.--14. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
hexmask.word 0x00 0.--9. 1. " REVMIN ,Minor revision"
tree.end
width 12.
tree "Target Endpoint Control"
tree "EPTRG0"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0x80)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x80+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x80+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x80)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x80+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x80+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG1"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0x88)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x88+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x88+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x88)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x88+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x88+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG2"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0x90)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x90+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x90+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x90)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x90+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x90+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG3"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0x98)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x98+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x98+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x98)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x98+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x98+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG4"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xA0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xA0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xA0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xA0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG5"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xA8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xA8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xA8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xA8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG6"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xB0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xB0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xB0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xB0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG7"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xB8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xB8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xB8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xB8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG8"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xC0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xC0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xC0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xC0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG9"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xC8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xC8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xC8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xC8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG10"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xD0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xD0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xD0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xD0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG11"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xD8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xD8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xD8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xD8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG12"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xE0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xE0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xE0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xE0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG13"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xE8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xE8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xE8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xE8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG14"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xF0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xF0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xF0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xF0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG15"
if ((d.b((ad:0x47401400+0x60))&0x4)==0x4)
group.byte (0xF8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xF8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xF8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xF8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree.end
width 17.
tree "Control and Status Registers for Endpoints"
tree "EOCSR0"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word 0x102++0x1
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
textline " "
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
textline " "
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
textline " "
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x108++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
group.byte 0x10a++0x0
line.byte 0x00 "HOST_TYPE0,Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
group.byte 0x10b++0x0
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
rgroup.byte 0x10f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
else
group.word 0x102++0x1
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
textline " "
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
textline " "
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
textline " "
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
rgroup.word 0x108++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
rgroup.byte 0x10f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
endif
tree.end
tree "EOCSR1"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x110)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x110+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x110+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x110+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x110+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x110+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x110+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x110+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x110+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x110)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x110+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x110+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x110+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR2"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x120)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x120+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x120+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x120+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x120+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x120+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x120+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x120+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x120+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x120)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x120+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x120+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x120+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR3"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x130)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x130+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x130+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x130+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x130+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x130+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x130+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x130+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x130+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x130)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x130+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x130+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x130+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR4"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x140)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x140+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x140+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x140+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x140+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x140+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x140+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x140+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x140+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x140)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x140+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x140+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x140+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR5"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x150)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x150+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x150+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x150+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x150+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x150+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x150+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x150+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x150+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x150)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x150+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x150+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x150+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR6"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x160)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x160+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x160+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x160+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x160+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x160+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x160+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x160+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x160+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x160)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x160+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x160+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x160+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR7"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x170)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x170+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x170+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x170+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x170+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x170+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x170+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x170+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x170+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x170)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x170+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x170+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x170+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR8"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x180)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x180+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x180+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x180+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x180+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x180+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x180+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x180+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x180+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x180)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x180+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x180+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x180+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR9"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x190)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x190+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x190+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x190+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x190+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x190+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x190+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x190+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x190+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x190)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x190+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x190+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x190+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR10"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1A0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1A0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1A0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1A0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1A0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1A0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1A0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1A0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1A0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1A0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1A0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1A0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1A0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR11"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1B0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1B0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1B0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1B0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1B0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1B0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1B0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1B0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1B0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1B0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1B0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1B0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1B0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR12"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1C0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1C0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1C0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1C0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1C0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1C0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1C0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1C0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1C0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1C0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1C0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1C0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1C0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR13"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1D0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1D0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1D0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1D0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1D0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1D0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1D0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1D0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1D0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1D0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1D0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1D0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1D0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR14"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1E0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1E0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1E0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1E0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1E0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1E0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1E0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1E0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1E0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1E0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1E0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1E0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1E0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR15"
if (((d.b(ad:0x47401400+0x60))&0x4)==0x4)
group.word (0x1F0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1F0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1F0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1F0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1F0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1F0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1F0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1F0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1F0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1F0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1F0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1F0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1F0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree.end
width 0xb
tree.end
tree "USB 1 Mentor Core and FIFO Registers"
base ad:0x47401C00
width 0xa
tree "Common USB Registers"
wgroup.byte 0x00++0x0
line.byte 0x0 "FADDR,Function Address Register"
hexmask.byte 0x0 0.--6. 1. " FUNCADDR ,7_bit address of the peripheral part of the transaction"
group.byte 0x01++0x00
line.byte 0x0 "POWER,Power Management Register"
bitfld.byte 0x0 7. " ISOUPDATE ,Waiting for SOF token" "No wait,Wait"
bitfld.byte 0x0 6. " SOFTCONN ,Soft Connect/Disconnect feature" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 5. " HSEN ,High-speed mode negotiation enable" "Disabled,Enabled"
bitfld.byte 0x0 4. " HSMODE ,High-speed mode" "Full speed,High speed"
textline " "
bitfld.byte 0x0 3. " RESET ,Reset" "No reset,Reset"
bitfld.byte 0x0 2. " RESUME ,Resume in suspend mode" "No resume,Resume"
textline " "
bitfld.byte 0x0 1. " SUSPENDM ,Suspend mode" "No effect,Suspend mode"
bitfld.byte 0x0 0. " ENSUSPM ,SUSPENDM output enable" "Disabled,Enabled"
rgroup.word 0x02++0x7
line.word 0x0 "INTRTX,Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 15"
bitfld.word 0x0 15. " EP15TX ,Tx Endpoint 15 interrupt active" "Not active,Active"
bitfld.word 0x0 14. " EP14TX ,Tx Endpoint 14 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 13. " EP13TX ,Tx Endpoint 13 interrupt active" "Not active,Active"
bitfld.word 0x0 2. " EP12TX ,Tx Endpoint 12 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 11. " EP11TX ,Tx Endpoint 11 interrupt active" "Not active,Active"
bitfld.word 0x0 10. " EP10TX ,Tx Endpoint 10 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 9. " EP9TX ,Tx Endpoint 9 interrupt active" "Not active,Active"
bitfld.word 0x0 8. " EP8TX ,Tx Endpoint 8 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 7. " EP7TX ,Tx Endpoint 7 interrupt active" "Not active,Active"
bitfld.word 0x0 6. " EP6TX ,Tx Endpoint 6 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 5. " EP5TX ,Tx Endpoint 5 interrupt active" "Not active,Active"
bitfld.word 0x0 4. " EP4TX ,Tx Endpoint 4 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 3. " EP3TX ,Tx Endpoint 3 interrupt active" "Not active,Active"
bitfld.word 0x0 2. " EP2TX ,Tx Endpoint 2 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x0 1. " EP1TX ,Tx Endpoint 1 interrupt active" "Not active,Active"
bitfld.word 0x0 0. " EP0 ,Endpoint 0 interrupt active" "Not active,Active"
line.word 0x2 "INTRRX,Interrupt Register for Receive Endpoints 1 to 15"
bitfld.word 0x02 15. " EP15RX ,Rx Endpoint 15 interrupt active" "Not active,Active"
bitfld.word 0x02 14. " EP14RX ,Rx Endpoint 14 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 13. " EP13RX ,Rx Endpoint 13 interrupt active" "Not active,Active"
bitfld.word 0x02 2. " EP12RX ,Rx Endpoint 12 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 11. " EP11RX ,Rx Endpoint 11 interrupt active" "Not active,Active"
bitfld.word 0x02 10. " EP10RX ,Rx Endpoint 10 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 9. " EP9RX ,Rx Endpoint 9 interrupt active" "Not active,Active"
bitfld.word 0x02 8. " EP8RX ,Rx Endpoint 8 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 7. " EP7RX ,Rx Endpoint 7 interrupt active" "Not active,Active"
bitfld.word 0x02 6. " EP6RX ,Rx Endpoint 6 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 5. " EP5RX ,Rx Endpoint 5 interrupt active" "Not active,Active"
bitfld.word 0x02 4. " EP4RX ,Receive Endpoint 4 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 3. " EP3RX ,Receive Endpoint 3 interrupt active" "Not active,Active"
bitfld.word 0x02 2. " EP2RX ,Receive Endpoint 2 interrupt active" "Not active,Active"
textline " "
bitfld.word 0x02 1. " EP1RX ,Receive Endpoint 1 interrupt active" "Not active,Active"
line.word 0x04 "INTRTXE,Interrupt Enable Register for INTRTX"
bitfld.word 0x04 15. " EP15TX ,Tx Endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 14. " EP14TX ,Tx Endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 13. " EP13TX ,Tx Endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 2. " EP12TX ,Tx Endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 11. " EP11TX ,Tx Endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 10. " EP10TX ,Tx Endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 9. " EP9TX ,Tx Endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 8. " EP8TX ,Tx Endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 7. " EP7TX ,Tx Endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 6. " EP6TX ,Tx Endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 5. " EP5TX ,Tx Endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 4. " EP4TX ,Tx Endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 3. " EP3TX ,Tx Endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 2. " EP2TX ,Tx Endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x04 1. " EP1TX ,Tx Endpoint 1 interrupt enable" "Disabled,Enabled"
bitfld.word 0x04 0. " EP0 ,Endpoint 0 interrupt enable" "Disabled,Enabled"
line.word 0x06 "INTRRXE,Interrupt Enable Register for INTRRX"
bitfld.word 0x06 15. " EP15RX ,Rx Endpoint 15 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 14. " EP14RX ,Rx Endpoint 14 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 13. " EP13RX ,Rx Endpoint 13 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 2. " EP12RX ,Rx Endpoint 12 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 11. " EP11RX ,Rx Endpoint 11 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 10. " EP10RX ,Rx Endpoint 10 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 9. " EP9RX ,Rx Endpoint 9 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 8. " EP8RX ,Rx Endpoint 8 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 7. " EP7RX ,Rx Endpoint 7 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 6. " EP6RX ,Rx Endpoint 6 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 5. " EP5RX ,Rx Endpoint 5 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 4. " EP4RX ,Receive Endpoint 4 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 3. " EP3RX ,Receive Endpoint 3 interrupt enable" "Disabled,Enabled"
bitfld.word 0x06 2. " EP2RX ,Receive Endpoint 2 interrupt enable" "Disabled,Enabled"
textline " "
bitfld.word 0x06 1. " EP1RX ,Receive Endpoint 1 interrupt enable" "Disabled,Enabled"
hgroup.byte 0x0a++0x0
hide.byte 0x0 "INTRUSB,Interrupt Register for Common USB Interrupts"
in
group.byte 0x0b++0x0
line.byte 0x0 "INTRUSBE,Interrupt Enable Register for INTRUSB"
bitfld.byte 0x0 7. " VBUSERR ,Vbus error interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 6. " SESSREQ ,Session request interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 5. " DISCON ,Disconnect interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 4. " CONN ,Connect interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 3. " SOF ,Start of frame interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 2. " RESET_BABBLE ,Reset interrupt enable" "Disabled,Enabled"
textline " "
bitfld.byte 0x0 1. " RESUME ,Resume interrupt enable" "Disabled,Enabled"
bitfld.byte 0x0 0. " SUSPEND ,Suspend interrupt enable" "Disabled,Enabled"
rgroup.word 0x0c++0x1
line.word 0x0 "FRAME,Frame Number Register"
hexmask.word 0x0 0.--10. 1. " FRAMENUMBER ,Last received frame number"
group.byte 0x0e++0x1
line.byte 0x0 "INDEX,Index Register for Selecting the Endpoint Status and Control Registers"
bitfld.byte 0x0 0.--3. " EPSEL ,Endpoint control/status register select" "EP 0,EP 1,EP 2,EP 3,EP 4,EP 5,EP 6,EP 7,EP 8,EP 9,EP 10,EP 11,EP 12,EP 13,EP 14,EP 15"
line.byte 0x1 "TESTMODE,Register to Enable the USB 2.0 Test Modes"
bitfld.byte 0x1 7. " FORCE_HOST ,Force Host mode" "Normal,Host"
bitfld.byte 0x1 6. " FIFO_ACCESS ,Transfer packet EP0 Tx FIFO to EP0 Receive FIFO" "Not transferred,Transferred"
textline " "
bitfld.byte 0x1 5. " FORCE_FS ,Force full-speed mode" "Normal,Full speed"
bitfld.byte 0x1 4. " FORCE_HS ,Force high-speed mode" "Normal,High speed"
textline " "
bitfld.byte 0x1 3. " TEST_PACKET ,Test_Packet test mode" "Normal,Test_Packet"
bitfld.byte 0x1 2. " TEST_K ,Test_K test mode" "Normal,Test_K"
textline " "
bitfld.byte 0x1 1. " TEST_J ,Test_J test mode" "Normal,Test_J"
bitfld.byte 0x1 0. " TEST_SE0_NAK ,Test_SE0_NAK test mode" "Normal,Test_SE0_NAK"
tree.end
width 17.
tree "Indexed Region Registers"
if ((((d.b(ad:0x47401C00+0x60))&0x4)==0x4)&&(((d.b(ad:0x47401C00+0x0e))&0xf)==0x0))
group.word 0x12++0x1
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
textline " "
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
textline " "
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
group.byte 0x1a++0x0
line.byte 0x00 "HOST_TYPE0,Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
group.byte 0x1b++0x0
line.byte 0x00 "HOST_NAKLIMIT0,NAKLIMIT0 Register"
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
rgroup.byte 0x1f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
elif ((((d.b(ad:0x47401C00+0x60))&0x4)==0x0)&&(((d.b(ad:0x47401C00+0x0e))&0xf)==0x0))
group.word 0x12++0x1
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
textline " "
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
textline " "
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
textline " "
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
rgroup.byte 0x1f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
elif ((((d.b(ad:0x47401C00+0x60))&0x4)==0x4)&&((((d.b(ad:0x47401C00+0x0e))&0xf)!=0x0)))
group.word 0x10++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word 0x12++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not received,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word 0x14++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word 0x16++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x18++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte 0x1a++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1b++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte 0x1c++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x1d++0x0
line.byte 0x00 "HOST_RXINTERVAL,Recieve Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word 0x10++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word 0x12++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
textline " "
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word 0x14++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word 0x16++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENTSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
width 12.
tree "FIFOs"
hgroup.long 0x20++0x3
hide.long 0x00 "FIFO0,Transmit and Receive FIFO Register for Endpoint 0"
in
hgroup.long 0x24++0x3
hide.long 0x00 "FIFO1,Transmit and Receive FIFO Register for Endpoint 1"
in
hgroup.long 0x28++0x3
hide.long 0x00 "FIFO2,Transmit and Receive FIFO Register for Endpoint 2"
in
hgroup.long 0x2C++0x3
hide.long 0x00 "FIFO3,Transmit and Receive FIFO Register for Endpoint 3"
in
hgroup.long 0x30++0x3
hide.long 0x00 "FIFO4,Transmit and Receive FIFO Register for Endpoint 4"
in
hgroup.long 0x34++0x3
hide.long 0x00 "FIFO5,Transmit and Receive FIFO Register for Endpoint 5"
in
hgroup.long 0x38++0x3
hide.long 0x00 "FIFO6,Transmit and Receive FIFO Register for Endpoint 6"
in
hgroup.long 0x3C++0x3
hide.long 0x00 "FIFO7,Transmit and Receive FIFO Register for Endpoint 7"
in
hgroup.long 0x40++0x3
hide.long 0x00 "FIFO8,Transmit and Receive FIFO Register for Endpoint 8"
in
hgroup.long 0x44++0x3
hide.long 0x00 "FIFO9,Transmit and Receive FIFO Register for Endpoint 9"
in
hgroup.long 0x48++0x3
hide.long 0x00 "FIFO10,Transmit and Receive FIFO Register for Endpoint 10"
in
hgroup.long 0x4C++0x3
hide.long 0x00 "FIFO11,Transmit and Receive FIFO Register for Endpoint 11"
in
hgroup.long 0x50++0x3
hide.long 0x00 "FIFO12,Transmit and Receive FIFO Register for Endpoint 12"
in
hgroup.long 0x54++0x3
hide.long 0x00 "FIFO13,Transmit and Receive FIFO Register for Endpoint 13"
in
hgroup.long 0x58++0x3
hide.long 0x00 "FIFO14,Transmit and Receive FIFO Register for Endpoint 14"
in
hgroup.long 0x5C++0x3
hide.long 0x00 "FIFO15,Transmit and Receive FIFO Register for Endpoint 15"
in
tree.end
tree "Additional Control and Configuration Registers"
if ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x80))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
textline " "
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
textline " "
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
elif ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x04)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x00))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 6. " FSDEV ,Full speed or high speed detected" "Not detected,Detected"
textline " "
bitfld.byte 0x00 5. " LSDEV ,Low speed detected" "Not detected,Detected"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
elif ((((data.byte(ad:0x47401C00+0x60))&0x04)==0x00)&&(((data.byte(ad:0x47401C00+0x60))&0x80)==0x80))
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 1. " HOSTREQ ,Host Negotiation initiated" "Not initiated,Initiated"
textline " "
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
else
group.byte 0x60++0x0
line.byte 0x00 "DEVCTL,OTG Device Control Register"
bitfld.byte 0x00 7. " BDEVICE ,USB controller is operating as the 'A' device or the 'B'" "A device,B device"
bitfld.byte 0x00 3.--4. " VBUS ,Current VBus level" "Below Session End,Above Session End,Above AValid,Above VBusValid"
textline " "
bitfld.byte 0x00 2. " HOSTMODE ,USB controller is acting as a Host" "Peripheral,Host"
bitfld.byte 0x00 0. " SESSION ,Session start" "Started,Ended"
endif
sif (cpuis("DM814?DSP")||cpuis("DRA62*"))
if (((data.byte(ad:0x47401C00+0x62))&(0x10))==0x0)
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
else
rgroup.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
endif
else
if (((data.byte(ad:0x47401C00+0x62))&(0x10))==0x0)
group.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
else
group.byte 0x62++0x0 "Dynamic FIFO Control"
line.byte 0x00 "TXFIFOSZ ,Transmit Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
endif
endif
if (((data.byte(ad:0x47401C00+0x63))&0x10)==0x0)
group.byte 0x63++0x0
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38"
else
group.byte 0x63++0x0
line.byte 0x00 "RXFIFOSZ ,Receive Endpoint FIFO Size"
bitfld.byte 0x00 4. " DPB ,Double packet buffering is enabled" "Single,Double"
bitfld.byte 0x00 0.--3. " SZ ,Maximum packet size allowed" "6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36"
endif
group.word 0x64++0x1
line.word 0x00 "TXFIFOADDR,Transmit Endpoint FIFO Address"
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
group.word 0x66++0x1
line.word 0x00 "RXFIFOADDR,Receive Endpoint FIFO Address"
hexmask.word 0x00 0.--12. 1. " ADDR ,Start address of endpoint FIFO"
group.word 0x6C++0x1
line.word 0x00 "HWVERS,Hardware Version Register"
bitfld.word 0x00 15. " RC ,RTL version from which the core hardware was generated" "Release candidate,Full release"
bitfld.word 0x00 10.--14. " REVMAJ ,Major revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
textline " "
hexmask.word 0x00 0.--9. 1. " REVMIN ,Minor revision"
tree.end
width 12.
tree "Target Endpoint Control"
tree "EPTRG0"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0x80)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x80+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x80+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x80)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x80+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x80+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG1"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0x88)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x88+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x88+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x88)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x88+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x88+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG2"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0x90)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x90+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x90+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x90)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x90+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x90+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG3"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0x98)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x98+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0x98+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0x98)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0x98+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0x98+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG4"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xA0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xA0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xA0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xA0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG5"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xA8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xA8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xA8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xA8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xA8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG6"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xB0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xB0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xB0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xB0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG7"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xB8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xB8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xB8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xB8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xB8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG8"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xC0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xC0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xC0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xC0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG9"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xC8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xC8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xC8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xC8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xC8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG10"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xD0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xD0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xD0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xD0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG11"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xD8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xD8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xD8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xD8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xD8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG12"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xE0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xE0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xE0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xE0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG13"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xE8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xE8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xE8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xE8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xE8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG14"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xF0)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF0+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF0+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xF0)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xF0+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xF0+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree "EPTRG15"
if ((d.b((ad:0x47401C00+0x60))&0x4)==0x4)
group.byte (0xF8)++0x0
line.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hexmask.byte 0x00 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF8+0x2)++0x2
line.byte 0x0 "TXHUBADDR,Transmit Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
line.byte 0x02 "RXFUNCADDR,Receive Function Address"
hexmask.byte 0x02 0.--6. 1. " FUNCADDR ,Address of target function"
group.byte (0xF8+0x6)++0x1
line.byte 0x0 "RXHUBADDR,Receive Hub Address"
bitfld.byte 0x0 7. " MULT_TRANS ,Multiple transaction translator" "Single,Multiple"
hexmask.byte 0x0 0.--6. 1. " HUBADDR ,Address of hub"
line.byte 0x01 "RXHUBPORT,Receive Hub Port"
hexmask.byte 0x01 0.--6. 1. " HUBPORT ,Port number of the hub"
else
hgroup.byte (0xF8)++0x0
hide.byte 0x00 "TXFUNCADDR,Transmit Function Address"
hgroup.byte (0xF8+0x2)++0x2
hide.byte 0x00 "TXHUBADDR,Transmit Hub Address"
hide.byte 0x01 "TXHUBPORT,Transmit Hub Port"
hide.byte 0x02 "RXFUNCADDR,Receive Function Address"
hgroup.byte (0xF8+0x6)++0x1
hide.byte 0x00 "RXHUBADDR,Receive Hub Address"
hide.byte 0x01 "RXHUBPORT,Receive Hub Port"
endif
tree.end
tree.end
width 17.
tree "Control and Status Registers for Endpoints"
tree "EOCSR0"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word 0x102++0x1
line.word 0x00 "HOST_CSR0,Control Status Register for Endpoint 0 in Host Mode"
bitfld.word 0x00 11. " DISPING ,PING tokens in data and status phases" "Enabled,Disabled"
textline " "
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOG ,Current state of EP0 data toggle" "Low,High"
textline " "
bitfld.word 0x00 8. " FLUSHFIFO ,Endpoint 0 FIFO next packet flush" "No effect,Flushed"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Endpoint 0 halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " STATUSPKT ,Status stage transaction" "No effect,Performed"
bitfld.word 0x00 5. " REQPKT ,IN transaction requested" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " ERROR ,Transaction perfrorm error" "No error,Error"
bitfld.word 0x00 3. " SETUPPKT ,SETUP token send" "Not sent,Sent"
textline " "
bitfld.word 0x00 2. " RXSTALL ,STALL handshake received" "Not received,Received"
bitfld.word 0x00 1. " TXPKTRDY ,FIFO data packet load" "Not loaded,Loaded"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word 0x108++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
group.byte 0x10a++0x0
line.byte 0x00 "HOST_TYPE0,Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
group.byte 0x10b++0x0
line.byte 0x00 "HOST_NAKLIMIT0,NAKLimit0 Register"
bitfld.byte 0x00 0.--4. " EP0NAKLIMIT ,Number of frames/microframes after which Endpoint 0 should time out" "Disabled,Disabled,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
rgroup.byte 0x10f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
else
group.word 0x102++0x1
line.word 0x00 "PERI_CSR0,Control Status Register for Endpoint 0 in Peripheral Mode"
bitfld.word 0x00 8. " FLUSHFIFO ,FIFO flush" "Not flushed,Flushed"
bitfld.word 0x00 7. " SERV_SETUPEND ,Clear SETUPEND bit" "No effect,Cleared"
textline " "
bitfld.word 0x00 6. " SERV_RXPKTRDY ,Clear RXPKTRDY bit" "No effect,Cleared"
bitfld.word 0x00 5. " SENDSTALL ,Terminate the current transaction" "Not terminated,Terminated"
textline " "
bitfld.word 0x00 4. " SETUPEND ,Control transaction ends" "Not ended,Ended"
bitfld.word 0x00 3. " DATAEND ,Data end" "Not ended,Ended"
textline " "
bitfld.word 0x00 2. " SENTSTALL ,STALL handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 1. " TXPKTRDY ,Transmit packet ready" "Not ready,Ready"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Packet received" "Not received,Received"
rgroup.word 0x108++0x1
line.word 0x00 "COUNT0,Count 0 Register"
hexmask.word.byte 0x00 0.--6. 1. " EP0RXCOUNT ,Number of received data bytes in the Endpoint 0 FIFO"
rgroup.byte 0x10f++0x0
line.byte 0x00 "CONFIGDATA,Configuration Data Register"
bitfld.byte 0x00 7. " MPRXE ,Indicates automatic amalgamation of bulk packets" "Not selected,Selected"
bitfld.byte 0x00 6. " MPTXE ,Indicates automatic splitting of bulk packets" "Not selected,Selected"
textline " "
bitfld.byte 0x00 5. " BIGENDIAN ,Indicates endian ordering" "Little-endian,Big-endian"
bitfld.byte 0x00 4. " HBRXE ,Indicates high-bandwidth Rx ISO endpoint support" "Not selected,Selected"
textline " "
bitfld.byte 0x00 3. " HBTXE ,Indicates high-bandwidth Tx ISO endpoint support" "Not selected,Selected"
bitfld.byte 0x00 2. " DYNFIFO ,Indicates dynamic FIFO sizing" "Not selected,Selected"
textline " "
bitfld.byte 0x00 1. " SOFTCONE ,Indicates soft connect/disconnect" "Not selected,Selected"
bitfld.byte 0x00 0. " UTMIDATAWIDTH ,Indicates selected UTMI data width" "8 bits,16 bits"
endif
tree.end
tree "EOCSR1"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x110)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x110+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x110+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x110+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x110+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x110+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x110+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x110+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x110+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x110)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x110+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x110+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x110+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR2"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x120)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x120+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x120+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x120+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x120+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x120+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x120+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x120+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x120+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x120)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x120+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x120+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x120+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR3"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x130)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x130+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x130+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x130+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x130+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x130+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x130+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x130+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x130+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x130)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x130+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x130+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x130+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR4"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x140)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x140+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x140+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x140+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x140+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x140+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x140+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x140+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x140+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x140)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x140+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x140+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x140+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR5"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x150)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x150+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x150+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x150+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x150+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x150+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x150+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x150+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x150+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x150)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x150+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x150+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x150+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR6"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x160)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x160+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x160+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x160+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x160+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x160+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x160+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x160+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x160+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x160)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x160+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x160+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x160+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR7"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x170)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x170+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x170+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x170+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x170+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x170+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x170+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x170+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x170+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x170)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x170+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x170+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x170+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR8"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x180)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x180+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x180+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x180+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x180+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x180+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x180+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x180+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x180+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x180)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x180+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x180+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x180+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR9"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x190)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x190+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x190+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x190+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x190+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x190+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x190+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x190+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x190+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x190)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x190+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x190+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x190+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR10"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1A0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1A0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1A0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1A0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1A0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1A0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1A0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1A0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1A0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1A0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1A0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1A0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1A0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR11"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1B0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1B0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1B0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1B0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1B0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1B0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1B0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1B0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1B0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1B0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1B0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1B0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1B0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR12"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1C0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1C0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1C0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1C0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1C0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1C0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1C0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1C0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1C0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1C0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1C0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1C0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1C0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR13"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1D0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1D0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1D0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1D0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1D0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1D0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1D0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1D0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1D0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1D0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1D0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1D0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1D0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR14"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1E0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1E0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1E0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1E0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1E0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1E0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1E0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1E0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1E0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1E0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1E0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1E0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1E0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree "EOCSR15"
if (((d.b(ad:0x47401C00+0x60))&0x4)==0x4)
group.word (0x1F0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1F0+0x2)++0x1
line.word 0x00 "HOST_TXCSR,Control Status Register for Host Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 9. " DATATOGWREN ,DATATOG bit write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 8. " DATATOG ,Current state of Tx EP data toggle" "Low,High"
bitfld.word 0x00 7. " NAK_TIMEOUT ,Tx endpoint halted" "Continue,Halted"
textline " "
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
bitfld.word 0x00 5. " RXSTALL ,Stall handshake received" "Not recieved,Received"
textline " "
bitfld.word 0x00 4. " SETUPPKT ,Setup token send" "Not sent,Sent"
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
textline " "
bitfld.word 0x00 2. " ERROR ,No handshake receive" "No error,Error"
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
textline " "
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1F0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1F0+0x6)++0x1
line.word 0x00 "HOST_RXCSR,Control Status Register for Host Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " AUTOREQ ,Auto request" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request for Receive endpoints" "Not requested,Requested"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 10. " DATATOGWREN ,DATATOG write enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 9. " DATATOG ,Current state of RX EP data toggle" "Low,High"
bitfld.word 0x00 7. " CLRDATATOG ,Reset endpoint data toggle" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " RXSTALL ,Stall handshake Received" "Not received,Received"
bitfld.word 0x00 5. " REQPKT ,IN transaction request" "Not requested,Requested"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERR_NAKTIMEOUT ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " ERROR ,No data packet received" "No Error,Error"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
rgroup.word (0x1F0+0x8)++0x1
line.word 0x00 "RXCOUNT,Receive Count Register"
hexmask.word 0x00 0.--12. 1. " EPRXCOUNT ,Number of received data bytes in the packet in the Receive FIFO"
group.byte (0x1F0+0xa)++0x0
line.byte 0x00 "HOST_TXTYPE,Transmit Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " TENDPN ,Endpoint number contained in the transmit endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1F0+0xb)++0x0
line.byte 0x00 "HOST_TXINTERVAL,Transmit Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
group.byte (0x1F0+0xc)++0x0
line.byte 0x00 "HOST_RXTYPE,Receive Type Register"
bitfld.byte 0x00 6.--7. " SPEED ,Operating speed of target device" "Illegal,High,Full,Low"
bitfld.byte 0x00 4.--5. " PROT ,Required protocol for the transmit endpoint" "Control,Isochronous,Bulk,Interrupt"
textline " "
bitfld.byte 0x00 0.--3. " RENDPN ,Endpoint number contained in the Receive endpoint descriptor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte (0x1F0+0xd)++0x0
line.byte 0x00 "HOST_RXINTERVAL,Receive Interval Register"
hexmask.byte 0x00 0.--7. 1. " POLINTVL_NAKLIMIT ,Polling interval for currenlty selected endpoint"
else
group.word (0x1F0)++0x1
line.word 0x00 "TXMAXP,Maximum Packet Size for Peripheral/Host Transmit Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum payload transmitted in a single transaction"
group.word (0x1F0+0x2)++0x1
line.word 0x00 "PERI_TXCSR,Control Status Register for Peripheral Transmit Endpoint"
bitfld.word 0x00 15. " AUTOSET ,Auto set" "Disabled,Enabled"
textline " "
bitfld.word 0x00 14. " ISO ,Isochronous transfer enable" "Disabled,Enabled"
bitfld.word 0x00 13. " MODE ,Tx endpoint direction enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 12. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 11. " FRCDATATOG ,Force endpoint data toggle" "No effect,Forced"
textline " "
bitfld.word 0x00 10. " DMAMODE ,DMA mode" "Disabled,Enabled"
bitfld.word 0x00 6. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 5. " TXSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 4. " SENDSTALL ,Stall handshake to IN token issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 3. " FLUSHFIFO ,Next packet from endpoint Tx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 2. " UNDERRUN ,IN token received" "Not received,Received"
textline " "
bitfld.word 0x00 1. " FIFONOTEMPTY ,FIFO not empty" "Empty,Not empty"
bitfld.word 0x00 0. " TXPKTRDY ,Data packet loaded into FIFO" "Not loaded,Loaded"
group.word (0x1F0+0x4)++0x1
line.word 0x00 "RXMAXP,Maximum Packet Size for Peripheral Host Receive Endpoint"
hexmask.word 0x00 0.--10. 1. " MAXPAYLOAD ,Maximum amount of data that can be transferred through the selected endpoint"
group.word (0x1F0+0x6)++0x1
line.word 0x00 "PERI_RXCSR,Control Status Register for Peripheral Receive Endpoint"
bitfld.word 0x00 15. " AUTOCLEAR ,Auto clear" "Disabled,Enabled"
bitfld.word 0x00 14. " ISO ,Receive endpoint for Isochronous transfers enable" "Disabled,Enabled"
textline " "
bitfld.word 0x00 13. " DMAEN ,DMA request enable" "Disabled,Enabled"
bitfld.word 0x00 12. " DISNYET ,NYET handshake disable" "Enabled,Disabled"
textline " "
bitfld.word 0x00 11. " DMAMODE ,DMA mode (should always be 0)" "Disabled,Enabled"
bitfld.word 0x00 7. " CLRDATATOG ,Endpoint data toggle reset" "No reset,Reset"
textline " "
bitfld.word 0x00 6. " SENDSTALL ,Stall handshake transmitted" "Not transmitted,Transmitted"
bitfld.word 0x00 5. " SENDSTALL ,Stall handshake issue" "Not issued,Issued"
textline " "
bitfld.word 0x00 4. " FLUSHFIFO ,Next packet from endpoint Rx FIFO flush" "No effect,Flushed"
bitfld.word 0x00 3. " DATAERROR ,CRC or bit-stuff error" "No error,Error"
textline " "
bitfld.word 0x00 2. " OVERRUN ,Rx FIFO overrun" "No overrun,Overrun"
bitfld.word 0x00 1. " FIFOFULL ,FIFO full" "Not full,Full"
textline " "
bitfld.word 0x00 0. " RXPKTRDY ,Data packet received" "Not received,Received"
endif
tree.end
tree.end
width 0xb
tree.end
tree.end
tree.end
textline ""
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